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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dapple.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
15 This currently includes devices based on the "M1" SoC:
17 - Mac mini (M1, 2020)
18 - MacBook Pro (13-inch, M1, 2020)
19 - MacBook Air (M1, 2020)
20 - iMac (24-inch, M1, 2021)
22 Devices based on the "M2" SoC:
[all …]
H A Drealtek.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andreas Färber <afaerber@suse.de>
17 # RTD1195 SoC based boards
18 - items:
19 - enum:
20 - mele,x1000 # MeLE X1000
21 - realtek,horseradish # Realtek Horseradish EVB
22 - const: realtek,rtd1195
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H A Damlogic,scpi.txt3 ----------------------------------------------------------
6 - compatible : should be "amlogic,meson-gxbb-scpi"
9 ------------------------------------
12 - compatible : should be "amlogic,meson-gxbb-sram"
14 Each sub-node represents the reserved area for SCPI.
16 Required sub-node properties:
17 - compatible : should be "amlogic,meson-gxbb-scp-shmem" for SRAM based shared
18 memory on Amlogic GXBB SoC.
20 Sensor bindings for the sensors based on SCPI Message Protocol
21 --------------------------------------------------------------
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/freebsd/sys/contrib/device-tree/Bindings/ptp/
H A Dbrcm,ptp-dte.txt1 * Broadcom Digital Timing Engine(DTE) based PTP clock
4 - compatible: should contain the core compatibility string
5 and the SoC compatibility string. The SoC
6 compatibility string is to handle SoC specific
9 "brcm,ptp-dte"
10 SoC compatibility strings:
11 "brcm,iproc-ptp-dte" - for iproc based SoC's
12 - reg: address and length of the DTE block's NCO registers
16 ptp: ptp-dte@180af650 {
17 compatible = "brcm,iproc-ptp-dte", "brcm,ptp-dte";
/freebsd/sys/contrib/device-tree/Bindings/arm/ti/
H A Dk3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments K3 Multicore SoC architecture
10 - Nishanth Menon <nm@ti.com>
13 Platforms based on Texas Instruments K3 Multicore SoC architecture
22 - description: K3 AM62A7 SoC
24 - enum:
25 - ti,am62a7-sk
26 - const: ti,am62a7
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H A Dk3.txt1 Texas Instruments K3 Multicore SoC architecture device tree bindings
2 --------------------------------------------------------------------
4 Platforms based on Texas Instruments K3 Multicore SoC architecture
8 ----
10 Each device tree root node must specify which exact SoC in K3 Multicore SoC
13 - AM654
16 - J721E
20 ------
23 of the following board-specific compatible values:
25 - AM654 EVM
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/freebsd/sys/contrib/device-tree/Bindings/rtc/
H A Disil,isl12057.txt8 ("wakeup-source") to handle the specific use-case found
9 on at least three in-tree users of the chip (NETGEAR ReadyNAS 102, 104
10 and 2120 ARM-based NAS); On those devices, the IRQ#2 pin of the chip
12 to the SoC but to a PMIC. It allows the device to be powered up when
15 be set when the IRQ#2 pin of the chip is not connected to the SoC but
20 - "compatible": must be "isil,isl12057"
21 - "reg": I2C bus address of the device
25 - "wakeup-source": mark the chip as a wakeup source, independently of
26 the availability of an IRQ line connected to the SoC.
37 Example isl12057 node with IRQ#2 pin connected to main SoC via MPP6 (note
[all …]
H A Drtc-mt7622.txt1 Device-Tree bindings for MediaTek SoC based RTC
4 - compatible : Should be
5 "mediatek,mt7622-rtc", "mediatek,soc-rtc" : for MT7622 SoC
6 - reg : Specifies base physical address and size of the registers;
7 - interrupts : Should contain the interrupt for RTC alarm;
8 - clocks : Specifies list of clock specifiers, corresponding to
9 entries in clock-names property;
10 - clock-names : Should contain "rtc" entries
15 compatible = "mediatek,mt7622-rtc",
16 "mediatek,soc-rtc";
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/freebsd/sys/contrib/device-tree/Bindings/arm/marvell/
H A Darmada-7k-8k.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR X11)
3 ---
4 $id: http://devicetree.org/schemas/arm/marvell/armada-7k-8k.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gregory CLEMENT <gregory.clement@bootlin.com>
18 - description: Armada 7020 SoC
20 - const: marvell,armada7020
21 - const: marvell,armada-ap806-dual
22 - const: marvell,armada-ap806
24 - description: Armada 7040 SoC
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/freebsd/sys/contrib/device-tree/Bindings/mips/
H A Dralink.txt1 Ralink MIPS SoC device tree bindings
5 Each device tree must specify a compatible value for the Ralink SoC
9 ralink,rt2880-soc
10 ralink,rt3050-soc
11 ralink,rt3052-soc
12 ralink,rt3350-soc
13 ralink,rt3352-soc
14 ralink,rt3883-soc
15 ralink,rt5350-soc
16 ralink,mt7620a-soc
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H A Dralink.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ralink SoC based Platforms
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 Boards with a Ralink SoC shall have the following properties.
20 - description: Boards with Ralink RT2880 SoC
22 - enum:
23 - ralink,rt2880-eval-board
24 - const: ralink,rt2880-soc
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/freebsd/sys/contrib/device-tree/Bindings/arm/nuvoton/
H A Dnuvoton,ma35d1.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton MA35 series SoC based platforms
10 - Jacky Huang <ychuang3@nuvoton.com>
13 Boards with an ARMv8 based Nuvoton MA35 series SoC shall have
22 - description: MA35D1 based boards
24 - enum:
25 - nuvoton,ma35d1-iot
26 - nuvoton,ma35d1-som
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dbrcm,iproc-gpio.txt5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
8 based SoCs
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
22 available on a variety of Broadcom SoCs, including some BCM3xxx, MIPS based
23 Broadband SoC (BCM63xx), ARM based Broadband SoC (BCMBCA) and iProc/Cygnus.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dthead.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
H A Dsifive.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive SoC-based boards
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 SiFive SoC-based boards
21 - items:
22 - enum:
23 - sifive,hifive-unleashed-a00
[all …]
H A Dsophgo.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo SoC-based boards
10 - Chao Wei <chao.wei@sophgo.com>
11 - Chen Wang <unicorn_wang@outlook.com>
14 Sophgo SoC-based boards
21 - items:
22 - enum:
23 - milkv,duo
[all …]
H A Dstarfive.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive SoC-based boards
10 - Michael Zhu <michael.zhu@starfivetech.com>
11 - Drew Fustini <drew@beagleboard.org>
14 StarFive SoC-based boards
21 - items:
22 - enum:
23 - beagle,beaglev-starlight-jh7100-r0
[all …]
H A Dmicrochip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PolarFire SoC-based boards
10 - Conor Dooley <conor.dooley@microchip.com>
11 - Daire McNamara <daire.mcnamara@microchip.com>
14 Microchip PolarFire SoC-based boards
21 - items:
22 - enum:
23 - microchip,mpfs-icicle-reference-rtlv2203
[all …]
H A Dcanaan.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Canaan SoC-based boards
10 - Damien Le Moal <dlemoal@kernel.org>
13 Canaan Kendryte K210 SoC-based boards
20 - items:
21 - const: sipeed,maix-bit
22 - const: sipeed,maix-bitm
23 - const: canaan,kendryte-k210
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dbrcm,bcm63xx-hsspi.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Broadband SoC High Speed SPI controller
10 - William Zhang <william.zhang@broadcom.com>
11 - Kursad Oney <kursad.oney@broadcom.com>
12 - Jonas Gorski <jonas.gorski@gmail.com>
15 Broadcom Broadband SoC supports High Speed SPI master controller since the
16 early MIPS based chips such as BCM6328 and BCM63268. This initial rev 1.0
[all …]
/freebsd/sys/contrib/device-tree/Bindings/
H A Dwriting-bindings.rst1 .. SPDX-License-Identifier: GPL-2.0
11 Documentation/devicetree/bindings/submitting-patches.rst
17 - DO attempt to make bindings complete even if a driver doesn't support some
21 - DON'T refer to Linux or "device driver" in bindings. Bindings should be
22 based on what the hardware has, not what an OS and driver currently support.
24 - DO use node names matching the class of the device. Many standard names are
27 - DO check that the example matches the documentation especially after making
30 - DON'T create nodes just for the sake of instantiating drivers. Multi-function
34 - DON'T use 'syscon' alone without a specific compatible string. A 'syscon'
42 - DO make 'compatible' properties specific. DON'T use wildcards in compatible
[all …]
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Ds3c6400.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's S3C6400 SoC device tree source
7 * Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400
8 * based board files can include this file and provide values for board specific
12 * S3C6400 SoC. As device tree coverage for S3C6400 increases, additional
23 valid-mask = <0xfffffe1f>;
24 valid-wakeup-mask = <0x00200004>;
28 valid-mask = <0xffffffff>;
29 valid-wakeup-mask = <0x53020000>;
32 &soc {
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dtwl-family.txt10 - compatible : Must be "ti,twl4030";
11 For Integrated power-management/audio CODEC device used in OMAP3
12 based boards
13 - compatible : Must be "ti,twl6030";
14 For Integrated power-management used in OMAP4 based boards
15 - interrupts : This i2c device has an IRQ line connected to the main SoC
16 - interrupt-controller : Since the twl support several interrupts internally,
17 it is considered as an interrupt controller cascaded to the SoC one.
18 - #interrupt-cells = <1>;
21 - Child nodes contain in the twl. The twl family is made of several variants
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/freebsd/share/man/man4/
H A Dfdt_pinctrl.434 Pin multiplexing is a technology used to re-purpose a single
37 different SoC internal devices.
38 For example, based on the actual device design, a single SoC chip
41 Function selection is performed by the pinmux controller, a SoC
48 based systems, the pinmux controller is represented by a node in
52 Properties of such nodes are hardware-specific and handled
56 .Bd -literal
58 compatible = "vndr,soc1715-pinctrl";
76 Each configuration is described by setting the pinctrl-N
81 pinctrl-0 is a default configuration that is applied in the
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