Single\-lane (full) in projects: linux - OpenGrok search results

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Searched +full:single +full:- +full:lane (Results 1 – 25 of 37) sorted by relevance

/illumos-gate/usr/src/man/man9e/
H A D	mac.9e	33 framework provides a means for implementing high-performance networking 75 .Ss High-Level Design 76 At a high-level, a device driver is chiefly concerned with three general 78 .Bl -enum -offset indent 94 Configuration of a device, such as whether auto-negotiation should be 138 structure and the corresponding NULL-terminated 204 .Bd -literal -offset indent 303 .Bl -bullet -offset indent -compact 346 In addition to the per-packet flow described below, there are certain 353 During a single interrupt or poll request, a device driver should process [all …]
/illumos-gate/usr/src/uts/common/fs/zfs/
H A D	zio_inject.c	133 if (zb->zb_objset == DMU_META_OBJSET && in zio_match_handler() 134 record->zi_objset == DMU_META_OBJSET && in zio_match_handler() 135 record->zi_object == DMU_META_DNODE_OBJECT) { in zio_match_handler() 136 if (record->zi_type == DMU_OT_NONE \|\| in zio_match_handler() 137 type == record->zi_type) in zio_match_handler() 138 return (freq_triggered(record->zi_freq)); in zio_match_handler() 146 if (zb->zb_objset == record->zi_objset && in zio_match_handler() 147 zb->zb_object == record->zi_object && in zio_match_handler() 148 zb->zb_level == record->zi_level && in zio_match_handler() 149 zb->zb_blkid >= record->zi_start && in zio_match_handler() [all …]
/illumos-gate/usr/src/man/man9/
H A D	iport.9	53 A lane is connected to a device, for example a disk driver. 56 When a phy connects to a device with a single lane, this is often 66 Each bit in the mask corresponds to a specific lane. 68 and may enumerate a different device for each lane of the phy. 73 Another example to consider is when each lane of a phy is directly 74 connected to a single disk through a passive backplane. 75 In this case, each lane may represent its own iport, since the 145 .Bl -enum 147 Full-set 149 Per-address [all …]
/illumos-gate/usr/src/uts/sun4v/sys/
H A D	vsw_ldc.h	`32 * can support communications to a single network device). The 39 * currently most devices only have a single channel. The current 42 * The ldc is a bi-directional channel, which is divided up into 45 * Depending on the type of device each lane may have seperate 49 * rings are associated with the appropriate lane. I.e. rings 52 * are associated with the inbound lane. 58 * +----->port_t----->port_t----->port_t-----> 60 * +--->ldc_t 62 * +--->lane_t (inbound) 64 * \| +--->dring [all …]`
/illumos-gate/usr/src/uts/common/sys/
H A D	mac_ether.h	42 * Ethernet-specific media types for use with MAC_PROP_MEDIA and 51 * 100BASE-X is a catchall term defined in 802.3. In 802.3 section 52 * 24.1.1 100BASE-X is used to cover the more specific 100BASE-TX and 53 * 100BASE-FX realized in copper and fiber. The PCS is shared between 59 * Note, previously there was never a 100BASE-TX value so some drivers 60 * would have returned this for 100BASE-TX. 64 * 1000BASE-X is a fiber catch all. This is for compatibility with the 65 * traditional ETHER_STAT_XCVR_INUSE 1000BASE-X value. More specific 89 * 2.5 GbE, 5.0 GbE, single lane. 98 * 10 GbE, all lane configurations. [all …]
/illumos-gate/usr/src/man/man7/
H A D	ieee802.3.7	`47 .Sy show-linkprop 51 .Sy set-linkprop 55 .Sy show-ether 61 Note that some statistics are available in both 32- and 64-bit counters, 63 32-bit, but with 68 is the 64-bit version of the 75 .Bl -tag -width tx_late_collisions 77 Advertises 10 Mbps half-duplex support. 79 Advertises 10 Mbps full-duplex support. 81 Advertises 100 Mbps half-duplex support. [all …]`
/illumos-gate/usr/src/uts/common/io/qede/579xx/drivers/ecore/
H A D	ecore_phy.c	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 53 struct ecore_ptt p_ptt, u32 port, u32 lane, in ecore_phy_read() argument 56 return ecore_mcp_phy_read(p_hwfn->p_dev, cmd, in ecore_phy_read() 57 addr \| (lane << 16) \| (1<<29) \| (port << 30), buf, 8); in ecore_phy_read() 62 u32 lane, u32 addr, u32 data_lo, in ecore_phy_write() argument 70 return ecore_mcp_phy_write(p_hwfn->p_dev, cmd, in ecore_phy_write() 71 addr \| (lane << 16) \| (1<<29) \| (port << 30), in ecore_phy_write() 89 rc = ecore_phy_write(p_hwfn, p_ptt, port, 0 / lane */, addr, data_lo, in ecore_phy_core_write() [all …]
/illumos-gate/usr/src/uts/common/io/mac/
H A D	mac_stat.c	133 * Definitions for per software lane tx statistics 147 * Definitions for per software lane rx statistics 162 * Definitions for per hardware lane rx statistics 220 * Definitions for per hardware lane tx statistics 301 mac_impl_t mip = ksp->ks_private; in i_mac_driver_stat_update() 302 kstat_named_t knp = ksp->ks_data; in i_mac_driver_stat_update() 311 for (i = 0; i < mip->mi_kstat_count; i++, msi_index++) { in i_mac_driver_stat_update() 320 msi = mip->mi_type->mt_stats; in i_mac_driver_stat_update() 326 knp->value.ui64 = val; in i_mac_driver_stat_update() 329 knp->value.ui32 = (uint32_t)val; in i_mac_driver_stat_update() [all …]
/illumos-gate/usr/src/lib/libdladm/common/
H A D	libdlstat.c	78 for (ksp = kcp->kc_chain; ksp != NULL; ksp = ksp->ks_next) { in dladm_kstat_lookup() 79 if ((module == NULL \|\| strcmp(ksp->ks_module, module) == 0) && in dladm_kstat_lookup() 80 (instance == -1 \|\| ksp->ks_instance == instance) && in dladm_kstat_lookup() 81 (name == NULL \|\| strcmp(ksp->ks_name, name) == 0) && in dladm_kstat_lookup() 82 (class == NULL \|\| strcmp(ksp->ks_class, class) == 0)) in dladm_kstat_lookup() 99 if (kstat_read(kcp, ksp, NULL) == -1) in dladm_get_stats() 102 stats->snaptime = gethrtime(); in dladm_get_stats() 105 &stats->ipackets) < 0) { in dladm_get_stats() 107 &stats->ipackets) < 0) in dladm_get_stats() 112 &stats->opackets) < 0) { in dladm_get_stats() [all …]
/illumos-gate/usr/src/uts/common/io/hxge/
H A D	hxge_peu_hw.h	230 * Master Data Parity Error - set if all the following conditions 234 * Fast Back-to-Back Capable (N/A in PCIE) 236 * Capabilities List - presence of extended capability item. 239 * Fast Back-to-Back Enable (N/A in PCIE) 244 * The device can issue Memory Write-and-Invalidate commands (N/A 346 * Multi-Function Device: dbi writeable 374 * Description: PIO BAR0 - For Hydra PIO space PIO BAR1 & PIO BAR0 432 * Description: MSIX BAR0 - For MSI-X Tables and PBA MSIX BAR1 & MSIX 489 * Description: Virtualization BAR0 - Previously for Hydra 566 * Subsystem ID as assigned by PCI-SIG : dbi writeable [all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/common/
H A D	bnxe_clc.c	55 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) 83 #define OFFSETOF(_s, _m) ((u32) ((u8 )(&((_s ) 0)->_m) - \ 148 #define CHIP_REV_SIM(_p) (((0xF - (CHIP_REV(_p) >> CHIP_REV_SHIFT)) \ 329 (_phy)->def_md_devad, \ 335 (_phy)->def_md_devad, \ 365 * elink_check_lfa - This function checks if link reinitialization is required, 378 struct elink_dev cb = params->cb; in elink_check_lfa() 381 REG_RD(cb, params->lfa_base + in elink_check_lfa() 384 / NOTE: must be first condition checked - in elink_check_lfa() 389 REG_WR(cb, params->lfa_base + in elink_check_lfa() [all …]
/illumos-gate/usr/src/data/hwdata/
H A D	pci.ids	`5 # Date: 2025-06-09 03:15:02 8 # the PCI ID Project at https://pci-ids.ucw.cz/. 14 # (version 2 or higher) or the 3-clause BSD License. 25 # device device_name <-- single tab 26 # subvendor subdevice subsystem_name <-- two tabs 30 # This is a relabelled RTL-8139 31 8139 AT-2500TX V3 Ethernet 41 7a09 PCI-to-PCI Bridge 51 7a19 PCI-to-PCI Bridge 57 7a29 PCI-to-PCI Bridge [all …]`
/illumos-gate/usr/src/uts/sun4v/io/n2piupc/
H A D	n2piupc_tables.h	54 * without representation in a select register can specify their (non-existant) 70 * is always an entry with a bitmask of LSB-aligned bits of that counter's 75 * (small) events array with at least CLEAR_PIC and a single event, so that 133 #define FULL64BIT -1ULL /* Can use this for fld_mask. / 148 / N2PIU-specific definitions. / 162 #define NO_REGISTER (off_t)-1ULL 165 Default event values used in n2piu_event_t structures for non-programmable 332 * raw data is impractical except to make a non-zero test. Fake that this 333 * register has multiple modes, so that each lane can be shown separately. 361 * For non-programmable registers, include an n2piu_event_t which has two [all …]
/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/
H A D	reg_addr_k2.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_e5.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_bb.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 85 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 86 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 87 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 88 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 90 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 92 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 100 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_ah_compile15.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 85 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 87 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 96 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 98 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 144 …_SYS_ERR (0x1<<30) // Fatal or Non-Fatal Error Message s… 148 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)… 149 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)… [all …]
/illumos-gate/usr/src/cmd/zinject/
H A D	zinject.c	31 * from a user-visible object type and name to an internal representation. 37 * Errors can be injected into a particular vdev using the '-d' option. This 40 * that can be controlled through the '-e' option. The default is ENXIO. For 45 * For label faults, the -L option must be specified. This allows faults 51 * zinject -d device [-e errno] [-L <uber \| nvlist \| pad1 \| pad2>] pool 94 * These types should be self-explanatory. This tuple is then passed to the 97 * is used when translating existing faults into a human-readable string. 103 * zinject <-a \| -u pool> 104 * zinject -c <id\|all> 105 * zinject [-q] <-t type> [-f freq] [-u] [-a] [-m] [-e errno] [-l level] [all …]
/illumos-gate/usr/src/contrib/zlib/
H A D	ChangeLog	5 - Cygwin does not have _wopen(), so do not create gzopen_w() there 6 - Permit a deflateParams() parameter change as soon as possible 7 - Limit hash table inserts after switch from stored deflate 8 - Fix bug when window full in deflate_stored() 9 - Fix CLEAR_HASH macro to be usable as a single statement 10 - Avoid a conversion error in gzseek when off_t type too small 11 - Have Makefile return non-zero error code on test failure 12 - Avoid some conversion warnings in gzread.c and gzwrite.c 13 - Update use of errno for newer Windows CE versions 14 - Small speedup to inflate [psumbera] [all …]
/illumos-gate/usr/src/cmd/pcieadm/
H A D	pcieadm_cfgspace.c	18 * space and many of the capabilities. There are multiple sub-commands that 19 * vector into the same logic (e.g. 'save-cfgspace' and 'show-cfgspace'). In 24 * human name. The short name is a dot-delineated name. When in parsable 25 * mode, the name will always refer to a single field. However, for 29 * in non-parsable mode, you'll get an indication of the capability and 43 * o Currently designated vendor-specific capabilities aren't included here (or 44 * any specific vendor-specific capabilities for that matter). If they are 46 * sub-capability as we did with HyperTransport. 114 * Enough space for up to an 8-bit fields worth of values 178 VERIFY3P(walkp->pcw_filt, !=, NULL); in pcieadm_strfilt_pop() [all …]
/illumos-gate/usr/src/uts/common/io/chxge/com/
H A D	vsc7326_reg.h	23 * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved. 31 * Straight off the data sheet, VMDS-10038 Rev 2.0 and 32 * PD0011-01-14-Meigs-II 2002-12-12 92 * fn = FIFO number, 0-9 107 * bn = bucket number 0-10 (yes, 11 buckets) 137 #define REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 / 156 tri-speed are only defined with the version that needs a port number. 163 /* 10GbE specific, and different from tri-speed / 170 #define REG_MAX_RXHIGH CRA(0x1,0xa,0x0a) / XGMII lane 0-3 debug / 171 #define REG_MAX_RXLOW CRA(0x1,0xa,0x0b) / XGMII lane 4-7 debug */ [all …]
H A D	vsc7321_reg.h	23 * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved. 31 * Straight off the data sheet, VMDS-10038 Rev 2.0 and 32 * PD0011-01-14-Meigs-II 2002-12-12 88 * fn = FIFO number, 0-9 101 * bn = bucket number 0-10 (yes, 11 buckets) 131 #define REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 / 148 tri-speed are only defined with the version that needs a port number. 155 /* 10GbE specific, and different from tri-speed / 162 #define REG_MAX_RXHIGH CRA(0x1,0xa,0x0a) / XGMII lane 0-3 debug / 163 #define REG_MAX_RXLOW CRA(0x1,0xa,0x0b) / XGMII lane 4-7 debug */ [all …]
/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/mcp/
H A D	mcp_public.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 79 #define ETH_SPEED_SMARTLINQ 0x8 /* deprecated - use link_modes field instead / 93 #define ETH_LOOPBACK_MAC (4) / MAC Loopback - not supported / 101 #define EEE_CFG_EEE_ENABLED (1<<0) / EEE is enabled (configuration). Refer to eee_status->active f… 129 u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter/ 137 u64 r1522; / 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged frame counter / 162 u64 t64; / 0x40 (Offset 0xa8 ) TX 64-byte frame counter / 204 / HSI - Cannot add more stats to this struct. If needed, then need to open new struct */ [all …]
/illumos-gate/usr/src/uts/common/io/xge/hal/include/
H A D	xgehal-stats.h	21 * Copyright (c) 2002-2006 Neterion, Inc. 27 #include "xge-os-pal.h" 28 #include "xge-debug.h" 29 #include "xgehal-types.h" 30 #include "xgehal-config.h" 35 * struct xge_hal_stats_hw_info_t - Xframe hardware statistics. 40 * be derived by calcualating (tmac_ttl_octets - tmac_ttl_less_fb_octets) / 8 64 * @tmac_nucst_frms: Count of transmitted frames containing a non-unicast 99 * frames received with frame-too-long, FCS, or length errors. 102 * frames. Does not include frames received with frame-too-long, FCS, or length [all …]