1*14b24e2bSVaishali Kulkarni /* 2*14b24e2bSVaishali Kulkarni * CDDL HEADER START 3*14b24e2bSVaishali Kulkarni * 4*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the 5*14b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1, (the "License"). 6*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License. 7*14b24e2bSVaishali Kulkarni * 8*14b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*14b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0. 10*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions 11*14b24e2bSVaishali Kulkarni * and limitations under the License. 12*14b24e2bSVaishali Kulkarni * 13*14b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each 14*14b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*14b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the 16*14b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying 17*14b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner] 18*14b24e2bSVaishali Kulkarni * 19*14b24e2bSVaishali Kulkarni * CDDL HEADER END 20*14b24e2bSVaishali Kulkarni */ 21*14b24e2bSVaishali Kulkarni 22*14b24e2bSVaishali Kulkarni /* 23*14b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc. 24*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development 25*14b24e2bSVaishali Kulkarni * and Distribution License, v.1, (the "License"). 26*14b24e2bSVaishali Kulkarni 27*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License. 28*14b24e2bSVaishali Kulkarni 29*14b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available 30*14b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0 31*14b24e2bSVaishali Kulkarni 32*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and 33*14b24e2bSVaishali Kulkarni * limitations under the License. 34*14b24e2bSVaishali Kulkarni */ 35*14b24e2bSVaishali Kulkarni 36*14b24e2bSVaishali Kulkarni /**************************************************************************** 37*14b24e2bSVaishali Kulkarni * 38*14b24e2bSVaishali Kulkarni * Name: mcp_public.h 39*14b24e2bSVaishali Kulkarni * 40*14b24e2bSVaishali Kulkarni * Description: MCP public data 41*14b24e2bSVaishali Kulkarni * 42*14b24e2bSVaishali Kulkarni * Created: 13/01/2013 yanivr 43*14b24e2bSVaishali Kulkarni * 44*14b24e2bSVaishali Kulkarni ****************************************************************************/ 45*14b24e2bSVaishali Kulkarni 46*14b24e2bSVaishali Kulkarni #ifndef MCP_PUBLIC_H 47*14b24e2bSVaishali Kulkarni #define MCP_PUBLIC_H 48*14b24e2bSVaishali Kulkarni 49*14b24e2bSVaishali Kulkarni #define VF_MAX_STATIC 192 /* In case of AH */ 50*14b24e2bSVaishali Kulkarni 51*14b24e2bSVaishali Kulkarni #define MCP_GLOB_PATH_MAX 2 52*14b24e2bSVaishali Kulkarni #define MCP_PORT_MAX 2 /* Global */ 53*14b24e2bSVaishali Kulkarni #define MCP_GLOB_PORT_MAX 4 /* Global */ 54*14b24e2bSVaishali Kulkarni #define MCP_GLOB_FUNC_MAX 16 /* Global */ 55*14b24e2bSVaishali Kulkarni 56*14b24e2bSVaishali Kulkarni typedef u32 offsize_t; /* In DWORDS !!! */ 57*14b24e2bSVaishali Kulkarni /* Offset from the beginning of the MCP scratchpad */ 58*14b24e2bSVaishali Kulkarni #define OFFSIZE_OFFSET_SHIFT 0 59*14b24e2bSVaishali Kulkarni #define OFFSIZE_OFFSET_MASK 0x0000ffff 60*14b24e2bSVaishali Kulkarni /* Size of specific element (not the whole array if any) */ 61*14b24e2bSVaishali Kulkarni #define OFFSIZE_SIZE_SHIFT 16 62*14b24e2bSVaishali Kulkarni #define OFFSIZE_SIZE_MASK 0xffff0000 63*14b24e2bSVaishali Kulkarni 64*14b24e2bSVaishali Kulkarni /* SECTION_OFFSET is calculating the offset in bytes out of offsize */ 65*14b24e2bSVaishali Kulkarni #define SECTION_OFFSET(_offsize) ((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_SHIFT) << 2)) 66*14b24e2bSVaishali Kulkarni 67*14b24e2bSVaishali Kulkarni /* SECTION_SIZE is calculating the size in bytes out of offsize */ 68*14b24e2bSVaishali Kulkarni #define SECTION_SIZE(_offsize) (((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_SHIFT) << 2) 69*14b24e2bSVaishali Kulkarni 70*14b24e2bSVaishali Kulkarni /* SECTION_ADDR returns the GRC addr of a section, given offsize and index within section */ 71*14b24e2bSVaishali Kulkarni #define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + SECTION_OFFSET(_offsize) + (SECTION_SIZE(_offsize) * idx)) 72*14b24e2bSVaishali Kulkarni 73*14b24e2bSVaishali Kulkarni /* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address. Use offsetof, since the OFFSETUP collide with the firmware definition */ 74*14b24e2bSVaishali Kulkarni #define SECTION_OFFSIZE_ADDR(_pub_base, _section) (_pub_base + offsetof(struct mcp_public_data, sections[_section])) 75*14b24e2bSVaishali Kulkarni /* PHY configuration */ 76*14b24e2bSVaishali Kulkarni struct eth_phy_cfg { 77*14b24e2bSVaishali Kulkarni u32 speed; /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */ 78*14b24e2bSVaishali Kulkarni #define ETH_SPEED_AUTONEG 0 79*14b24e2bSVaishali Kulkarni #define ETH_SPEED_SMARTLINQ 0x8 /* deprecated - use link_modes field instead */ 80*14b24e2bSVaishali Kulkarni 81*14b24e2bSVaishali Kulkarni u32 pause; /* bitmask */ 82*14b24e2bSVaishali Kulkarni #define ETH_PAUSE_NONE 0x0 83*14b24e2bSVaishali Kulkarni #define ETH_PAUSE_AUTONEG 0x1 84*14b24e2bSVaishali Kulkarni #define ETH_PAUSE_RX 0x2 85*14b24e2bSVaishali Kulkarni #define ETH_PAUSE_TX 0x4 86*14b24e2bSVaishali Kulkarni 87*14b24e2bSVaishali Kulkarni u32 adv_speed; /* Default should be the speed_cap_mask */ 88*14b24e2bSVaishali Kulkarni u32 loopback_mode; 89*14b24e2bSVaishali Kulkarni #define ETH_LOOPBACK_NONE (0) 90*14b24e2bSVaishali Kulkarni #define ETH_LOOPBACK_INT_PHY (1) /* Serdes loopback. In AH, it refers to Near End */ 91*14b24e2bSVaishali Kulkarni #define ETH_LOOPBACK_EXT_PHY (2) /* External PHY Loopback */ 92*14b24e2bSVaishali Kulkarni #define ETH_LOOPBACK_EXT (3) /* External Loopback (Require loopback plug) */ 93*14b24e2bSVaishali Kulkarni #define ETH_LOOPBACK_MAC (4) /* MAC Loopback - not supported */ 94*14b24e2bSVaishali Kulkarni #define ETH_LOOPBACK_CNIG_AH_ONLY_0123 (5) /* Port to itself */ 95*14b24e2bSVaishali Kulkarni #define ETH_LOOPBACK_CNIG_AH_ONLY_2301 (6) /* Port to Port */ 96*14b24e2bSVaishali Kulkarni #define ETH_LOOPBACK_PCS_AH_ONLY (7) /* PCS loopback (TX to RX) */ 97*14b24e2bSVaishali Kulkarni #define ETH_LOOPBACK_REVERSE_MAC_AH_ONLY (8) /* Loop RX packet from PCS to TX */ 98*14b24e2bSVaishali Kulkarni #define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY (9) /* Remote Serdes Loopback (RX to TX) */ 99*14b24e2bSVaishali Kulkarni 100*14b24e2bSVaishali Kulkarni u32 eee_cfg; 101*14b24e2bSVaishali Kulkarni #define EEE_CFG_EEE_ENABLED (1<<0) /* EEE is enabled (configuration). Refer to eee_status->active for negotiated status */ 102*14b24e2bSVaishali Kulkarni #define EEE_CFG_TX_LPI (1<<1) 103*14b24e2bSVaishali Kulkarni #define EEE_CFG_ADV_SPEED_1G (1<<2) 104*14b24e2bSVaishali Kulkarni #define EEE_CFG_ADV_SPEED_10G (1<<3) 105*14b24e2bSVaishali Kulkarni #define EEE_TX_TIMER_USEC_MASK (0xfffffff0) 106*14b24e2bSVaishali Kulkarni #define EEE_TX_TIMER_USEC_SHIFT 4 107*14b24e2bSVaishali Kulkarni #define EEE_TX_TIMER_USEC_BALANCED_TIME (0xa00) 108*14b24e2bSVaishali Kulkarni #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME (0x100) 109*14b24e2bSVaishali Kulkarni #define EEE_TX_TIMER_USEC_LATENCY_TIME (0x6000) 110*14b24e2bSVaishali Kulkarni 111*14b24e2bSVaishali Kulkarni u32 link_modes; /* Additional link modes */ 112*14b24e2bSVaishali Kulkarni #define LINK_MODE_SMARTLINQ_ENABLE 0x1 /* XXX deprecated */ 113*14b24e2bSVaishali Kulkarni }; 114*14b24e2bSVaishali Kulkarni 115*14b24e2bSVaishali Kulkarni struct port_mf_cfg { 116*14b24e2bSVaishali Kulkarni 117*14b24e2bSVaishali Kulkarni u32 dynamic_cfg; /* device control channel */ 118*14b24e2bSVaishali Kulkarni #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff 119*14b24e2bSVaishali Kulkarni #define PORT_MF_CFG_OV_TAG_SHIFT 0 120*14b24e2bSVaishali Kulkarni #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK 121*14b24e2bSVaishali Kulkarni 122*14b24e2bSVaishali Kulkarni u32 reserved[1]; 123*14b24e2bSVaishali Kulkarni }; 124*14b24e2bSVaishali Kulkarni 125*14b24e2bSVaishali Kulkarni /* DO NOT add new fields in the middle 126*14b24e2bSVaishali Kulkarni * MUST be synced with struct pmm_stats_map 127*14b24e2bSVaishali Kulkarni */ 128*14b24e2bSVaishali Kulkarni struct eth_stats { 129*14b24e2bSVaishali Kulkarni u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/ 130*14b24e2bSVaishali Kulkarni u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/ 131*14b24e2bSVaishali Kulkarni u64 r255; /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter*/ 132*14b24e2bSVaishali Kulkarni u64 r511; /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter*/ 133*14b24e2bSVaishali Kulkarni u64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter*/ 134*14b24e2bSVaishali Kulkarni u64 r1518; /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */ 135*14b24e2bSVaishali Kulkarni union { 136*14b24e2bSVaishali Kulkarni struct { /* bb */ 137*14b24e2bSVaishali Kulkarni u64 r1522; /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged frame counter */ 138*14b24e2bSVaishali Kulkarni u64 r2047; /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/ 139*14b24e2bSVaishali Kulkarni u64 r4095; /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/ 140*14b24e2bSVaishali Kulkarni u64 r9216; /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/ 141*14b24e2bSVaishali Kulkarni u64 r16383; /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame counter */ 142*14b24e2bSVaishali Kulkarni 143*14b24e2bSVaishali Kulkarni } bb0; 144*14b24e2bSVaishali Kulkarni struct { /* ah */ 145*14b24e2bSVaishali Kulkarni u64 unused1; 146*14b24e2bSVaishali Kulkarni u64 r1519_to_max; /* 0x07 (Offset 0x38 ) RX 1519 to max byte frame counter*/ 147*14b24e2bSVaishali Kulkarni u64 unused2; 148*14b24e2bSVaishali Kulkarni u64 unused3; 149*14b24e2bSVaishali Kulkarni u64 unused4; 150*14b24e2bSVaishali Kulkarni } ah0; 151*14b24e2bSVaishali Kulkarni } u0; 152*14b24e2bSVaishali Kulkarni u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/ 153*14b24e2bSVaishali Kulkarni u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/ 154*14b24e2bSVaishali Kulkarni u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/ 155*14b24e2bSVaishali Kulkarni u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter*/ 156*14b24e2bSVaishali Kulkarni u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter*/ 157*14b24e2bSVaishali Kulkarni u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */ 158*14b24e2bSVaishali Kulkarni u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter*/ 159*14b24e2bSVaishali Kulkarni u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */ 160*14b24e2bSVaishali Kulkarni u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */ 161*14b24e2bSVaishali Kulkarni u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */ 162*14b24e2bSVaishali Kulkarni u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */ 163*14b24e2bSVaishali Kulkarni u64 t127; /* 0x41 (Offset 0xb0 ) TX 65 to 127 byte frame counter */ 164*14b24e2bSVaishali Kulkarni u64 t255; /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter*/ 165*14b24e2bSVaishali Kulkarni u64 t511; /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter*/ 166*14b24e2bSVaishali Kulkarni u64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter*/ 167*14b24e2bSVaishali Kulkarni u64 t1518; /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */ 168*14b24e2bSVaishali Kulkarni union { 169*14b24e2bSVaishali Kulkarni struct { /* bb */ 170*14b24e2bSVaishali Kulkarni u64 t2047; /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */ 171*14b24e2bSVaishali Kulkarni u64 t4095; /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */ 172*14b24e2bSVaishali Kulkarni u64 t9216; /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */ 173*14b24e2bSVaishali Kulkarni u64 t16383; /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame counter */ 174*14b24e2bSVaishali Kulkarni } bb1; 175*14b24e2bSVaishali Kulkarni struct { /* ah */ 176*14b24e2bSVaishali Kulkarni u64 t1519_to_max; /* 0x47 (Offset 0xd8 ) TX 1519 to max byte frame counter */ 177*14b24e2bSVaishali Kulkarni u64 unused6; 178*14b24e2bSVaishali Kulkarni u64 unused7; 179*14b24e2bSVaishali Kulkarni u64 unused8; 180*14b24e2bSVaishali Kulkarni } ah1; 181*14b24e2bSVaishali Kulkarni } u1; 182*14b24e2bSVaishali Kulkarni u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */ 183*14b24e2bSVaishali Kulkarni u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */ 184*14b24e2bSVaishali Kulkarni union { 185*14b24e2bSVaishali Kulkarni struct { /* bb */ 186*14b24e2bSVaishali Kulkarni u64 tlpiec; /* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */ 187*14b24e2bSVaishali Kulkarni u64 tncl; /* 0x6E (Offset 0x110) Transmit Total Collision Counter */ 188*14b24e2bSVaishali Kulkarni } bb2; 189*14b24e2bSVaishali Kulkarni struct { /* ah */ 190*14b24e2bSVaishali Kulkarni u64 unused9; 191*14b24e2bSVaishali Kulkarni u64 unused10; 192*14b24e2bSVaishali Kulkarni } ah2; 193*14b24e2bSVaishali Kulkarni } u2; 194*14b24e2bSVaishali Kulkarni u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */ 195*14b24e2bSVaishali Kulkarni u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */ 196*14b24e2bSVaishali Kulkarni u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */ 197*14b24e2bSVaishali Kulkarni u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */ 198*14b24e2bSVaishali Kulkarni u64 rxpok; /* 0x22 (Offset 0x138) RX good frame (good CRC, not oversized, no ERROR) */ 199*14b24e2bSVaishali Kulkarni u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */ 200*14b24e2bSVaishali Kulkarni u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */ 201*14b24e2bSVaishali Kulkarni u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */ 202*14b24e2bSVaishali Kulkarni u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */ 203*14b24e2bSVaishali Kulkarni u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */ 204*14b24e2bSVaishali Kulkarni /* HSI - Cannot add more stats to this struct. If needed, then need to open new struct */ 205*14b24e2bSVaishali Kulkarni }; 206*14b24e2bSVaishali Kulkarni 207*14b24e2bSVaishali Kulkarni struct brb_stats { 208*14b24e2bSVaishali Kulkarni u64 brb_truncate[8]; 209*14b24e2bSVaishali Kulkarni u64 brb_discard[8]; 210*14b24e2bSVaishali Kulkarni }; 211*14b24e2bSVaishali Kulkarni 212*14b24e2bSVaishali Kulkarni struct port_stats { 213*14b24e2bSVaishali Kulkarni struct brb_stats brb; 214*14b24e2bSVaishali Kulkarni struct eth_stats eth; 215*14b24e2bSVaishali Kulkarni }; 216*14b24e2bSVaishali Kulkarni 217*14b24e2bSVaishali Kulkarni /*-----+----------------------------------------------------------------------------- 218*14b24e2bSVaishali Kulkarni * Chip | Number and | Ports in| Ports in|2 PHY-s |# of ports|# of engines 219*14b24e2bSVaishali Kulkarni * | rate of physical | team #1 | team #2 |are used|per path | (paths) enabled 220*14b24e2bSVaishali Kulkarni * | ports | | | | | 221*14b24e2bSVaishali Kulkarni *======+==================+=========+=========+========+==========+================= 222*14b24e2bSVaishali Kulkarni * BB | 1x100G | This is special mode, where there are actually 2 HW func 223*14b24e2bSVaishali Kulkarni * BB | 2x10/20Gbps | 0,1 | NA | No | 1 | 1 224*14b24e2bSVaishali Kulkarni * BB | 2x40 Gbps | 0,1 | NA | Yes | 1 | 1 225*14b24e2bSVaishali Kulkarni * BB | 2x50Gbps | 0,1 | NA | No | 1 | 1 226*14b24e2bSVaishali Kulkarni * BB | 4x10Gbps | 0,2 | 1,3 | No | 1/2 | 1,2 (2 is optional) 227*14b24e2bSVaishali Kulkarni * BB | 4x10Gbps | 0,1 | 2,3 | No | 1/2 | 1,2 (2 is optional) 228*14b24e2bSVaishali Kulkarni * BB | 4x10Gbps | 0,3 | 1,2 | No | 1/2 | 1,2 (2 is optional) 229*14b24e2bSVaishali Kulkarni * BB | 4x10Gbps | 0,1,2,3 | NA | No | 1 | 1 230*14b24e2bSVaishali Kulkarni * AH | 2x10/20Gbps | 0,1 | NA | NA | 1 | NA 231*14b24e2bSVaishali Kulkarni * AH | 4x10Gbps | 0,1 | 2,3 | NA | 2 | NA 232*14b24e2bSVaishali Kulkarni * AH | 4x10Gbps | 0,2 | 1,3 | NA | 2 | NA 233*14b24e2bSVaishali Kulkarni * AH | 4x10Gbps | 0,3 | 1,2 | NA | 2 | NA 234*14b24e2bSVaishali Kulkarni * AH | 4x10Gbps | 0,1,2,3 | NA | NA | 1 | NA 235*14b24e2bSVaishali Kulkarni *======+==================+=========+=========+========+==========+=================== 236*14b24e2bSVaishali Kulkarni */ 237*14b24e2bSVaishali Kulkarni 238*14b24e2bSVaishali Kulkarni #define CMT_TEAM0 0 239*14b24e2bSVaishali Kulkarni #define CMT_TEAM1 1 240*14b24e2bSVaishali Kulkarni #define CMT_TEAM_MAX 2 241*14b24e2bSVaishali Kulkarni 242*14b24e2bSVaishali Kulkarni struct couple_mode_teaming { 243*14b24e2bSVaishali Kulkarni u8 port_cmt[MCP_GLOB_PORT_MAX]; 244*14b24e2bSVaishali Kulkarni #define PORT_CMT_IN_TEAM (1<<0) 245*14b24e2bSVaishali Kulkarni 246*14b24e2bSVaishali Kulkarni #define PORT_CMT_PORT_ROLE (1<<1) 247*14b24e2bSVaishali Kulkarni #define PORT_CMT_PORT_INACTIVE (0<<1) 248*14b24e2bSVaishali Kulkarni #define PORT_CMT_PORT_ACTIVE (1<<1) 249*14b24e2bSVaishali Kulkarni 250*14b24e2bSVaishali Kulkarni #define PORT_CMT_TEAM_MASK (1<<2) 251*14b24e2bSVaishali Kulkarni #define PORT_CMT_TEAM0 (0<<2) 252*14b24e2bSVaishali Kulkarni #define PORT_CMT_TEAM1 (1<<2) 253*14b24e2bSVaishali Kulkarni }; 254*14b24e2bSVaishali Kulkarni 255*14b24e2bSVaishali Kulkarni /************************************** 256*14b24e2bSVaishali Kulkarni * LLDP and DCBX HSI structures 257*14b24e2bSVaishali Kulkarni **************************************/ 258*14b24e2bSVaishali Kulkarni #define LLDP_CHASSIS_ID_STAT_LEN 4 259*14b24e2bSVaishali Kulkarni #define LLDP_PORT_ID_STAT_LEN 4 260*14b24e2bSVaishali Kulkarni #define DCBX_MAX_APP_PROTOCOL 32 261*14b24e2bSVaishali Kulkarni #define MAX_SYSTEM_LLDP_TLV_DATA 32 262*14b24e2bSVaishali Kulkarni 263*14b24e2bSVaishali Kulkarni typedef enum _lldp_agent_e { 264*14b24e2bSVaishali Kulkarni LLDP_NEAREST_BRIDGE = 0, 265*14b24e2bSVaishali Kulkarni LLDP_NEAREST_NON_TPMR_BRIDGE, 266*14b24e2bSVaishali Kulkarni LLDP_NEAREST_CUSTOMER_BRIDGE, 267*14b24e2bSVaishali Kulkarni LLDP_MAX_LLDP_AGENTS 268*14b24e2bSVaishali Kulkarni } lldp_agent_e; 269*14b24e2bSVaishali Kulkarni 270*14b24e2bSVaishali Kulkarni struct lldp_config_params_s { 271*14b24e2bSVaishali Kulkarni u32 config; 272*14b24e2bSVaishali Kulkarni #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff 273*14b24e2bSVaishali Kulkarni #define LLDP_CONFIG_TX_INTERVAL_SHIFT 0 274*14b24e2bSVaishali Kulkarni #define LLDP_CONFIG_HOLD_MASK 0x00000f00 275*14b24e2bSVaishali Kulkarni #define LLDP_CONFIG_HOLD_SHIFT 8 276*14b24e2bSVaishali Kulkarni #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000 277*14b24e2bSVaishali Kulkarni #define LLDP_CONFIG_MAX_CREDIT_SHIFT 12 278*14b24e2bSVaishali Kulkarni #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000 279*14b24e2bSVaishali Kulkarni #define LLDP_CONFIG_ENABLE_RX_SHIFT 30 280*14b24e2bSVaishali Kulkarni #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000 281*14b24e2bSVaishali Kulkarni #define LLDP_CONFIG_ENABLE_TX_SHIFT 31 282*14b24e2bSVaishali Kulkarni /* Holds local Chassis ID TLV header, subtype and 9B of payload. 283*14b24e2bSVaishali Kulkarni If firtst byte is 0, then we will use default chassis ID */ 284*14b24e2bSVaishali Kulkarni u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 285*14b24e2bSVaishali Kulkarni /* Holds local Port ID TLV header, subtype and 9B of payload. 286*14b24e2bSVaishali Kulkarni If firtst byte is 0, then we will use default port ID */ 287*14b24e2bSVaishali Kulkarni u32 local_port_id[LLDP_PORT_ID_STAT_LEN]; 288*14b24e2bSVaishali Kulkarni }; 289*14b24e2bSVaishali Kulkarni 290*14b24e2bSVaishali Kulkarni struct lldp_status_params_s { 291*14b24e2bSVaishali Kulkarni u32 prefix_seq_num; 292*14b24e2bSVaishali Kulkarni u32 status; /* TBD */ 293*14b24e2bSVaishali Kulkarni /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 294*14b24e2bSVaishali Kulkarni u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 295*14b24e2bSVaishali Kulkarni /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 296*14b24e2bSVaishali Kulkarni u32 peer_port_id[LLDP_PORT_ID_STAT_LEN]; 297*14b24e2bSVaishali Kulkarni u32 suffix_seq_num; 298*14b24e2bSVaishali Kulkarni }; 299*14b24e2bSVaishali Kulkarni 300*14b24e2bSVaishali Kulkarni struct dcbx_ets_feature { 301*14b24e2bSVaishali Kulkarni u32 flags; 302*14b24e2bSVaishali Kulkarni #define DCBX_ETS_ENABLED_MASK 0x00000001 303*14b24e2bSVaishali Kulkarni #define DCBX_ETS_ENABLED_SHIFT 0 304*14b24e2bSVaishali Kulkarni #define DCBX_ETS_WILLING_MASK 0x00000002 305*14b24e2bSVaishali Kulkarni #define DCBX_ETS_WILLING_SHIFT 1 306*14b24e2bSVaishali Kulkarni #define DCBX_ETS_ERROR_MASK 0x00000004 307*14b24e2bSVaishali Kulkarni #define DCBX_ETS_ERROR_SHIFT 2 308*14b24e2bSVaishali Kulkarni #define DCBX_ETS_CBS_MASK 0x00000008 309*14b24e2bSVaishali Kulkarni #define DCBX_ETS_CBS_SHIFT 3 310*14b24e2bSVaishali Kulkarni #define DCBX_ETS_MAX_TCS_MASK 0x000000f0 311*14b24e2bSVaishali Kulkarni #define DCBX_ETS_MAX_TCS_SHIFT 4 312*14b24e2bSVaishali Kulkarni #define DCBX_OOO_TC_MASK 0x00000f00 313*14b24e2bSVaishali Kulkarni #define DCBX_OOO_TC_SHIFT 8 314*14b24e2bSVaishali Kulkarni /* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */ 315*14b24e2bSVaishali Kulkarni u32 pri_tc_tbl[1]; 316*14b24e2bSVaishali Kulkarni /* Fixed TCP OOO TC usage is deprecated and used only for driver backward compatibility */ 317*14b24e2bSVaishali Kulkarni #define DCBX_TCP_OOO_TC (4) 318*14b24e2bSVaishali Kulkarni #define DCBX_TCP_OOO_K2_4PORT_TC (3) 319*14b24e2bSVaishali Kulkarni 320*14b24e2bSVaishali Kulkarni #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_TCP_OOO_TC + 1) 321*14b24e2bSVaishali Kulkarni #define DCBX_CEE_STRICT_PRIORITY 0xf 322*14b24e2bSVaishali Kulkarni /* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */ 323*14b24e2bSVaishali Kulkarni u32 tc_bw_tbl[2]; 324*14b24e2bSVaishali Kulkarni /* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */ 325*14b24e2bSVaishali Kulkarni u32 tc_tsa_tbl[2]; 326*14b24e2bSVaishali Kulkarni #define DCBX_ETS_TSA_STRICT 0 327*14b24e2bSVaishali Kulkarni #define DCBX_ETS_TSA_CBS 1 328*14b24e2bSVaishali Kulkarni #define DCBX_ETS_TSA_ETS 2 329*14b24e2bSVaishali Kulkarni }; 330*14b24e2bSVaishali Kulkarni 331*14b24e2bSVaishali Kulkarni struct dcbx_app_priority_entry { 332*14b24e2bSVaishali Kulkarni u32 entry; 333*14b24e2bSVaishali Kulkarni #define DCBX_APP_PRI_MAP_MASK 0x000000ff 334*14b24e2bSVaishali Kulkarni #define DCBX_APP_PRI_MAP_SHIFT 0 335*14b24e2bSVaishali Kulkarni #define DCBX_APP_PRI_0 0x01 336*14b24e2bSVaishali Kulkarni #define DCBX_APP_PRI_1 0x02 337*14b24e2bSVaishali Kulkarni #define DCBX_APP_PRI_2 0x04 338*14b24e2bSVaishali Kulkarni #define DCBX_APP_PRI_3 0x08 339*14b24e2bSVaishali Kulkarni #define DCBX_APP_PRI_4 0x10 340*14b24e2bSVaishali Kulkarni #define DCBX_APP_PRI_5 0x20 341*14b24e2bSVaishali Kulkarni #define DCBX_APP_PRI_6 0x40 342*14b24e2bSVaishali Kulkarni #define DCBX_APP_PRI_7 0x80 343*14b24e2bSVaishali Kulkarni #define DCBX_APP_SF_MASK 0x00000300 344*14b24e2bSVaishali Kulkarni #define DCBX_APP_SF_SHIFT 8 345*14b24e2bSVaishali Kulkarni #define DCBX_APP_SF_ETHTYPE 0 346*14b24e2bSVaishali Kulkarni #define DCBX_APP_SF_PORT 1 347*14b24e2bSVaishali Kulkarni #define DCBX_APP_SF_IEEE_MASK 0x0000f000 348*14b24e2bSVaishali Kulkarni #define DCBX_APP_SF_IEEE_SHIFT 12 349*14b24e2bSVaishali Kulkarni #define DCBX_APP_SF_IEEE_RESERVED 0 350*14b24e2bSVaishali Kulkarni #define DCBX_APP_SF_IEEE_ETHTYPE 1 351*14b24e2bSVaishali Kulkarni #define DCBX_APP_SF_IEEE_TCP_PORT 2 352*14b24e2bSVaishali Kulkarni #define DCBX_APP_SF_IEEE_UDP_PORT 3 353*14b24e2bSVaishali Kulkarni #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4 354*14b24e2bSVaishali Kulkarni 355*14b24e2bSVaishali Kulkarni #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000 356*14b24e2bSVaishali Kulkarni #define DCBX_APP_PROTOCOL_ID_SHIFT 16 357*14b24e2bSVaishali Kulkarni }; 358*14b24e2bSVaishali Kulkarni 359*14b24e2bSVaishali Kulkarni 360*14b24e2bSVaishali Kulkarni /* FW structure in BE */ 361*14b24e2bSVaishali Kulkarni struct dcbx_app_priority_feature { 362*14b24e2bSVaishali Kulkarni u32 flags; 363*14b24e2bSVaishali Kulkarni #define DCBX_APP_ENABLED_MASK 0x00000001 364*14b24e2bSVaishali Kulkarni #define DCBX_APP_ENABLED_SHIFT 0 365*14b24e2bSVaishali Kulkarni #define DCBX_APP_WILLING_MASK 0x00000002 366*14b24e2bSVaishali Kulkarni #define DCBX_APP_WILLING_SHIFT 1 367*14b24e2bSVaishali Kulkarni #define DCBX_APP_ERROR_MASK 0x00000004 368*14b24e2bSVaishali Kulkarni #define DCBX_APP_ERROR_SHIFT 2 369*14b24e2bSVaishali Kulkarni /* Not in use 370*14b24e2bSVaishali Kulkarni #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00 371*14b24e2bSVaishali Kulkarni #define DCBX_APP_DEFAULT_PRI_SHIFT 8 372*14b24e2bSVaishali Kulkarni */ 373*14b24e2bSVaishali Kulkarni #define DCBX_APP_MAX_TCS_MASK 0x0000f000 374*14b24e2bSVaishali Kulkarni #define DCBX_APP_MAX_TCS_SHIFT 12 375*14b24e2bSVaishali Kulkarni #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000 376*14b24e2bSVaishali Kulkarni #define DCBX_APP_NUM_ENTRIES_SHIFT 16 377*14b24e2bSVaishali Kulkarni struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 378*14b24e2bSVaishali Kulkarni }; 379*14b24e2bSVaishali Kulkarni 380*14b24e2bSVaishali Kulkarni /* FW structure in BE */ 381*14b24e2bSVaishali Kulkarni struct dcbx_features { 382*14b24e2bSVaishali Kulkarni /* PG feature */ 383*14b24e2bSVaishali Kulkarni struct dcbx_ets_feature ets; 384*14b24e2bSVaishali Kulkarni /* PFC feature */ 385*14b24e2bSVaishali Kulkarni u32 pfc; 386*14b24e2bSVaishali Kulkarni #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff 387*14b24e2bSVaishali Kulkarni #define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0 388*14b24e2bSVaishali Kulkarni #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01 389*14b24e2bSVaishali Kulkarni #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02 390*14b24e2bSVaishali Kulkarni #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04 391*14b24e2bSVaishali Kulkarni #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08 392*14b24e2bSVaishali Kulkarni #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10 393*14b24e2bSVaishali Kulkarni #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20 394*14b24e2bSVaishali Kulkarni #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40 395*14b24e2bSVaishali Kulkarni #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80 396*14b24e2bSVaishali Kulkarni 397*14b24e2bSVaishali Kulkarni #define DCBX_PFC_FLAGS_MASK 0x0000ff00 398*14b24e2bSVaishali Kulkarni #define DCBX_PFC_FLAGS_SHIFT 8 399*14b24e2bSVaishali Kulkarni #define DCBX_PFC_CAPS_MASK 0x00000f00 400*14b24e2bSVaishali Kulkarni #define DCBX_PFC_CAPS_SHIFT 8 401*14b24e2bSVaishali Kulkarni #define DCBX_PFC_MBC_MASK 0x00004000 402*14b24e2bSVaishali Kulkarni #define DCBX_PFC_MBC_SHIFT 14 403*14b24e2bSVaishali Kulkarni #define DCBX_PFC_WILLING_MASK 0x00008000 404*14b24e2bSVaishali Kulkarni #define DCBX_PFC_WILLING_SHIFT 15 405*14b24e2bSVaishali Kulkarni #define DCBX_PFC_ENABLED_MASK 0x00010000 406*14b24e2bSVaishali Kulkarni #define DCBX_PFC_ENABLED_SHIFT 16 407*14b24e2bSVaishali Kulkarni #define DCBX_PFC_ERROR_MASK 0x00020000 408*14b24e2bSVaishali Kulkarni #define DCBX_PFC_ERROR_SHIFT 17 409*14b24e2bSVaishali Kulkarni 410*14b24e2bSVaishali Kulkarni /* APP feature */ 411*14b24e2bSVaishali Kulkarni struct dcbx_app_priority_feature app; 412*14b24e2bSVaishali Kulkarni }; 413*14b24e2bSVaishali Kulkarni 414*14b24e2bSVaishali Kulkarni struct dcbx_local_params { 415*14b24e2bSVaishali Kulkarni u32 config; 416*14b24e2bSVaishali Kulkarni #define DCBX_CONFIG_VERSION_MASK 0x00000007 417*14b24e2bSVaishali Kulkarni #define DCBX_CONFIG_VERSION_SHIFT 0 418*14b24e2bSVaishali Kulkarni #define DCBX_CONFIG_VERSION_DISABLED 0 419*14b24e2bSVaishali Kulkarni #define DCBX_CONFIG_VERSION_IEEE 1 420*14b24e2bSVaishali Kulkarni #define DCBX_CONFIG_VERSION_CEE 2 421*14b24e2bSVaishali Kulkarni #define DCBX_CONFIG_VERSION_STATIC 4 422*14b24e2bSVaishali Kulkarni 423*14b24e2bSVaishali Kulkarni u32 flags; 424*14b24e2bSVaishali Kulkarni struct dcbx_features features; 425*14b24e2bSVaishali Kulkarni }; 426*14b24e2bSVaishali Kulkarni 427*14b24e2bSVaishali Kulkarni struct dcbx_mib { 428*14b24e2bSVaishali Kulkarni u32 prefix_seq_num; 429*14b24e2bSVaishali Kulkarni u32 flags; 430*14b24e2bSVaishali Kulkarni /* 431*14b24e2bSVaishali Kulkarni #define DCBX_CONFIG_VERSION_MASK 0x00000007 432*14b24e2bSVaishali Kulkarni #define DCBX_CONFIG_VERSION_SHIFT 0 433*14b24e2bSVaishali Kulkarni #define DCBX_CONFIG_VERSION_DISABLED 0 434*14b24e2bSVaishali Kulkarni #define DCBX_CONFIG_VERSION_IEEE 1 435*14b24e2bSVaishali Kulkarni #define DCBX_CONFIG_VERSION_CEE 2 436*14b24e2bSVaishali Kulkarni #define DCBX_CONFIG_VERSION_STATIC 4 437*14b24e2bSVaishali Kulkarni */ 438*14b24e2bSVaishali Kulkarni struct dcbx_features features; 439*14b24e2bSVaishali Kulkarni u32 suffix_seq_num; 440*14b24e2bSVaishali Kulkarni }; 441*14b24e2bSVaishali Kulkarni 442*14b24e2bSVaishali Kulkarni struct lldp_system_tlvs_buffer_s { 443*14b24e2bSVaishali Kulkarni u16 valid; 444*14b24e2bSVaishali Kulkarni u16 length; 445*14b24e2bSVaishali Kulkarni u32 data[MAX_SYSTEM_LLDP_TLV_DATA]; 446*14b24e2bSVaishali Kulkarni }; 447*14b24e2bSVaishali Kulkarni 448*14b24e2bSVaishali Kulkarni struct dcb_dscp_map { 449*14b24e2bSVaishali Kulkarni u32 flags; 450*14b24e2bSVaishali Kulkarni #define DCB_DSCP_ENABLE_MASK 0x1 451*14b24e2bSVaishali Kulkarni #define DCB_DSCP_ENABLE_SHIFT 0 452*14b24e2bSVaishali Kulkarni #define DCB_DSCP_ENABLE 1 453*14b24e2bSVaishali Kulkarni u32 dscp_pri_map[8]; 454*14b24e2bSVaishali Kulkarni /* the map structure is the following: 455*14b24e2bSVaishali Kulkarni each u32 is split into 4 bits chunks, each chunk holds priority for respective dscp 456*14b24e2bSVaishali Kulkarni Lowest dscp is at lsb 457*14b24e2bSVaishali Kulkarni 31 28 24 20 16 12 8 4 0 458*14b24e2bSVaishali Kulkarni dscp_pri_map[0]: | dscp7 pri | dscp6 pri | dscp5 pri | dscp4 pri | dscp3 pri | dscp2 pri | dscp1 pri | dscp0 pri | 459*14b24e2bSVaishali Kulkarni dscp_pri_map[1]: | dscp15 pri| dscp14 pri| dscp13 pri| dscp12 pri| dscp11 pri| dscp10 pri| dscp9 pri | dscp8 pri | 460*14b24e2bSVaishali Kulkarni etc.*/ 461*14b24e2bSVaishali Kulkarni }; 462*14b24e2bSVaishali Kulkarni 463*14b24e2bSVaishali Kulkarni /**************************************/ 464*14b24e2bSVaishali Kulkarni /* */ 465*14b24e2bSVaishali Kulkarni /* P U B L I C G L O B A L */ 466*14b24e2bSVaishali Kulkarni /* */ 467*14b24e2bSVaishali Kulkarni /**************************************/ 468*14b24e2bSVaishali Kulkarni struct public_global { 469*14b24e2bSVaishali Kulkarni u32 max_path; /* 32bit is wasty, but this will be used often */ 470*14b24e2bSVaishali Kulkarni u32 max_ports; /* (Global) 32bit is wasty, but this will be used often */ 471*14b24e2bSVaishali Kulkarni #define MODE_1P 1 /* TBD - NEED TO THINK OF A BETTER NAME */ 472*14b24e2bSVaishali Kulkarni #define MODE_2P 2 473*14b24e2bSVaishali Kulkarni #define MODE_3P 3 474*14b24e2bSVaishali Kulkarni #define MODE_4P 4 475*14b24e2bSVaishali Kulkarni u32 debug_mb_offset; 476*14b24e2bSVaishali Kulkarni u32 phymod_dbg_mb_offset; 477*14b24e2bSVaishali Kulkarni struct couple_mode_teaming cmt; 478*14b24e2bSVaishali Kulkarni s32 internal_temperature; /* Temperature in Celcius (-255C / +255C), measured every second. */ 479*14b24e2bSVaishali Kulkarni u32 mfw_ver; 480*14b24e2bSVaishali Kulkarni u32 running_bundle_id; 481*14b24e2bSVaishali Kulkarni s32 external_temperature; 482*14b24e2bSVaishali Kulkarni u32 mdump_reason; 483*14b24e2bSVaishali Kulkarni #define MDUMP_REASON_INTERNAL_ERROR (1 << 0) 484*14b24e2bSVaishali Kulkarni #define MDUMP_REASON_EXTERNAL_TRIGGER (1 << 1) 485*14b24e2bSVaishali Kulkarni #define MDUMP_REASON_DUMP_AGED (1 << 2) 486*14b24e2bSVaishali Kulkarni u32 ext_phy_upgrade_fw; 487*14b24e2bSVaishali Kulkarni #define EXT_PHY_FW_UPGRADE_STATUS_MASK (0x0000ffff) 488*14b24e2bSVaishali Kulkarni #define EXT_PHY_FW_UPGRADE_STATUS_SHIFT (0) 489*14b24e2bSVaishali Kulkarni #define EXT_PHY_FW_UPGRADE_STATUS_IN_PROGRESS (1) 490*14b24e2bSVaishali Kulkarni #define EXT_PHY_FW_UPGRADE_STATUS_FAILED (2) 491*14b24e2bSVaishali Kulkarni #define EXT_PHY_FW_UPGRADE_STATUS_SUCCESS (3) 492*14b24e2bSVaishali Kulkarni #define EXT_PHY_FW_UPGRADE_TYPE_MASK (0xffff0000) 493*14b24e2bSVaishali Kulkarni #define EXT_PHY_FW_UPGRADE_TYPE_SHIFT (16) 494*14b24e2bSVaishali Kulkarni 495*14b24e2bSVaishali Kulkarni u8 runtime_port_swap_map[MODE_4P]; 496*14b24e2bSVaishali Kulkarni u32 data_ptr; 497*14b24e2bSVaishali Kulkarni u32 data_size; 498*14b24e2bSVaishali Kulkarni }; 499*14b24e2bSVaishali Kulkarni 500*14b24e2bSVaishali Kulkarni /**************************************/ 501*14b24e2bSVaishali Kulkarni /* */ 502*14b24e2bSVaishali Kulkarni /* P U B L I C P A T H */ 503*14b24e2bSVaishali Kulkarni /* */ 504*14b24e2bSVaishali Kulkarni /**************************************/ 505*14b24e2bSVaishali Kulkarni 506*14b24e2bSVaishali Kulkarni /**************************************************************************** 507*14b24e2bSVaishali Kulkarni * Shared Memory 2 Region * 508*14b24e2bSVaishali Kulkarni ****************************************************************************/ 509*14b24e2bSVaishali Kulkarni /* The fw_flr_ack is actually built in the following way: */ 510*14b24e2bSVaishali Kulkarni /* 8 bit: PF ack */ 511*14b24e2bSVaishali Kulkarni /* 128 bit: VF ack */ 512*14b24e2bSVaishali Kulkarni /* 8 bit: ios_dis_ack */ 513*14b24e2bSVaishali Kulkarni /* In order to maintain endianity in the mailbox hsi, we want to keep using */ 514*14b24e2bSVaishali Kulkarni /* u32. The fw must have the VF right after the PF since this is how it */ 515*14b24e2bSVaishali Kulkarni /* access arrays(it expects always the VF to reside after the PF, and that */ 516*14b24e2bSVaishali Kulkarni /* makes the calculation much easier for it. ) */ 517*14b24e2bSVaishali Kulkarni /* In order to answer both limitations, and keep the struct small, the code */ 518*14b24e2bSVaishali Kulkarni /* will abuse the structure defined here to achieve the actual partition */ 519*14b24e2bSVaishali Kulkarni /* above */ 520*14b24e2bSVaishali Kulkarni /****************************************************************************/ 521*14b24e2bSVaishali Kulkarni struct fw_flr_mb { 522*14b24e2bSVaishali Kulkarni u32 aggint; 523*14b24e2bSVaishali Kulkarni u32 opgen_addr; 524*14b24e2bSVaishali Kulkarni u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */ 525*14b24e2bSVaishali Kulkarni #define ACCUM_ACK_PF_BASE 0 526*14b24e2bSVaishali Kulkarni #define ACCUM_ACK_PF_SHIFT 0 527*14b24e2bSVaishali Kulkarni 528*14b24e2bSVaishali Kulkarni #define ACCUM_ACK_VF_BASE 8 529*14b24e2bSVaishali Kulkarni #define ACCUM_ACK_VF_SHIFT 3 530*14b24e2bSVaishali Kulkarni 531*14b24e2bSVaishali Kulkarni #define ACCUM_ACK_IOV_DIS_BASE 256 532*14b24e2bSVaishali Kulkarni #define ACCUM_ACK_IOV_DIS_SHIFT 8 533*14b24e2bSVaishali Kulkarni 534*14b24e2bSVaishali Kulkarni }; 535*14b24e2bSVaishali Kulkarni 536*14b24e2bSVaishali Kulkarni struct public_path { 537*14b24e2bSVaishali Kulkarni struct fw_flr_mb flr_mb; 538*14b24e2bSVaishali Kulkarni /* 539*14b24e2bSVaishali Kulkarni * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 540*14b24e2bSVaishali Kulkarni * which were disabled/flred 541*14b24e2bSVaishali Kulkarni */ 542*14b24e2bSVaishali Kulkarni u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; /* 0x003c */ 543*14b24e2bSVaishali Kulkarni 544*14b24e2bSVaishali Kulkarni u32 process_kill; /* Reset on mcp reset, and incremented for eveny process kill event. */ 545*14b24e2bSVaishali Kulkarni #define PROCESS_KILL_COUNTER_MASK 0x0000ffff 546*14b24e2bSVaishali Kulkarni #define PROCESS_KILL_COUNTER_SHIFT 0 547*14b24e2bSVaishali Kulkarni #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000 548*14b24e2bSVaishali Kulkarni #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16 549*14b24e2bSVaishali Kulkarni #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id*32 + aeu_bit) 550*14b24e2bSVaishali Kulkarni }; 551*14b24e2bSVaishali Kulkarni 552*14b24e2bSVaishali Kulkarni /**************************************/ 553*14b24e2bSVaishali Kulkarni /* */ 554*14b24e2bSVaishali Kulkarni /* P U B L I C P O R T */ 555*14b24e2bSVaishali Kulkarni /* */ 556*14b24e2bSVaishali Kulkarni /**************************************/ 557*14b24e2bSVaishali Kulkarni #define FC_NPIV_WWPN_SIZE 8 558*14b24e2bSVaishali Kulkarni #define FC_NPIV_WWNN_SIZE 8 559*14b24e2bSVaishali Kulkarni struct dci_npiv_settings { 560*14b24e2bSVaishali Kulkarni u8 npiv_wwpn[FC_NPIV_WWPN_SIZE]; 561*14b24e2bSVaishali Kulkarni u8 npiv_wwnn[FC_NPIV_WWNN_SIZE]; 562*14b24e2bSVaishali Kulkarni }; 563*14b24e2bSVaishali Kulkarni 564*14b24e2bSVaishali Kulkarni struct dci_fc_npiv_cfg { 565*14b24e2bSVaishali Kulkarni /* hdr used internally by the MFW */ 566*14b24e2bSVaishali Kulkarni u32 hdr; 567*14b24e2bSVaishali Kulkarni u32 num_of_npiv; 568*14b24e2bSVaishali Kulkarni }; 569*14b24e2bSVaishali Kulkarni 570*14b24e2bSVaishali Kulkarni #define MAX_NUMBER_NPIV 64 571*14b24e2bSVaishali Kulkarni struct dci_fc_npiv_tbl { 572*14b24e2bSVaishali Kulkarni struct dci_fc_npiv_cfg fc_npiv_cfg; 573*14b24e2bSVaishali Kulkarni struct dci_npiv_settings settings[MAX_NUMBER_NPIV]; 574*14b24e2bSVaishali Kulkarni }; 575*14b24e2bSVaishali Kulkarni 576*14b24e2bSVaishali Kulkarni /**************************************************************************** 577*14b24e2bSVaishali Kulkarni * Driver <-> FW Mailbox * 578*14b24e2bSVaishali Kulkarni ****************************************************************************/ 579*14b24e2bSVaishali Kulkarni 580*14b24e2bSVaishali Kulkarni struct public_port { 581*14b24e2bSVaishali Kulkarni u32 validity_map; /* 0x0 (4*2 = 0x8) */ 582*14b24e2bSVaishali Kulkarni 583*14b24e2bSVaishali Kulkarni /* validity bits */ 584*14b24e2bSVaishali Kulkarni #define MCP_VALIDITY_PCI_CFG 0x00100000 585*14b24e2bSVaishali Kulkarni #define MCP_VALIDITY_MB 0x00200000 586*14b24e2bSVaishali Kulkarni #define MCP_VALIDITY_DEV_INFO 0x00400000 587*14b24e2bSVaishali Kulkarni #define MCP_VALIDITY_RESERVED 0x00000007 588*14b24e2bSVaishali Kulkarni 589*14b24e2bSVaishali Kulkarni /* One licensing bit should be set */ 590*14b24e2bSVaishali Kulkarni #define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 /* yaniv - tbd ? license */ 591*14b24e2bSVaishali Kulkarni #define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 592*14b24e2bSVaishali Kulkarni #define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 593*14b24e2bSVaishali Kulkarni #define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 594*14b24e2bSVaishali Kulkarni 595*14b24e2bSVaishali Kulkarni /* Active MFW */ 596*14b24e2bSVaishali Kulkarni #define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 597*14b24e2bSVaishali Kulkarni #define MCP_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 598*14b24e2bSVaishali Kulkarni #define MCP_VALIDITY_ACTIVE_MFW_NCSI 0x00000040 599*14b24e2bSVaishali Kulkarni #define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 600*14b24e2bSVaishali Kulkarni 601*14b24e2bSVaishali Kulkarni u32 link_status; 602*14b24e2bSVaishali Kulkarni #define LINK_STATUS_LINK_UP 0x00000001 603*14b24e2bSVaishali Kulkarni #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e 604*14b24e2bSVaishali Kulkarni #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1<<1) 605*14b24e2bSVaishali Kulkarni #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2<<1) 606*14b24e2bSVaishali Kulkarni #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3<<1) 607*14b24e2bSVaishali Kulkarni #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4<<1) 608*14b24e2bSVaishali Kulkarni #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5<<1) 609*14b24e2bSVaishali Kulkarni #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6<<1) 610*14b24e2bSVaishali Kulkarni #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7<<1) 611*14b24e2bSVaishali Kulkarni #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8<<1) 612*14b24e2bSVaishali Kulkarni #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 613*14b24e2bSVaishali Kulkarni #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 614*14b24e2bSVaishali Kulkarni #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 615*14b24e2bSVaishali Kulkarni #define LINK_STATUS_PFC_ENABLED 0x00000100 616*14b24e2bSVaishali Kulkarni #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 617*14b24e2bSVaishali Kulkarni #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 618*14b24e2bSVaishali Kulkarni #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800 619*14b24e2bSVaishali Kulkarni #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000 620*14b24e2bSVaishali Kulkarni #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000 621*14b24e2bSVaishali Kulkarni #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000 622*14b24e2bSVaishali Kulkarni #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000 623*14b24e2bSVaishali Kulkarni #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000 624*14b24e2bSVaishali Kulkarni #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 625*14b24e2bSVaishali Kulkarni #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 626*14b24e2bSVaishali Kulkarni #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 627*14b24e2bSVaishali Kulkarni #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 628*14b24e2bSVaishali Kulkarni #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 629*14b24e2bSVaishali Kulkarni #define LINK_STATUS_SFP_TX_FAULT 0x00100000 630*14b24e2bSVaishali Kulkarni #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000 631*14b24e2bSVaishali Kulkarni #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000 632*14b24e2bSVaishali Kulkarni #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000 633*14b24e2bSVaishali Kulkarni #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000 634*14b24e2bSVaishali Kulkarni #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000 635*14b24e2bSVaishali Kulkarni #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000 636*14b24e2bSVaishali Kulkarni #define LINK_STATUS_FEC_MODE_MASK 0x38000000 637*14b24e2bSVaishali Kulkarni #define LINK_STATUS_FEC_MODE_NONE (0<<27) 638*14b24e2bSVaishali Kulkarni #define LINK_STATUS_FEC_MODE_FIRECODE_CL74 (1<<27) 639*14b24e2bSVaishali Kulkarni #define LINK_STATUS_FEC_MODE_RS_CL91 (2<<27) 640*14b24e2bSVaishali Kulkarni #define LINK_STATUS_EXT_PHY_LINK_UP 0x40000000 641*14b24e2bSVaishali Kulkarni 642*14b24e2bSVaishali Kulkarni u32 link_status1; 643*14b24e2bSVaishali Kulkarni u32 ext_phy_fw_version; 644*14b24e2bSVaishali Kulkarni u32 drv_phy_cfg_addr; /* Points to struct eth_phy_cfg (For READ-ONLY) */ 645*14b24e2bSVaishali Kulkarni 646*14b24e2bSVaishali Kulkarni u32 port_stx; 647*14b24e2bSVaishali Kulkarni 648*14b24e2bSVaishali Kulkarni u32 stat_nig_timer; 649*14b24e2bSVaishali Kulkarni 650*14b24e2bSVaishali Kulkarni struct port_mf_cfg port_mf_config; 651*14b24e2bSVaishali Kulkarni struct port_stats stats; 652*14b24e2bSVaishali Kulkarni 653*14b24e2bSVaishali Kulkarni u32 media_type; 654*14b24e2bSVaishali Kulkarni #define MEDIA_UNSPECIFIED 0x0 655*14b24e2bSVaishali Kulkarni #define MEDIA_SFPP_10G_FIBER 0x1 /* Use MEDIA_MODULE_FIBER instead */ 656*14b24e2bSVaishali Kulkarni #define MEDIA_XFP_FIBER 0x2 /* Use MEDIA_MODULE_FIBER instead */ 657*14b24e2bSVaishali Kulkarni #define MEDIA_DA_TWINAX 0x3 658*14b24e2bSVaishali Kulkarni #define MEDIA_BASE_T 0x4 659*14b24e2bSVaishali Kulkarni #define MEDIA_SFP_1G_FIBER 0x5 /* Use MEDIA_MODULE_FIBER instead */ 660*14b24e2bSVaishali Kulkarni #define MEDIA_MODULE_FIBER 0x6 661*14b24e2bSVaishali Kulkarni #define MEDIA_KR 0xf0 662*14b24e2bSVaishali Kulkarni #define MEDIA_NOT_PRESENT 0xff 663*14b24e2bSVaishali Kulkarni 664*14b24e2bSVaishali Kulkarni u32 lfa_status; 665*14b24e2bSVaishali Kulkarni #define LFA_LINK_FLAP_REASON_OFFSET 0 666*14b24e2bSVaishali Kulkarni #define LFA_LINK_FLAP_REASON_MASK 0x000000ff 667*14b24e2bSVaishali Kulkarni #define LFA_NO_REASON (0<<0) 668*14b24e2bSVaishali Kulkarni #define LFA_LINK_DOWN (1<<0) 669*14b24e2bSVaishali Kulkarni #define LFA_FORCE_INIT (1<<1) 670*14b24e2bSVaishali Kulkarni #define LFA_LOOPBACK_MISMATCH (1<<2) 671*14b24e2bSVaishali Kulkarni #define LFA_SPEED_MISMATCH (1<<3) 672*14b24e2bSVaishali Kulkarni #define LFA_FLOW_CTRL_MISMATCH (1<<4) 673*14b24e2bSVaishali Kulkarni #define LFA_ADV_SPEED_MISMATCH (1<<5) 674*14b24e2bSVaishali Kulkarni #define LFA_EEE_MISMATCH (1<<6) 675*14b24e2bSVaishali Kulkarni #define LFA_LINK_MODES_MISMATCH (1<<7) 676*14b24e2bSVaishali Kulkarni #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 677*14b24e2bSVaishali Kulkarni #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 678*14b24e2bSVaishali Kulkarni #define LINK_FLAP_COUNT_OFFSET 16 679*14b24e2bSVaishali Kulkarni #define LINK_FLAP_COUNT_MASK 0x00ff0000 680*14b24e2bSVaishali Kulkarni 681*14b24e2bSVaishali Kulkarni u32 link_change_count; 682*14b24e2bSVaishali Kulkarni 683*14b24e2bSVaishali Kulkarni /* LLDP params */ 684*14b24e2bSVaishali Kulkarni struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS]; // offset: 536 bytes? 685*14b24e2bSVaishali Kulkarni struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS]; 686*14b24e2bSVaishali Kulkarni struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf; 687*14b24e2bSVaishali Kulkarni 688*14b24e2bSVaishali Kulkarni /* DCBX related MIB */ 689*14b24e2bSVaishali Kulkarni struct dcbx_local_params local_admin_dcbx_mib; 690*14b24e2bSVaishali Kulkarni struct dcbx_mib remote_dcbx_mib; 691*14b24e2bSVaishali Kulkarni struct dcbx_mib operational_dcbx_mib; 692*14b24e2bSVaishali Kulkarni 693*14b24e2bSVaishali Kulkarni /* FC_NPIV table offset & size in NVRAM value of 0 means not present */ 694*14b24e2bSVaishali Kulkarni u32 fc_npiv_nvram_tbl_addr; 695*14b24e2bSVaishali Kulkarni #define NPIV_TBL_INVALID_ADDR 0xFFFFFFFF 696*14b24e2bSVaishali Kulkarni 697*14b24e2bSVaishali Kulkarni u32 fc_npiv_nvram_tbl_size; 698*14b24e2bSVaishali Kulkarni u32 transceiver_data; 699*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_STATE_MASK 0x000000FF 700*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_STATE_SHIFT 0x0 701*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00 702*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_STATE_PRESENT 0x01 703*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_STATE_VALID 0x03 704*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_STATE_UPDATING 0x08 705*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_MASK 0x0000FF00 706*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_SHIFT 0x8 707*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_NONE 0x00 708*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_UNKNOWN 0xFF 709*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01 /* 1G Passive copper cable */ 710*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02 /* 1G Active copper cable */ 711*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_1G_LX 0x03 712*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_1G_SX 0x04 713*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_10G_SR 0x05 714*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_10G_LR 0x06 715*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07 716*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_10G_ER 0x08 717*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09 /* 10G Passive copper cable */ 718*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a /* 10G Active copper cable */ 719*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b 720*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c 721*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d 722*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e 723*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f /* Active optical cable */ 724*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10 725*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11 726*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12 727*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13 /* Active copper cable */ 728*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14 729*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15 730*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16 /* 25G Passive copper cable - short */ 731*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17 /* 25G Active copper cable - short */ 732*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18 /* 25G Passive copper cable - medium */ 733*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19 /* 25G Active copper cable - medium */ 734*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a /* 25G Passive copper cable - long */ 735*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b /* 25G Active copper cable - long */ 736*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c 737*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d 738*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e 739*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_4x10G 0x1f 740*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20 741*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_1000BASET 0x21 742*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30 743*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31 744*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32 745*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33 746*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34 747*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35 748*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36 749*14b24e2bSVaishali Kulkarni u32 wol_info; 750*14b24e2bSVaishali Kulkarni u32 wol_pkt_len; 751*14b24e2bSVaishali Kulkarni u32 wol_pkt_details; 752*14b24e2bSVaishali Kulkarni struct dcb_dscp_map dcb_dscp_map; 753*14b24e2bSVaishali Kulkarni 754*14b24e2bSVaishali Kulkarni u32 eee_status; 755*14b24e2bSVaishali Kulkarni #define EEE_ACTIVE_BIT (1<<0) /* Set when EEE negotiation is complete. */ 756*14b24e2bSVaishali Kulkarni 757*14b24e2bSVaishali Kulkarni #define EEE_LD_ADV_STATUS_MASK 0x000000f0 /* Shows the Local Device EEE capabilities */ 758*14b24e2bSVaishali Kulkarni #define EEE_LD_ADV_STATUS_SHIFT 4 759*14b24e2bSVaishali Kulkarni #define EEE_1G_ADV (1<<1) 760*14b24e2bSVaishali Kulkarni #define EEE_10G_ADV (1<<2) 761*14b24e2bSVaishali Kulkarni #define EEE_LP_ADV_STATUS_MASK 0x00000f00 /* Same values as in EEE_LD_ADV, but for Link Parter */ 762*14b24e2bSVaishali Kulkarni #define EEE_LP_ADV_STATUS_SHIFT 8 763*14b24e2bSVaishali Kulkarni 764*14b24e2bSVaishali Kulkarni u32 eee_remote; /* Used for EEE in LLDP */ 765*14b24e2bSVaishali Kulkarni #define EEE_REMOTE_TW_TX_MASK 0x0000ffff 766*14b24e2bSVaishali Kulkarni #define EEE_REMOTE_TW_TX_SHIFT 0 767*14b24e2bSVaishali Kulkarni #define EEE_REMOTE_TW_RX_MASK 0xffff0000 768*14b24e2bSVaishali Kulkarni #define EEE_REMOTE_TW_RX_SHIFT 16 769*14b24e2bSVaishali Kulkarni 770*14b24e2bSVaishali Kulkarni u32 module_info; 771*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_MONITORING_TYPE_MASK 0x000000FF 772*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_MONITORING_TYPE_OFFSET 0 773*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_ADDR_CHNG_REQUIRED (1 << 2) 774*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_RCV_PWR_MEASURE_TYPE (1 << 3) 775*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_EXTERNALLY_CALIBRATED (1 << 4) 776*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_INTERNALLY_CALIBRATED (1 << 5) 777*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_HAS_DIAGNOSTIC (1 << 6) 778*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_IDENT_MASK 0x0000ff00 779*14b24e2bSVaishali Kulkarni #define ETH_TRANSCEIVER_IDENT_OFFSET 8 780*14b24e2bSVaishali Kulkarni }; 781*14b24e2bSVaishali Kulkarni 782*14b24e2bSVaishali Kulkarni /**************************************/ 783*14b24e2bSVaishali Kulkarni /* */ 784*14b24e2bSVaishali Kulkarni /* P U B L I C F U N C */ 785*14b24e2bSVaishali Kulkarni /* */ 786*14b24e2bSVaishali Kulkarni /**************************************/ 787*14b24e2bSVaishali Kulkarni 788*14b24e2bSVaishali Kulkarni struct public_func { 789*14b24e2bSVaishali Kulkarni 790*14b24e2bSVaishali Kulkarni u32 iscsi_boot_signature; 791*14b24e2bSVaishali Kulkarni u32 iscsi_boot_block_offset; 792*14b24e2bSVaishali Kulkarni 793*14b24e2bSVaishali Kulkarni /* MTU size per funciton is needed for the OV feature */ 794*14b24e2bSVaishali Kulkarni u32 mtu_size; 795*14b24e2bSVaishali Kulkarni /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */ 796*14b24e2bSVaishali Kulkarni /* For PCP values 0-3 use the map lower */ 797*14b24e2bSVaishali Kulkarni /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1, 798*14b24e2bSVaishali Kulkarni * 0x0000FF00 - PCP 2, 0x000000FF PCP 3 799*14b24e2bSVaishali Kulkarni */ 800*14b24e2bSVaishali Kulkarni u32 c2s_pcp_map_lower; 801*14b24e2bSVaishali Kulkarni /* For PCP values 4-7 use the map upper */ 802*14b24e2bSVaishali Kulkarni /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5, 803*14b24e2bSVaishali Kulkarni * 0x0000FF00 - PCP 6, 0x000000FF PCP 7 804*14b24e2bSVaishali Kulkarni */ 805*14b24e2bSVaishali Kulkarni u32 c2s_pcp_map_upper; 806*14b24e2bSVaishali Kulkarni 807*14b24e2bSVaishali Kulkarni /* For PCP default value get the MSB byte of the map default */ 808*14b24e2bSVaishali Kulkarni u32 c2s_pcp_map_default; 809*14b24e2bSVaishali Kulkarni 810*14b24e2bSVaishali Kulkarni u32 reserved[4]; 811*14b24e2bSVaishali Kulkarni 812*14b24e2bSVaishali Kulkarni // replace old mf_cfg 813*14b24e2bSVaishali Kulkarni u32 config; 814*14b24e2bSVaishali Kulkarni /* E/R/I/D */ 815*14b24e2bSVaishali Kulkarni /* function 0 of each port cannot be hidden */ 816*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 817*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002 818*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001 819*14b24e2bSVaishali Kulkarni 820*14b24e2bSVaishali Kulkarni 821*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0 822*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_PROTOCOL_SHIFT 4 823*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000 824*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010 825*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020 826*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030 827*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030 828*14b24e2bSVaishali Kulkarni 829*14b24e2bSVaishali Kulkarni /* MINBW, MAXBW */ 830*14b24e2bSVaishali Kulkarni /* value range - 0..100, increments in 1 % */ 831*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00 832*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_MIN_BW_SHIFT 8 833*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 834*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000 835*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_MAX_BW_SHIFT 16 836*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000 837*14b24e2bSVaishali Kulkarni 838*14b24e2bSVaishali Kulkarni /*RDMA PROTOCL*/ 839*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_RDMA_PROTOCOL_MASK 0x03000000 840*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_RDMA_PROTOCOL_SHIFT 24 841*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_RDMA_PROTOCOL_NONE 0x00000000 842*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_RDMA_PROTOCOL_ROCE 0x01000000 843*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_RDMA_PROTOCOL_IWARP 0x02000000 844*14b24e2bSVaishali Kulkarni /*for future support*/ 845*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_RDMA_PROTOCOL_BOTH 0x03000000 846*14b24e2bSVaishali Kulkarni 847*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_BOOT_MODE_MASK 0x0C000000 848*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_BOOT_MODE_SHIFT 26 849*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_BOOT_MODE_BIOS_CTRL 0x00000000 850*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_BOOT_MODE_DISABLED 0x04000000 851*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_BOOT_MODE_ENABLED 0x08000000 852*14b24e2bSVaishali Kulkarni 853*14b24e2bSVaishali Kulkarni u32 status; 854*14b24e2bSVaishali Kulkarni #define FUNC_STATUS_VLINK_DOWN 0x00000001 855*14b24e2bSVaishali Kulkarni 856*14b24e2bSVaishali Kulkarni u32 mac_upper; /* MAC */ 857*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 858*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 859*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 860*14b24e2bSVaishali Kulkarni u32 mac_lower; 861*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 862*14b24e2bSVaishali Kulkarni 863*14b24e2bSVaishali Kulkarni u32 fcoe_wwn_port_name_upper; 864*14b24e2bSVaishali Kulkarni u32 fcoe_wwn_port_name_lower; 865*14b24e2bSVaishali Kulkarni 866*14b24e2bSVaishali Kulkarni u32 fcoe_wwn_node_name_upper; 867*14b24e2bSVaishali Kulkarni u32 fcoe_wwn_node_name_lower; 868*14b24e2bSVaishali Kulkarni 869*14b24e2bSVaishali Kulkarni u32 ovlan_stag; /* tags */ 870*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff 871*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_OV_STAG_SHIFT 0 872*14b24e2bSVaishali Kulkarni #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK 873*14b24e2bSVaishali Kulkarni 874*14b24e2bSVaishali Kulkarni u32 pf_allocation; /* vf per pf */ 875*14b24e2bSVaishali Kulkarni 876*14b24e2bSVaishali Kulkarni u32 preserve_data; /* Will be used bt CCM */ 877*14b24e2bSVaishali Kulkarni 878*14b24e2bSVaishali Kulkarni u32 driver_last_activity_ts; 879*14b24e2bSVaishali Kulkarni 880*14b24e2bSVaishali Kulkarni /* 881*14b24e2bSVaishali Kulkarni * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 882*14b24e2bSVaishali Kulkarni * VFs 883*14b24e2bSVaishali Kulkarni */ 884*14b24e2bSVaishali Kulkarni u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */ 885*14b24e2bSVaishali Kulkarni 886*14b24e2bSVaishali Kulkarni u32 drv_id; 887*14b24e2bSVaishali Kulkarni #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff 888*14b24e2bSVaishali Kulkarni #define DRV_ID_PDA_COMP_VER_SHIFT 0 889*14b24e2bSVaishali Kulkarni 890*14b24e2bSVaishali Kulkarni #define LOAD_REQ_HSI_VERSION 2 891*14b24e2bSVaishali Kulkarni #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000 892*14b24e2bSVaishali Kulkarni #define DRV_ID_MCP_HSI_VER_SHIFT 16 893*14b24e2bSVaishali Kulkarni #define DRV_ID_MCP_HSI_VER_CURRENT (LOAD_REQ_HSI_VERSION << DRV_ID_MCP_HSI_VER_SHIFT) 894*14b24e2bSVaishali Kulkarni 895*14b24e2bSVaishali Kulkarni #define DRV_ID_DRV_TYPE_MASK 0x7f000000 896*14b24e2bSVaishali Kulkarni #define DRV_ID_DRV_TYPE_SHIFT 24 897*14b24e2bSVaishali Kulkarni #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT) 898*14b24e2bSVaishali Kulkarni #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT) 899*14b24e2bSVaishali Kulkarni #define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_SHIFT) 900*14b24e2bSVaishali Kulkarni #define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_SHIFT) 901*14b24e2bSVaishali Kulkarni #define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_SHIFT) 902*14b24e2bSVaishali Kulkarni #define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_SHIFT) 903*14b24e2bSVaishali Kulkarni #define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_SHIFT) 904*14b24e2bSVaishali Kulkarni #define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_SHIFT) 905*14b24e2bSVaishali Kulkarni #define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_SHIFT) 906*14b24e2bSVaishali Kulkarni 907*14b24e2bSVaishali Kulkarni #define DRV_ID_DRV_TYPE_OS (DRV_ID_DRV_TYPE_LINUX | DRV_ID_DRV_TYPE_WINDOWS | \ 908*14b24e2bSVaishali Kulkarni DRV_ID_DRV_TYPE_SOLARIS | DRV_ID_DRV_TYPE_VMWARE | \ 909*14b24e2bSVaishali Kulkarni DRV_ID_DRV_TYPE_FREEBSD | DRV_ID_DRV_TYPE_AIX) 910*14b24e2bSVaishali Kulkarni 911*14b24e2bSVaishali Kulkarni #define DRV_ID_DRV_INIT_HW_MASK 0x80000000 912*14b24e2bSVaishali Kulkarni #define DRV_ID_DRV_INIT_HW_SHIFT 31 913*14b24e2bSVaishali Kulkarni #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT) 914*14b24e2bSVaishali Kulkarni }; 915*14b24e2bSVaishali Kulkarni 916*14b24e2bSVaishali Kulkarni /**************************************/ 917*14b24e2bSVaishali Kulkarni /* */ 918*14b24e2bSVaishali Kulkarni /* P U B L I C M B */ 919*14b24e2bSVaishali Kulkarni /* */ 920*14b24e2bSVaishali Kulkarni /**************************************/ 921*14b24e2bSVaishali Kulkarni /* This is the only section that the driver can write to, and each */ 922*14b24e2bSVaishali Kulkarni /* Basically each driver request to set feature parameters, 923*14b24e2bSVaishali Kulkarni * will be done using a different command, which will be linked 924*14b24e2bSVaishali Kulkarni * to a specific data structure from the union below. 925*14b24e2bSVaishali Kulkarni * For huge strucuture, the common blank structure should be used. 926*14b24e2bSVaishali Kulkarni */ 927*14b24e2bSVaishali Kulkarni 928*14b24e2bSVaishali Kulkarni struct mcp_mac { 929*14b24e2bSVaishali Kulkarni u32 mac_upper; /* Upper 16 bits are always zeroes */ 930*14b24e2bSVaishali Kulkarni u32 mac_lower; 931*14b24e2bSVaishali Kulkarni }; 932*14b24e2bSVaishali Kulkarni 933*14b24e2bSVaishali Kulkarni struct mcp_val64 { 934*14b24e2bSVaishali Kulkarni u32 lo; 935*14b24e2bSVaishali Kulkarni u32 hi; 936*14b24e2bSVaishali Kulkarni }; 937*14b24e2bSVaishali Kulkarni 938*14b24e2bSVaishali Kulkarni struct mcp_file_att { 939*14b24e2bSVaishali Kulkarni u32 nvm_start_addr; 940*14b24e2bSVaishali Kulkarni u32 len; 941*14b24e2bSVaishali Kulkarni }; 942*14b24e2bSVaishali Kulkarni 943*14b24e2bSVaishali Kulkarni struct bist_nvm_image_att { 944*14b24e2bSVaishali Kulkarni u32 return_code; 945*14b24e2bSVaishali Kulkarni u32 image_type; /* Image type */ 946*14b24e2bSVaishali Kulkarni u32 nvm_start_addr; /* NVM address of the image */ 947*14b24e2bSVaishali Kulkarni u32 len; /* Include CRC */ 948*14b24e2bSVaishali Kulkarni }; 949*14b24e2bSVaishali Kulkarni 950*14b24e2bSVaishali Kulkarni #define MCP_DRV_VER_STR_SIZE 16 951*14b24e2bSVaishali Kulkarni #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32)) 952*14b24e2bSVaishali Kulkarni #define MCP_DRV_NVM_BUF_LEN 32 953*14b24e2bSVaishali Kulkarni struct drv_version_stc { 954*14b24e2bSVaishali Kulkarni u32 version; 955*14b24e2bSVaishali Kulkarni u8 name[MCP_DRV_VER_STR_SIZE - 4]; 956*14b24e2bSVaishali Kulkarni }; 957*14b24e2bSVaishali Kulkarni 958*14b24e2bSVaishali Kulkarni /* statistics for ncsi */ 959*14b24e2bSVaishali Kulkarni struct lan_stats_stc { 960*14b24e2bSVaishali Kulkarni u64 ucast_rx_pkts; 961*14b24e2bSVaishali Kulkarni u64 ucast_tx_pkts; 962*14b24e2bSVaishali Kulkarni u32 fcs_err; 963*14b24e2bSVaishali Kulkarni u32 rserved; 964*14b24e2bSVaishali Kulkarni }; 965*14b24e2bSVaishali Kulkarni 966*14b24e2bSVaishali Kulkarni struct fcoe_stats_stc { 967*14b24e2bSVaishali Kulkarni u64 rx_pkts; 968*14b24e2bSVaishali Kulkarni u64 tx_pkts; 969*14b24e2bSVaishali Kulkarni u32 fcs_err; 970*14b24e2bSVaishali Kulkarni u32 login_failure; 971*14b24e2bSVaishali Kulkarni }; 972*14b24e2bSVaishali Kulkarni 973*14b24e2bSVaishali Kulkarni struct iscsi_stats_stc { 974*14b24e2bSVaishali Kulkarni u64 rx_pdus; 975*14b24e2bSVaishali Kulkarni u64 tx_pdus; 976*14b24e2bSVaishali Kulkarni u64 rx_bytes; 977*14b24e2bSVaishali Kulkarni u64 tx_bytes; 978*14b24e2bSVaishali Kulkarni }; 979*14b24e2bSVaishali Kulkarni 980*14b24e2bSVaishali Kulkarni struct rdma_stats_stc { 981*14b24e2bSVaishali Kulkarni u64 rx_pkts; 982*14b24e2bSVaishali Kulkarni u64 tx_pkts; 983*14b24e2bSVaishali Kulkarni u64 rx_bytes; 984*14b24e2bSVaishali Kulkarni u64 tx_bytes; 985*14b24e2bSVaishali Kulkarni }; 986*14b24e2bSVaishali Kulkarni 987*14b24e2bSVaishali Kulkarni struct ocbb_data_stc { 988*14b24e2bSVaishali Kulkarni u32 ocbb_host_addr; 989*14b24e2bSVaishali Kulkarni u32 ocsd_host_addr; 990*14b24e2bSVaishali Kulkarni u32 ocsd_req_update_interval; 991*14b24e2bSVaishali Kulkarni }; 992*14b24e2bSVaishali Kulkarni 993*14b24e2bSVaishali Kulkarni #define MAX_NUM_OF_SENSORS 7 994*14b24e2bSVaishali Kulkarni #define MFW_SENSOR_LOCATION_INTERNAL 1 995*14b24e2bSVaishali Kulkarni #define MFW_SENSOR_LOCATION_EXTERNAL 2 996*14b24e2bSVaishali Kulkarni #define MFW_SENSOR_LOCATION_SFP 3 997*14b24e2bSVaishali Kulkarni 998*14b24e2bSVaishali Kulkarni #define SENSOR_LOCATION_SHIFT 0 999*14b24e2bSVaishali Kulkarni #define SENSOR_LOCATION_MASK 0x000000ff 1000*14b24e2bSVaishali Kulkarni #define THRESHOLD_HIGH_SHIFT 8 1001*14b24e2bSVaishali Kulkarni #define THRESHOLD_HIGH_MASK 0x0000ff00 1002*14b24e2bSVaishali Kulkarni #define CRITICAL_TEMPERATURE_SHIFT 16 1003*14b24e2bSVaishali Kulkarni #define CRITICAL_TEMPERATURE_MASK 0x00ff0000 1004*14b24e2bSVaishali Kulkarni #define CURRENT_TEMP_SHIFT 24 1005*14b24e2bSVaishali Kulkarni #define CURRENT_TEMP_MASK 0xff000000 1006*14b24e2bSVaishali Kulkarni struct temperature_status_stc { 1007*14b24e2bSVaishali Kulkarni u32 num_of_sensors; 1008*14b24e2bSVaishali Kulkarni u32 sensor[MAX_NUM_OF_SENSORS]; 1009*14b24e2bSVaishali Kulkarni }; 1010*14b24e2bSVaishali Kulkarni 1011*14b24e2bSVaishali Kulkarni /* crash dump configuration header */ 1012*14b24e2bSVaishali Kulkarni struct mdump_config_stc { 1013*14b24e2bSVaishali Kulkarni u32 version; 1014*14b24e2bSVaishali Kulkarni u32 config; 1015*14b24e2bSVaishali Kulkarni u32 epoc; 1016*14b24e2bSVaishali Kulkarni u32 num_of_logs; 1017*14b24e2bSVaishali Kulkarni u32 valid_logs; 1018*14b24e2bSVaishali Kulkarni }; 1019*14b24e2bSVaishali Kulkarni 1020*14b24e2bSVaishali Kulkarni enum resource_id_enum { 1021*14b24e2bSVaishali Kulkarni RESOURCE_NUM_SB_E = 0, 1022*14b24e2bSVaishali Kulkarni RESOURCE_NUM_L2_QUEUE_E = 1, 1023*14b24e2bSVaishali Kulkarni RESOURCE_NUM_VPORT_E = 2, 1024*14b24e2bSVaishali Kulkarni RESOURCE_NUM_VMQ_E = 3, 1025*14b24e2bSVaishali Kulkarni RESOURCE_FACTOR_NUM_RSS_PF_E = 4, /* Not a real resource!! it's a factor used to calculate others */ 1026*14b24e2bSVaishali Kulkarni RESOURCE_FACTOR_RSS_PER_VF_E = 5, /* Not a real resource!! it's a factor used to calculate others */ 1027*14b24e2bSVaishali Kulkarni RESOURCE_NUM_RL_E = 6, 1028*14b24e2bSVaishali Kulkarni RESOURCE_NUM_PQ_E = 7, 1029*14b24e2bSVaishali Kulkarni RESOURCE_NUM_VF_E = 8, 1030*14b24e2bSVaishali Kulkarni RESOURCE_VFC_FILTER_E = 9, 1031*14b24e2bSVaishali Kulkarni RESOURCE_ILT_E = 10, 1032*14b24e2bSVaishali Kulkarni RESOURCE_CQS_E = 11, 1033*14b24e2bSVaishali Kulkarni RESOURCE_GFT_PROFILES_E = 12, 1034*14b24e2bSVaishali Kulkarni RESOURCE_NUM_TC_E = 13, 1035*14b24e2bSVaishali Kulkarni RESOURCE_NUM_RSS_ENGINES_E = 14, 1036*14b24e2bSVaishali Kulkarni RESOURCE_LL2_QUEUE_E = 15, 1037*14b24e2bSVaishali Kulkarni RESOURCE_RDMA_STATS_QUEUE_E = 16, 1038*14b24e2bSVaishali Kulkarni RESOURCE_BDQ_E = 17, 1039*14b24e2bSVaishali Kulkarni RESOURCE_MAX_NUM, 1040*14b24e2bSVaishali Kulkarni RESOURCE_NUM_INVALID = 0xFFFFFFFF 1041*14b24e2bSVaishali Kulkarni }; 1042*14b24e2bSVaishali Kulkarni 1043*14b24e2bSVaishali Kulkarni /* Resource ID is to be filled by the driver in the MB request 1044*14b24e2bSVaishali Kulkarni * Size, offset & flags to be filled by the MFW in the MB response 1045*14b24e2bSVaishali Kulkarni */ 1046*14b24e2bSVaishali Kulkarni struct resource_info { 1047*14b24e2bSVaishali Kulkarni enum resource_id_enum res_id; 1048*14b24e2bSVaishali Kulkarni u32 size; /* number of allocated resources */ 1049*14b24e2bSVaishali Kulkarni u32 offset; /* Offset of the 1st resource */ 1050*14b24e2bSVaishali Kulkarni u32 vf_size; 1051*14b24e2bSVaishali Kulkarni u32 vf_offset; 1052*14b24e2bSVaishali Kulkarni u32 flags; 1053*14b24e2bSVaishali Kulkarni #define RESOURCE_ELEMENT_STRICT (1 << 0) 1054*14b24e2bSVaishali Kulkarni }; 1055*14b24e2bSVaishali Kulkarni 1056*14b24e2bSVaishali Kulkarni struct mcp_wwn { 1057*14b24e2bSVaishali Kulkarni u32 wwn_upper; 1058*14b24e2bSVaishali Kulkarni u32 wwn_lower; 1059*14b24e2bSVaishali Kulkarni }; 1060*14b24e2bSVaishali Kulkarni 1061*14b24e2bSVaishali Kulkarni #define DRV_ROLE_NONE 0 1062*14b24e2bSVaishali Kulkarni #define DRV_ROLE_PREBOOT 1 1063*14b24e2bSVaishali Kulkarni #define DRV_ROLE_OS 2 1064*14b24e2bSVaishali Kulkarni #define DRV_ROLE_KDUMP 3 1065*14b24e2bSVaishali Kulkarni 1066*14b24e2bSVaishali Kulkarni struct load_req_stc { 1067*14b24e2bSVaishali Kulkarni u32 drv_ver_0; 1068*14b24e2bSVaishali Kulkarni u32 drv_ver_1; 1069*14b24e2bSVaishali Kulkarni u32 fw_ver; 1070*14b24e2bSVaishali Kulkarni u32 misc0; 1071*14b24e2bSVaishali Kulkarni #define LOAD_REQ_ROLE_MASK 0x000000FF 1072*14b24e2bSVaishali Kulkarni #define LOAD_REQ_ROLE_SHIFT 0 1073*14b24e2bSVaishali Kulkarni #define LOAD_REQ_LOCK_TO_MASK 0x0000FF00 1074*14b24e2bSVaishali Kulkarni #define LOAD_REQ_LOCK_TO_SHIFT 8 1075*14b24e2bSVaishali Kulkarni #define LOAD_REQ_LOCK_TO_DEFAULT 0 1076*14b24e2bSVaishali Kulkarni #define LOAD_REQ_LOCK_TO_NONE 255 1077*14b24e2bSVaishali Kulkarni #define LOAD_REQ_FORCE_MASK 0x000F0000 1078*14b24e2bSVaishali Kulkarni #define LOAD_REQ_FORCE_SHIFT 16 1079*14b24e2bSVaishali Kulkarni #define LOAD_REQ_FORCE_NONE 0 1080*14b24e2bSVaishali Kulkarni #define LOAD_REQ_FORCE_PF 1 1081*14b24e2bSVaishali Kulkarni #define LOAD_REQ_FORCE_ALL 2 1082*14b24e2bSVaishali Kulkarni #define LOAD_REQ_FLAGS0_MASK 0x00F00000 1083*14b24e2bSVaishali Kulkarni #define LOAD_REQ_FLAGS0_SHIFT 20 1084*14b24e2bSVaishali Kulkarni #define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0) 1085*14b24e2bSVaishali Kulkarni }; 1086*14b24e2bSVaishali Kulkarni 1087*14b24e2bSVaishali Kulkarni struct load_rsp_stc { 1088*14b24e2bSVaishali Kulkarni u32 drv_ver_0; 1089*14b24e2bSVaishali Kulkarni u32 drv_ver_1; 1090*14b24e2bSVaishali Kulkarni u32 fw_ver; 1091*14b24e2bSVaishali Kulkarni u32 misc0; 1092*14b24e2bSVaishali Kulkarni #define LOAD_RSP_ROLE_MASK 0x000000FF 1093*14b24e2bSVaishali Kulkarni #define LOAD_RSP_ROLE_SHIFT 0 1094*14b24e2bSVaishali Kulkarni #define LOAD_RSP_HSI_MASK 0x0000FF00 1095*14b24e2bSVaishali Kulkarni #define LOAD_RSP_HSI_SHIFT 8 1096*14b24e2bSVaishali Kulkarni #define LOAD_RSP_FLAGS0_MASK 0x000F0000 1097*14b24e2bSVaishali Kulkarni #define LOAD_RSP_FLAGS0_SHIFT 16 1098*14b24e2bSVaishali Kulkarni #define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0) 1099*14b24e2bSVaishali Kulkarni }; 1100*14b24e2bSVaishali Kulkarni 1101*14b24e2bSVaishali Kulkarni struct mdump_retain_data_stc { 1102*14b24e2bSVaishali Kulkarni u32 valid; 1103*14b24e2bSVaishali Kulkarni u32 epoch; 1104*14b24e2bSVaishali Kulkarni u32 pf; 1105*14b24e2bSVaishali Kulkarni u32 status; 1106*14b24e2bSVaishali Kulkarni }; 1107*14b24e2bSVaishali Kulkarni 1108*14b24e2bSVaishali Kulkarni union drv_union_data { 1109*14b24e2bSVaishali Kulkarni struct mcp_mac wol_mac; /* UNLOAD_DONE */ 1110*14b24e2bSVaishali Kulkarni 1111*14b24e2bSVaishali Kulkarni /* This configuration should be set by the driver for the LINK_SET command. */ 1112*14b24e2bSVaishali Kulkarni struct eth_phy_cfg drv_phy_cfg; 1113*14b24e2bSVaishali Kulkarni 1114*14b24e2bSVaishali Kulkarni struct mcp_val64 val64; /* For PHY / AVS commands */ 1115*14b24e2bSVaishali Kulkarni 1116*14b24e2bSVaishali Kulkarni u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 1117*14b24e2bSVaishali Kulkarni 1118*14b24e2bSVaishali Kulkarni struct mcp_file_att file_att; 1119*14b24e2bSVaishali Kulkarni 1120*14b24e2bSVaishali Kulkarni u32 ack_vf_disabled[VF_MAX_STATIC / 32]; 1121*14b24e2bSVaishali Kulkarni 1122*14b24e2bSVaishali Kulkarni struct drv_version_stc drv_version; 1123*14b24e2bSVaishali Kulkarni 1124*14b24e2bSVaishali Kulkarni struct lan_stats_stc lan_stats; 1125*14b24e2bSVaishali Kulkarni struct fcoe_stats_stc fcoe_stats; 1126*14b24e2bSVaishali Kulkarni struct iscsi_stats_stc iscsi_stats; 1127*14b24e2bSVaishali Kulkarni struct rdma_stats_stc rdma_stats; 1128*14b24e2bSVaishali Kulkarni struct ocbb_data_stc ocbb_info; 1129*14b24e2bSVaishali Kulkarni struct temperature_status_stc temp_info; 1130*14b24e2bSVaishali Kulkarni struct resource_info resource; 1131*14b24e2bSVaishali Kulkarni struct bist_nvm_image_att nvm_image_att; 1132*14b24e2bSVaishali Kulkarni struct mdump_config_stc mdump_config; 1133*14b24e2bSVaishali Kulkarni struct mcp_mac lldp_mac; 1134*14b24e2bSVaishali Kulkarni struct mcp_wwn fcoe_fabric_name; 1135*14b24e2bSVaishali Kulkarni u32 dword; 1136*14b24e2bSVaishali Kulkarni 1137*14b24e2bSVaishali Kulkarni struct load_req_stc load_req; 1138*14b24e2bSVaishali Kulkarni struct load_rsp_stc load_rsp; 1139*14b24e2bSVaishali Kulkarni struct mdump_retain_data_stc mdump_retain; 1140*14b24e2bSVaishali Kulkarni /* ... */ 1141*14b24e2bSVaishali Kulkarni }; 1142*14b24e2bSVaishali Kulkarni 1143*14b24e2bSVaishali Kulkarni struct public_drv_mb { 1144*14b24e2bSVaishali Kulkarni 1145*14b24e2bSVaishali Kulkarni u32 drv_mb_header; 1146*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_MASK 0xffff0000 1147*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1148*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1149*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_INIT_HW 0x12000000 1150*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_CANCEL_LOAD_REQ 0x13000000 1151*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000 1152*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1153*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_INIT_PHY 0x22000000 1154*14b24e2bSVaishali Kulkarni /* Params - FORCE - Reinitialize the link regardless of LFA */ 1155*14b24e2bSVaishali Kulkarni /* - DONT_CARE - Don't flap the link if up */ 1156*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_LINK_RESET 0x23000000 1157*14b24e2bSVaishali Kulkarni 1158*14b24e2bSVaishali Kulkarni // Vitaly: LLDP commands 1159*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_SET_LLDP 0x24000000 1160*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_SET_DCBX 0x25000000 1161*14b24e2bSVaishali Kulkarni /* OneView feature driver HSI*/ 1162*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000 1163*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000 1164*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000 1165*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000 1166*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_NIG_DRAIN 0x30000000 1167*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000 1168*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000 1169*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000 1170*14b24e2bSVaishali Kulkarni #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000 /* DRV_MB Param: driver version supp, FW_MB param: MFW version supp, data: struct resource_info */ 1171*14b24e2bSVaishali Kulkarni #define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000 1172*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OV_UPDATE_WOL 0x38000000 1173*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE 0x39000000 1174*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000 1175*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OEM_UPDATE_FCOE_CVID 0x3c000000 1176*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OEM_UPDATE_FCOE_FABRIC_NAME 0x3d000000 1177*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OEM_UPDATE_BOOT_CFG 0x3e000000 1178*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OEM_RESET_TO_DEFAULT 0x3f000000 1179*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OV_GET_CURR_CFG 0x40000000 1180*14b24e2bSVaishali Kulkarni 1181*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED 0x02000000 /*deprecated don't use*/ 1182*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000 1183*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1184*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000 1185*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_CFG_PF_VFS_MSIX 0xc0020000 1186*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000 /* Param is either DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW/IMAGE */ 1187*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000 /* Param should be set to the transaction size (up to 64 bytes) */ 1188*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000 /* MFW will place the file offset and len in file_att struct */ 1189*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000 /* Read 32bytes of nvram data. Param is [0:23] ??? Offset [24:31] ??? Len in Bytes*/ 1190*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000 /* Writes up to 32Bytes to nvram. Param is [0:23] ??? Offset [24:31] ??? Len in Bytes. In case this address is in the range of secured file in secured mode, the operation will fail */ 1191*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_NVM_DEL_FILE 0x00080000 /* Delete a file from nvram. Param is image_type. */ 1192*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_MCP_RESET 0x00090000 /* Reset MCP when no NVM operation is going on, and no drivers are loaded. In case operation succeed, MCP will not ack back. */ 1193*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_SET_SECURE_MODE 0x000a0000 /* Temporary command to set secure mode, where the param is 0 (None secure) / 1 (Secure) / 2 (Full-Secure) */ 1194*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_PHY_RAW_READ 0x000b0000 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, [30:31] - port*/ 1195*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_PHY_RAW_WRITE 0x000c0000 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, [30:31] - port */ 1196*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_PHY_CORE_READ 0x000d0000 /* Param: [0:15] - Address, [30:31] - port */ 1197*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000 /* Param: [0:15] - Address, [30:31] - port */ 1198*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_SET_VERSION 0x000f0000 /* Param: [0:3] - version, [4:15] - name (null terminated) */ 1199*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_MCP_HALT 0x00100000 /* Halts the MCP. To resume MCP, user will need to use MCP_REG_CPU_STATE/MCP_REG_CPU_MODE registers. */ 1200*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_SET_VMAC 0x00110000 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN */ 1201*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_GET_VMAC 0x00120000 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN */ 1202*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_VMAC_TYPE_SHIFT 4 1203*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30 1204*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_VMAC_TYPE_MAC 1 1205*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2 1206*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_VMAC_TYPE_WWPN 3 1207*14b24e2bSVaishali Kulkarni 1208*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_GET_STATS 0x00130000 /* Get statistics from pf, params [31:4] - reserved, [3:0] - stats type */ 1209*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_STATS_TYPE_LAN 1 1210*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_STATS_TYPE_FCOE 2 1211*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_STATS_TYPE_ISCSI 3 1212*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_STATS_TYPE_RDMA 4 1213*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_PMD_DIAG_DUMP 0x00140000 /* Host shall provide buffer and size for MFW */ 1214*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_PMD_DIAG_EYE 0x00150000 /* Host shall provide buffer and size for MFW */ 1215*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_TRANSCEIVER_READ 0x00160000 /* Param: [0:1] - Port, [2:7] - read size, [8:15] - I2C address, [16:31] - offset */ 1216*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_TRANSCEIVER_WRITE 0x00170000 /* Param: [0:1] - Port, [2:7] - write size, [8:15] - I2C address, [16:31] - offset */ 1217*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OCBB_DATA 0x00180000 /* indicate OCBB related information */ 1218*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_SET_BW 0x00190000 /* Set function BW, params[15:8] - min, params[7:0] - max */ 1219*14b24e2bSVaishali Kulkarni #define BW_MAX_MASK 0x000000ff 1220*14b24e2bSVaishali Kulkarni #define BW_MAX_SHIFT 0 1221*14b24e2bSVaishali Kulkarni #define BW_MIN_MASK 0x0000ff00 1222*14b24e2bSVaishali Kulkarni #define BW_MIN_SHIFT 8 1223*14b24e2bSVaishali Kulkarni 1224*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000 /* When param is set to 1, all parities will be masked(disabled). When params are set to 0, parities will be unmasked again. */ 1225*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_INDUCE_FAILURE 0x001b0000 /* param[0] - Simulate fan failure, param[1] - simulate over temp. */ 1226*14b24e2bSVaishali Kulkarni #define DRV_MSG_FAN_FAILURE_TYPE (1 << 0) 1227*14b24e2bSVaishali Kulkarni #define DRV_MSG_TEMPERATURE_FAILURE_TYPE (1 << 1) 1228*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_GPIO_READ 0x001c0000 /* Param: [0:15] - gpio number */ 1229*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_GPIO_WRITE 0x001d0000 /* Param: [0:15] - gpio number, [16:31] - gpio value */ 1230*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_BIST_TEST 0x001e0000 /* Param: [0:7] - test enum, [8:15] - image index, [16:31] - reserved */ 1231*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_GET_TEMPERATURE 0x001f0000 1232*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_SET_LED_MODE 0x00200000 /* Set LED mode params :0 operational, 1 LED turn ON, 2 LED turn OFF */ 1233*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_TIMESTAMP 0x00210000 /* drv_data[7:0] - EPOC in seconds, drv_data[15:8] - driver version (MAJ MIN BUILD SUB) */ 1234*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_EMPTY_MB 0x00220000 /* This is an empty mailbox just return OK*/ 1235*14b24e2bSVaishali Kulkarni 1236*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_RESOURCE_CMD 0x00230000 /* Param[0:4] - resource number (0-31), Param[5:7] - opcode, param[15:8] - age */ 1237*14b24e2bSVaishali Kulkarni 1238*14b24e2bSVaishali Kulkarni #define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F 1239*14b24e2bSVaishali Kulkarni #define RESOURCE_CMD_REQ_RESC_SHIFT 0 1240*14b24e2bSVaishali Kulkarni #define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0 1241*14b24e2bSVaishali Kulkarni #define RESOURCE_CMD_REQ_OPCODE_SHIFT 5 1242*14b24e2bSVaishali Kulkarni #define RESOURCE_OPCODE_REQ 1 /* request resource ownership with default aging */ 1243*14b24e2bSVaishali Kulkarni #define RESOURCE_OPCODE_REQ_WO_AGING 2 /* request resource ownership without aging */ 1244*14b24e2bSVaishali Kulkarni #define RESOURCE_OPCODE_REQ_W_AGING 3 /* request resource ownership with specific aging timer (in seconds) */ 1245*14b24e2bSVaishali Kulkarni #define RESOURCE_OPCODE_RELEASE 4 /* release resource */ 1246*14b24e2bSVaishali Kulkarni #define RESOURCE_OPCODE_FORCE_RELEASE 5 /* force resource release */ 1247*14b24e2bSVaishali Kulkarni #define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00 1248*14b24e2bSVaishali Kulkarni #define RESOURCE_CMD_REQ_AGE_SHIFT 8 1249*14b24e2bSVaishali Kulkarni 1250*14b24e2bSVaishali Kulkarni #define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF 1251*14b24e2bSVaishali Kulkarni #define RESOURCE_CMD_RSP_OWNER_SHIFT 0 1252*14b24e2bSVaishali Kulkarni #define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700 1253*14b24e2bSVaishali Kulkarni #define RESOURCE_CMD_RSP_OPCODE_SHIFT 8 1254*14b24e2bSVaishali Kulkarni #define RESOURCE_OPCODE_GNT 1 /* resource is free and granted to requester */ 1255*14b24e2bSVaishali Kulkarni #define RESOURCE_OPCODE_BUSY 2 /* resource is busy, param[7:0] indicates owner as follow 0-15 = PF0-15, 16 = MFW, 17 = diag over serial */ 1256*14b24e2bSVaishali Kulkarni #define RESOURCE_OPCODE_RELEASED 3 /* indicate release request was acknowledged */ 1257*14b24e2bSVaishali Kulkarni #define RESOURCE_OPCODE_RELEASED_PREVIOUS 4 /* indicate release request was previously received by other owner */ 1258*14b24e2bSVaishali Kulkarni #define RESOURCE_OPCODE_WRONG_OWNER 5 /* indicate wrong owner during release */ 1259*14b24e2bSVaishali Kulkarni #define RESOURCE_OPCODE_UNKNOWN_CMD 255 1260*14b24e2bSVaishali Kulkarni 1261*14b24e2bSVaishali Kulkarni #define RESOURCE_DUMP 0 /* dedicate resource 0 for dump */ 1262*14b24e2bSVaishali Kulkarni 1263*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_GET_MBA_VERSION 0x00240000 /* Get MBA version */ 1264*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_MDUMP_CMD 0x00250000 /* Send crash dump commands with param[3:0] - opcode */ 1265*14b24e2bSVaishali Kulkarni #define MDUMP_DRV_PARAM_OPCODE_MASK 0x0000000f 1266*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_MDUMP_ACK 0x01 /* acknowledge reception of error indication */ 1267*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_MDUMP_SET_VALUES 0x02 /* set epoc and personality as follow: drv_data[3:0] - epoch, drv_data[7:4] - personality */ 1268*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_MDUMP_TRIGGER 0x03 /* trigger crash dump procedure */ 1269*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_MDUMP_GET_CONFIG 0x04 /* Request valid logs and config words */ 1270*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05 /* Set triggers mask. drv_mb_param should indicate (bitwise) which trigger enabled */ 1271*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06 /* Clear all logs */ 1272*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_MDUMP_GET_RETAIN 0x07 /* Get retained data */ 1273*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_MDUMP_CLR_RETAIN 0x08 /* Clear retain data */ 1274*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_MEM_ECC_EVENTS 0x00260000 /* Param: None */ 1275*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_GPIO_INFO 0x00270000 /* Param: [0:15] - gpio number */ 1276*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_EXT_PHY_READ 0x00280000 /* Value will be placed in union */ 1277*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_EXT_PHY_WRITE 0x00290000 /* Value shoud be placed in union */ 1278*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_ADDR_SHIFT 0 1279*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_ADDR_MASK 0x0000FFFF 1280*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_DEVAD_SHIFT 16 1281*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_DEVAD_MASK 0x001F0000 1282*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_PORT_SHIFT 21 1283*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_PORT_MASK 0x00600000 1284*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_EXT_PHY_FW_UPGRADE 0x002a0000 1285*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL 0x002b0000 1286*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_SET_LLDP_MAC 0x002c0000 1287*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_GET_LLDP_MAC 0x002d0000 1288*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OS_WOL 0x002e0000 1289*14b24e2bSVaishali Kulkarni 1290*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_GET_TLV_DONE 0x002f0000 /* Param: None */ 1291*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000 /* Param: Set DRV_MB_PARAM_FEATURE_SUPPORT_* */ 1292*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000 /* return FW_MB_PARAM_FEATURE_SUPPORT_* */ 1293*14b24e2bSVaishali Kulkarni 1294*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_READ_WOL_REG 0X00320000 1295*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_WRITE_WOL_REG 0X00330000 1296*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_GET_WOL_BUFFER 0X00340000 1297*14b24e2bSVaishali Kulkarni 1298*14b24e2bSVaishali Kulkarni #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1299*14b24e2bSVaishali Kulkarni 1300*14b24e2bSVaishali Kulkarni u32 drv_mb_param; 1301*14b24e2bSVaishali Kulkarni /* UNLOAD_REQ params */ 1302*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000 1303*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001 1304*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002 1305*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003 1306*14b24e2bSVaishali Kulkarni 1307*14b24e2bSVaishali Kulkarni /* UNLOAD_DONE_params */ 1308*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001 1309*14b24e2bSVaishali Kulkarni 1310*14b24e2bSVaishali Kulkarni /* INIT_PHY params */ 1311*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001 1312*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002 1313*14b24e2bSVaishali Kulkarni 1314*14b24e2bSVaishali Kulkarni /* LLDP / DCBX params*/ 1315*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001 1316*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0 1317*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006 1318*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_LLDP_AGENT_SHIFT 1 1319*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008 1320*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3 1321*14b24e2bSVaishali Kulkarni 1322*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF 1323*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT 0 1324*14b24e2bSVaishali Kulkarni 1325*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1 1326*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2 1327*14b24e2bSVaishali Kulkarni 1328*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_NVM_OFFSET_SHIFT 0 1329*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF 1330*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_NVM_LEN_SHIFT 24 1331*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000 1332*14b24e2bSVaishali Kulkarni 1333*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_PHY_ADDR_SHIFT 0 1334*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF 1335*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_PHY_LANE_SHIFT 16 1336*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000 1337*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_PHY_SELECT_PORT_SHIFT 29 1338*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000 1339*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_PHY_PORT_SHIFT 30 1340*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000 1341*14b24e2bSVaishali Kulkarni 1342*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_PHYMOD_LANE_SHIFT 0 1343*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_PHYMOD_LANE_MASK 0x000000FF 1344*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_PHYMOD_SIZE_SHIFT 8 1345*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_PHYMOD_SIZE_MASK 0x000FFF00 1346*14b24e2bSVaishali Kulkarni /* configure vf MSIX params BB */ 1347*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0 1348*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF 1349*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8 1350*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00 1351*14b24e2bSVaishali Kulkarni /* configure vf MSIX for PF params AH*/ 1352*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_SHIFT 0 1353*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_MASK 0x000000FF 1354*14b24e2bSVaishali Kulkarni 1355*14b24e2bSVaishali Kulkarni /* OneView configuration parametres */ 1356*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0 1357*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F 1358*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0 1359*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_CURR_CFG_OS 1 1360*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2 1361*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3 1362*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_CURR_CFG_VC_CLP 4 1363*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_CURR_CFG_CNU 5 1364*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_CURR_CFG_DCI 6 1365*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_CURR_CFG_HII 7 1366*14b24e2bSVaishali Kulkarni 1367*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_SHIFT 0 1368*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK 0x000000FF 1369*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE (1 << 0) 1370*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_IP_ACQUIRED (1 << 1) 1371*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS (1 << 1) 1372*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_TRARGET_FOUND (1 << 2) 1373*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_CHAP_SUCCESS (1 << 3) 1374*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_LUN_FOUND (1 << 3) 1375*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_LOGGED_INTO_TGT (1 << 4) 1376*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_IMG_DOWNLOADED (1 << 5) 1377*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF (1 << 6) 1378*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED 0 1379*14b24e2bSVaishali Kulkarni 1380*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_PCI_BUS_NUM_SHIFT 0 1381*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK 0x000000FF 1382*14b24e2bSVaishali Kulkarni 1383*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0 1384*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF 1385*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000 1386*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000 1387*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00 1388*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF 1389*14b24e2bSVaishali Kulkarni 1390*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0 1391*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF 1392*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1 1393*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2 /* Not Installed*/ 1394*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3 1395*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4 /* installed but disabled by user/admin/OS */ 1396*14b24e2bSVaishali Kulkarni #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5 /* installed and active */ 1397*14b24e2bSVaishali Kulkarni 1398*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0 1399*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF 1400*14b24e2bSVaishali Kulkarni 1401*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_WOL_MASK (DRV_MB_PARAM_WOL_DEFAULT | \ 1402*14b24e2bSVaishali Kulkarni DRV_MB_PARAM_WOL_DISABLED | \ 1403*14b24e2bSVaishali Kulkarni DRV_MB_PARAM_WOL_ENABLED) 1404*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_WOL_DEFAULT DRV_MB_PARAM_UNLOAD_WOL_MCP 1405*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_WOL_DISABLED DRV_MB_PARAM_UNLOAD_WOL_DISABLED 1406*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_WOL_ENABLED DRV_MB_PARAM_UNLOAD_WOL_ENABLED 1407*14b24e2bSVaishali Kulkarni 1408*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_ESWITCH_MODE_MASK (DRV_MB_PARAM_ESWITCH_MODE_NONE | \ 1409*14b24e2bSVaishali Kulkarni DRV_MB_PARAM_ESWITCH_MODE_VEB | \ 1410*14b24e2bSVaishali Kulkarni DRV_MB_PARAM_ESWITCH_MODE_VEPA) 1411*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0 1412*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1 1413*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2 1414*14b24e2bSVaishali Kulkarni 1415*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_FCOE_CVID_MASK 0xFFF 1416*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_FCOE_CVID_SHIFT 0 1417*14b24e2bSVaishali Kulkarni 1418*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0 1419*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1 1420*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2 1421*14b24e2bSVaishali Kulkarni 1422*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT 0 1423*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003 1424*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT 2 1425*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC 1426*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT 8 1427*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00 1428*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT 16 1429*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000 1430*14b24e2bSVaishali Kulkarni 1431*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_GPIO_NUMBER_SHIFT 0 1432*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_GPIO_NUMBER_MASK 0x0000FFFF 1433*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_GPIO_VALUE_SHIFT 16 1434*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_GPIO_VALUE_MASK 0xFFFF0000 1435*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_GPIO_DIRECTION_SHIFT 16 1436*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_GPIO_DIRECTION_MASK 0x00FF0000 1437*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_GPIO_CTRL_SHIFT 24 1438*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_GPIO_CTRL_MASK 0xFF000000 1439*14b24e2bSVaishali Kulkarni 1440*14b24e2bSVaishali Kulkarni /* Resource Allocation params - Driver version support*/ 1441*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 1442*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16 1443*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF 1444*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0 1445*14b24e2bSVaishali Kulkarni 1446*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0 1447*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_BIST_REGISTER_TEST 1 1448*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_BIST_CLOCK_TEST 2 1449*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3 1450*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4 1451*14b24e2bSVaishali Kulkarni 1452*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0 1453*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_BIST_RC_PASSED 1 1454*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_BIST_RC_FAILED 2 1455*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3 1456*14b24e2bSVaishali Kulkarni 1457*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0 1458*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF 1459*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8 1460*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00 1461*14b24e2bSVaishali Kulkarni 1462*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000FFFF 1463*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SHIFT 0 1464*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ 0x00000001 /* driver supports SmartLinQ parameter */ 1465*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002 /* driver supports EEE parameter */ 1466*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_MASK 0xFFFF0000 1467*14b24e2bSVaishali Kulkarni #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_SHIFT 16 1468*14b24e2bSVaishali Kulkarni 1469*14b24e2bSVaishali Kulkarni u32 fw_mb_header; 1470*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_MASK 0xffff0000 1471*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_UNSUPPORTED 0x00000000 1472*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000 1473*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1474*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1475*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000 1476*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 0x10210000 1477*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000 1478*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10230000 1479*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000 1480*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT 0x10310000 1481*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1482*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000 1483*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000 1484*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000 1485*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1486*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_INIT_PHY_DONE 0x21200000 1487*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS 0x21300000 1488*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_LINK_RESET_DONE 0x23000000 1489*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_SET_LLDP_DONE 0x24000000 1490*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000 1491*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_SET_DCBX_DONE 0x25000000 1492*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_UPDATE_CURR_CFG_DONE 0x26000000 1493*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_UPDATE_BUS_NUM_DONE 0x27000000 1494*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_UPDATE_BOOT_PROGRESS_DONE 0x28000000 1495*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_UPDATE_STORM_FW_VER_DONE 0x29000000 1496*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0x31000000 1497*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_DRV_MSG_CODE_BW_UPDATE_DONE 0x32000000 1498*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_DRV_MSG_CODE_MTU_SIZE_DONE 0x33000000 1499*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000 1500*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000 1501*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000 1502*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_RESOURCE_ALLOC_GEN_ERR 0x37000000 1503*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_UPDATE_WOL_DONE 0x38000000 1504*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_UPDATE_ESWITCH_MODE_DONE 0x39000000 1505*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_UPDATE_ERR 0x3a010000 1506*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_UPDATE_PARAM_ERR 0x3a020000 1507*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_UPDATE_NOT_ALLOWED 0x3a030000 1508*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE 0x3b000000 1509*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_UPDATE_FCOE_CVID_DONE 0x3c000000 1510*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_UPDATE_FCOE_FABRIC_NAME_DONE 0x3d000000 1511*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_UPDATE_BOOT_CFG_DONE 0x3e000000 1512*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_RESET_TO_DEFAULT_ACK 0x3f000000 1513*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_OV_GET_CURR_CFG_DONE 0x40000000 1514*14b24e2bSVaishali Kulkarni 1515*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000 1516*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1517*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000 1518*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_FLR_ACK 0x02000000 1519*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_FLR_NACK 0x02100000 1520*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_SET_DRIVER_DONE 0x02200000 1521*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_SET_VMAC_SUCCESS 0x02300000 1522*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_SET_VMAC_FAIL 0x02400000 1523*14b24e2bSVaishali Kulkarni 1524*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_OK 0x00010000 1525*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_INVALID_MODE 0x00020000 1526*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED 0x00030000 1527*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000 1528*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_INVALID_DIR_FOUND 0x00050000 1529*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_PAGE_NOT_FOUND 0x00060000 1530*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000 1531*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000 1532*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC 0x00090000 1533*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 0x000a0000 1534*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 0x000b0000 1535*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_FILE_NOT_FOUND 0x000c0000 1536*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_OPERATION_FAILED 0x000d0000 1537*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_FAILED_UNALIGNED 0x000e0000 1538*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_BAD_OFFSET 0x000f0000 1539*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_BAD_SIGNATURE 0x00100000 1540*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_FILE_READ_ONLY 0x00200000 1541*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_UNKNOWN_FILE 0x00300000 1542*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000 1543*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_MCP_RESET_REJECT 0x00600000 /* MFW reject "mcp reset" command if one of the drivers is up */ 1544*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_FAILED_CALC_HASH 0x00310000 1545*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_PUBLIC_KEY_MISSING 0x00320000 1546*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_NVM_INVALID_PUBLIC_KEY 0x00330000 1547*14b24e2bSVaishali Kulkarni 1548*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_PHY_OK 0x00110000 1549*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_PHY_ERROR 0x00120000 1550*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_SET_SECURE_MODE_ERROR 0x00130000 1551*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000 1552*14b24e2bSVaishali Kulkarni #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000 1553*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_OK 0x00160000 1554*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_LED_MODE_INVALID 0x00170000 1555*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_PHY_DIAG_OK 0x00160000 1556*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_PHY_DIAG_ERROR 0x00170000 1557*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_INIT_HW_FAILED_TO_ALLOCATE_PAGE 0x00040000 1558*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_INIT_HW_FAILED_BAD_STATE 0x00170000 1559*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_INIT_HW_FAILED_TO_SET_WINDOW 0x000d0000 1560*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_INIT_HW_FAILED_NO_IMAGE 0x000c0000 1561*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_INIT_HW_FAILED_VERSION_MISMATCH 0x00100000 1562*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000 1563*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000 1564*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000 1565*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE 0x000f0000 1566*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_GPIO_OK 0x00160000 1567*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_GPIO_DIRECTION_ERR 0x00170000 1568*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_GPIO_CTRL_ERR 0x00020000 1569*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_GPIO_INVALID 0x000f0000 1570*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_GPIO_INVALID_VALUE 0x00050000 1571*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_BIST_TEST_INVALID 0x000f0000 1572*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_EXTPHY_INVALID_IMAGE_HEADER 0x00700000 1573*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_EXTPHY_INVALID_PHY_TYPE 0x00710000 1574*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_EXTPHY_OPERATION_FAILED 0x00720000 1575*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_EXTPHY_NO_PHY_DETECTED 0x00730000 1576*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_RECOVERY_MODE 0x00740000 1577*14b24e2bSVaishali Kulkarni 1578*14b24e2bSVaishali Kulkarni /* mdump related response codes */ 1579*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_MDUMP_NO_IMAGE_FOUND 0x00010000 1580*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_MDUMP_ALLOC_FAILED 0x00020000 1581*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_MDUMP_INVALID_CMD 0x00030000 1582*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_MDUMP_IN_PROGRESS 0x00040000 1583*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_MDUMP_WRITE_FAILED 0x00050000 1584*14b24e2bSVaishali Kulkarni 1585*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_OS_WOL_SUPPORTED 0x00800000 1586*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED 0x00810000 1587*14b24e2bSVaishali Kulkarni 1588*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_WOL_READ_WRITE_OK 0x00820000 1589*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_WOL_READ_WRITE_INVALID_VAL 0x00830000 1590*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_WOL_READ_WRITE_INVALID_ADDR 0x00840000 1591*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_WOL_READ_BUFFER_OK 0x00850000 1592*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_WOL_READ_BUFFER_INVALID_VAL 0x00860000 1593*14b24e2bSVaishali Kulkarni 1594*14b24e2bSVaishali Kulkarni 1595*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000 1596*14b24e2bSVaishali Kulkarni #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_BAD_ASIC 0x00880000 1597*14b24e2bSVaishali Kulkarni 1598*14b24e2bSVaishali Kulkarni #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1599*14b24e2bSVaishali Kulkarni 1600*14b24e2bSVaishali Kulkarni 1601*14b24e2bSVaishali Kulkarni u32 fw_mb_param; 1602*14b24e2bSVaishali Kulkarni /* Resource Allocation params - MFW version support */ 1603*14b24e2bSVaishali Kulkarni #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 1604*14b24e2bSVaishali Kulkarni #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16 1605*14b24e2bSVaishali Kulkarni #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF 1606*14b24e2bSVaishali Kulkarni #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0 1607*14b24e2bSVaishali Kulkarni 1608*14b24e2bSVaishali Kulkarni /* get pf rdma protocol command response */ 1609*14b24e2bSVaishali Kulkarni #define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0 1610*14b24e2bSVaishali Kulkarni #define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1 1611*14b24e2bSVaishali Kulkarni #define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2 1612*14b24e2bSVaishali Kulkarni #define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3 1613*14b24e2bSVaishali Kulkarni 1614*14b24e2bSVaishali Kulkarni /* get MFW feature support response */ 1615*14b24e2bSVaishali Kulkarni #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ 0x00000001 /* MFW supports SmartLinQ */ 1616*14b24e2bSVaishali Kulkarni #define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002 /* MFW supports EEE */ 1617*14b24e2bSVaishali Kulkarni 1618*14b24e2bSVaishali Kulkarni #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1<<0) 1619*14b24e2bSVaishali Kulkarni 1620*14b24e2bSVaishali Kulkarni u32 drv_pulse_mb; 1621*14b24e2bSVaishali Kulkarni #define DRV_PULSE_SEQ_MASK 0x00007fff 1622*14b24e2bSVaishali Kulkarni #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1623*14b24e2bSVaishali Kulkarni /* 1624*14b24e2bSVaishali Kulkarni * The system time is in the format of 1625*14b24e2bSVaishali Kulkarni * (year-2001)*12*32 + month*32 + day. 1626*14b24e2bSVaishali Kulkarni */ 1627*14b24e2bSVaishali Kulkarni #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1628*14b24e2bSVaishali Kulkarni /* 1629*14b24e2bSVaishali Kulkarni * Indicate to the firmware not to go into the 1630*14b24e2bSVaishali Kulkarni * OS-absent when it is not getting driver pulse. 1631*14b24e2bSVaishali Kulkarni * This is used for debugging as well for PXE(MBA). 1632*14b24e2bSVaishali Kulkarni */ 1633*14b24e2bSVaishali Kulkarni 1634*14b24e2bSVaishali Kulkarni u32 mcp_pulse_mb; 1635*14b24e2bSVaishali Kulkarni #define MCP_PULSE_SEQ_MASK 0x00007fff 1636*14b24e2bSVaishali Kulkarni #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1637*14b24e2bSVaishali Kulkarni /* Indicates to the driver not to assert due to lack 1638*14b24e2bSVaishali Kulkarni * of MCP response */ 1639*14b24e2bSVaishali Kulkarni #define MCP_EVENT_MASK 0xffff0000 1640*14b24e2bSVaishali Kulkarni #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1641*14b24e2bSVaishali Kulkarni 1642*14b24e2bSVaishali Kulkarni /* The union data is used by the driver to pass parameters to the scratchpad. */ 1643*14b24e2bSVaishali Kulkarni union drv_union_data union_data; 1644*14b24e2bSVaishali Kulkarni 1645*14b24e2bSVaishali Kulkarni }; 1646*14b24e2bSVaishali Kulkarni 1647*14b24e2bSVaishali Kulkarni /* MFW - DRV MB */ 1648*14b24e2bSVaishali Kulkarni /********************************************************************** 1649*14b24e2bSVaishali Kulkarni * Description 1650*14b24e2bSVaishali Kulkarni * Incremental Aggregative 1651*14b24e2bSVaishali Kulkarni * 8-bit MFW counter per message 1652*14b24e2bSVaishali Kulkarni * 8-bit ack-counter per message 1653*14b24e2bSVaishali Kulkarni * Capabilities 1654*14b24e2bSVaishali Kulkarni * Provides up to 256 aggregative message per type 1655*14b24e2bSVaishali Kulkarni * Provides 4 message types in dword 1656*14b24e2bSVaishali Kulkarni * Message type pointers to byte offset 1657*14b24e2bSVaishali Kulkarni * Backward Compatibility by using sizeof for the counters. 1658*14b24e2bSVaishali Kulkarni * No lock requires for 32bit messages 1659*14b24e2bSVaishali Kulkarni * Limitations: 1660*14b24e2bSVaishali Kulkarni * In case of messages greater than 32bit, a dedicated mechanism(e.g lock) 1661*14b24e2bSVaishali Kulkarni * is required to prevent data corruption. 1662*14b24e2bSVaishali Kulkarni **********************************************************************/ 1663*14b24e2bSVaishali Kulkarni enum MFW_DRV_MSG_TYPE { 1664*14b24e2bSVaishali Kulkarni MFW_DRV_MSG_LINK_CHANGE, 1665*14b24e2bSVaishali Kulkarni MFW_DRV_MSG_FLR_FW_ACK_FAILED, 1666*14b24e2bSVaishali Kulkarni MFW_DRV_MSG_VF_DISABLED, 1667*14b24e2bSVaishali Kulkarni MFW_DRV_MSG_LLDP_DATA_UPDATED, 1668*14b24e2bSVaishali Kulkarni MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED, 1669*14b24e2bSVaishali Kulkarni MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED, 1670*14b24e2bSVaishali Kulkarni MFW_DRV_MSG_ERROR_RECOVERY, 1671*14b24e2bSVaishali Kulkarni MFW_DRV_MSG_BW_UPDATE, 1672*14b24e2bSVaishali Kulkarni MFW_DRV_MSG_S_TAG_UPDATE, 1673*14b24e2bSVaishali Kulkarni MFW_DRV_MSG_GET_LAN_STATS, 1674*14b24e2bSVaishali Kulkarni MFW_DRV_MSG_GET_FCOE_STATS, 1675*14b24e2bSVaishali Kulkarni MFW_DRV_MSG_GET_ISCSI_STATS, 1676*14b24e2bSVaishali Kulkarni MFW_DRV_MSG_GET_RDMA_STATS, 1677*14b24e2bSVaishali Kulkarni MFW_DRV_MSG_FAILURE_DETECTED, 1678*14b24e2bSVaishali Kulkarni MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE, 1679*14b24e2bSVaishali Kulkarni MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED, 1680*14b24e2bSVaishali Kulkarni MFW_DRV_MSG_EEE_NEGOTIATION_COMPLETE, 1681*14b24e2bSVaishali Kulkarni MFW_DRV_MSG_GET_TLV_REQ, 1682*14b24e2bSVaishali Kulkarni MFW_DRV_MSG_MAX 1683*14b24e2bSVaishali Kulkarni }; 1684*14b24e2bSVaishali Kulkarni 1685*14b24e2bSVaishali Kulkarni #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1) 1686*14b24e2bSVaishali Kulkarni #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2) 1687*14b24e2bSVaishali Kulkarni #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3) 1688*14b24e2bSVaishali Kulkarni #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id)) 1689*14b24e2bSVaishali Kulkarni 1690*14b24e2bSVaishali Kulkarni #ifdef BIG_ENDIAN /* Like MFW */ 1691*14b24e2bSVaishali Kulkarni #define DRV_ACK_MSG(msg_p, msg_id) (u8)((u8*)msg_p)[msg_id]++; 1692*14b24e2bSVaishali Kulkarni #else 1693*14b24e2bSVaishali Kulkarni #define DRV_ACK_MSG(msg_p, msg_id) (u8)((u8*)msg_p)[((msg_id & ~3) | ((~msg_id) & 3))]++; 1694*14b24e2bSVaishali Kulkarni #endif 1695*14b24e2bSVaishali Kulkarni 1696*14b24e2bSVaishali Kulkarni #define MFW_DRV_UPDATE(shmem_func, msg_id) (u8)((u8*)(MFW_MB_P(shmem_func)->msg))[msg_id]++; 1697*14b24e2bSVaishali Kulkarni 1698*14b24e2bSVaishali Kulkarni struct public_mfw_mb { 1699*14b24e2bSVaishali Kulkarni u32 sup_msgs; /* Assigend with MFW_DRV_MSG_MAX */ 1700*14b24e2bSVaishali Kulkarni u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; /* Incremented by the MFW */ 1701*14b24e2bSVaishali Kulkarni u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; /* Incremented by the driver */ 1702*14b24e2bSVaishali Kulkarni }; 1703*14b24e2bSVaishali Kulkarni 1704*14b24e2bSVaishali Kulkarni /**************************************/ 1705*14b24e2bSVaishali Kulkarni /* */ 1706*14b24e2bSVaishali Kulkarni /* P U B L I C D A T A */ 1707*14b24e2bSVaishali Kulkarni /* */ 1708*14b24e2bSVaishali Kulkarni /**************************************/ 1709*14b24e2bSVaishali Kulkarni enum public_sections { 1710*14b24e2bSVaishali Kulkarni PUBLIC_DRV_MB, /* Points to the first drv_mb of path0 */ 1711*14b24e2bSVaishali Kulkarni PUBLIC_MFW_MB, /* Points to the first mfw_mb of path0 */ 1712*14b24e2bSVaishali Kulkarni PUBLIC_GLOBAL, 1713*14b24e2bSVaishali Kulkarni PUBLIC_PATH, 1714*14b24e2bSVaishali Kulkarni PUBLIC_PORT, 1715*14b24e2bSVaishali Kulkarni PUBLIC_FUNC, 1716*14b24e2bSVaishali Kulkarni PUBLIC_MAX_SECTIONS 1717*14b24e2bSVaishali Kulkarni }; 1718*14b24e2bSVaishali Kulkarni 1719*14b24e2bSVaishali Kulkarni struct drv_ver_info_stc { 1720*14b24e2bSVaishali Kulkarni u32 ver; 1721*14b24e2bSVaishali Kulkarni u8 name[32]; 1722*14b24e2bSVaishali Kulkarni }; 1723*14b24e2bSVaishali Kulkarni 1724*14b24e2bSVaishali Kulkarni /* Runtime data needs about 1/2K. We use 2K to be on the safe side. 1725*14b24e2bSVaishali Kulkarni * Please make sure data does not exceed this size. 1726*14b24e2bSVaishali Kulkarni */ 1727*14b24e2bSVaishali Kulkarni #define NUM_RUNTIME_DWORDS 16 1728*14b24e2bSVaishali Kulkarni struct drv_init_hw_stc { 1729*14b24e2bSVaishali Kulkarni u32 init_hw_bitmask[NUM_RUNTIME_DWORDS]; 1730*14b24e2bSVaishali Kulkarni u32 init_hw_data[NUM_RUNTIME_DWORDS * 32]; 1731*14b24e2bSVaishali Kulkarni }; 1732*14b24e2bSVaishali Kulkarni 1733*14b24e2bSVaishali Kulkarni struct mcp_public_data { 1734*14b24e2bSVaishali Kulkarni /* The sections fields is an array */ 1735*14b24e2bSVaishali Kulkarni u32 num_sections; 1736*14b24e2bSVaishali Kulkarni offsize_t sections[PUBLIC_MAX_SECTIONS]; 1737*14b24e2bSVaishali Kulkarni struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX]; 1738*14b24e2bSVaishali Kulkarni struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX]; 1739*14b24e2bSVaishali Kulkarni struct public_global global; 1740*14b24e2bSVaishali Kulkarni struct public_path path[MCP_GLOB_PATH_MAX]; 1741*14b24e2bSVaishali Kulkarni struct public_port port[MCP_GLOB_PORT_MAX]; 1742*14b24e2bSVaishali Kulkarni struct public_func func[MCP_GLOB_FUNC_MAX]; 1743*14b24e2bSVaishali Kulkarni }; 1744*14b24e2bSVaishali Kulkarni 1745*14b24e2bSVaishali Kulkarni #define I2C_TRANSCEIVER_ADDR 0xa0 1746*14b24e2bSVaishali Kulkarni #define MAX_I2C_TRANSACTION_SIZE 16 1747*14b24e2bSVaishali Kulkarni #define MAX_I2C_TRANSCEIVER_PAGE_SIZE 256 1748*14b24e2bSVaishali Kulkarni 1749*14b24e2bSVaishali Kulkarni /* OCBB definitions */ 1750*14b24e2bSVaishali Kulkarni enum tlvs { 1751*14b24e2bSVaishali Kulkarni /* Category 1: Device Properties */ 1752*14b24e2bSVaishali Kulkarni DRV_TLV_CLP_STR, 1753*14b24e2bSVaishali Kulkarni DRV_TLV_CLP_STR_CTD, 1754*14b24e2bSVaishali Kulkarni /* Category 6: Device Configuration */ 1755*14b24e2bSVaishali Kulkarni DRV_TLV_SCSI_TO, 1756*14b24e2bSVaishali Kulkarni DRV_TLV_R_T_TOV, 1757*14b24e2bSVaishali Kulkarni DRV_TLV_R_A_TOV, 1758*14b24e2bSVaishali Kulkarni DRV_TLV_E_D_TOV, 1759*14b24e2bSVaishali Kulkarni DRV_TLV_CR_TOV, 1760*14b24e2bSVaishali Kulkarni DRV_TLV_BOOT_TYPE, 1761*14b24e2bSVaishali Kulkarni /* Category 8: Port Configuration */ 1762*14b24e2bSVaishali Kulkarni DRV_TLV_NPIV_ENABLED, 1763*14b24e2bSVaishali Kulkarni /* Category 10: Function Configuration */ 1764*14b24e2bSVaishali Kulkarni DRV_TLV_FEATURE_FLAGS, 1765*14b24e2bSVaishali Kulkarni DRV_TLV_LOCAL_ADMIN_ADDR, 1766*14b24e2bSVaishali Kulkarni DRV_TLV_ADDITIONAL_MAC_ADDR_1, 1767*14b24e2bSVaishali Kulkarni DRV_TLV_ADDITIONAL_MAC_ADDR_2, 1768*14b24e2bSVaishali Kulkarni DRV_TLV_LSO_MAX_OFFLOAD_SIZE, 1769*14b24e2bSVaishali Kulkarni DRV_TLV_LSO_MIN_SEGMENT_COUNT, 1770*14b24e2bSVaishali Kulkarni DRV_TLV_PROMISCUOUS_MODE, 1771*14b24e2bSVaishali Kulkarni DRV_TLV_TX_DESCRIPTORS_QUEUE_SIZE, 1772*14b24e2bSVaishali Kulkarni DRV_TLV_RX_DESCRIPTORS_QUEUE_SIZE, 1773*14b24e2bSVaishali Kulkarni DRV_TLV_NUM_OF_NET_QUEUE_VMQ_CFG, 1774*14b24e2bSVaishali Kulkarni DRV_TLV_FLEX_NIC_OUTER_VLAN_ID, 1775*14b24e2bSVaishali Kulkarni DRV_TLV_OS_DRIVER_STATES, 1776*14b24e2bSVaishali Kulkarni DRV_TLV_PXE_BOOT_PROGRESS, 1777*14b24e2bSVaishali Kulkarni /* Category 12: FC/FCoE Configuration */ 1778*14b24e2bSVaishali Kulkarni DRV_TLV_NPIV_STATE, 1779*14b24e2bSVaishali Kulkarni DRV_TLV_NUM_OF_NPIV_IDS, 1780*14b24e2bSVaishali Kulkarni DRV_TLV_SWITCH_NAME, 1781*14b24e2bSVaishali Kulkarni DRV_TLV_SWITCH_PORT_NUM, 1782*14b24e2bSVaishali Kulkarni DRV_TLV_SWITCH_PORT_ID, 1783*14b24e2bSVaishali Kulkarni DRV_TLV_VENDOR_NAME, 1784*14b24e2bSVaishali Kulkarni DRV_TLV_SWITCH_MODEL, 1785*14b24e2bSVaishali Kulkarni DRV_TLV_SWITCH_FW_VER, 1786*14b24e2bSVaishali Kulkarni DRV_TLV_QOS_PRIORITY_PER_802_1P, 1787*14b24e2bSVaishali Kulkarni DRV_TLV_PORT_ALIAS, 1788*14b24e2bSVaishali Kulkarni DRV_TLV_PORT_STATE, 1789*14b24e2bSVaishali Kulkarni DRV_TLV_FIP_TX_DESCRIPTORS_QUEUE_SIZE, 1790*14b24e2bSVaishali Kulkarni DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_SIZE, 1791*14b24e2bSVaishali Kulkarni DRV_TLV_LINK_FAILURE_COUNT, 1792*14b24e2bSVaishali Kulkarni DRV_TLV_FCOE_BOOT_PROGRESS, 1793*14b24e2bSVaishali Kulkarni /* Category 13: iSCSI Configuration */ 1794*14b24e2bSVaishali Kulkarni DRV_TLV_TARGET_LLMNR_ENABLED, 1795*14b24e2bSVaishali Kulkarni DRV_TLV_HEADER_DIGEST_FLAG_ENABLED, 1796*14b24e2bSVaishali Kulkarni DRV_TLV_DATA_DIGEST_FLAG_ENABLED, 1797*14b24e2bSVaishali Kulkarni DRV_TLV_AUTHENTICATION_METHOD, 1798*14b24e2bSVaishali Kulkarni DRV_TLV_ISCSI_BOOT_TARGET_PORTAL, 1799*14b24e2bSVaishali Kulkarni DRV_TLV_MAX_FRAME_SIZE, 1800*14b24e2bSVaishali Kulkarni DRV_TLV_PDU_TX_DESCRIPTORS_QUEUE_SIZE, 1801*14b24e2bSVaishali Kulkarni DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_SIZE, 1802*14b24e2bSVaishali Kulkarni DRV_TLV_ISCSI_BOOT_PROGRESS, 1803*14b24e2bSVaishali Kulkarni /* Category 20: Device Data */ 1804*14b24e2bSVaishali Kulkarni DRV_TLV_PCIE_BUS_RX_UTILIZATION, 1805*14b24e2bSVaishali Kulkarni DRV_TLV_PCIE_BUS_TX_UTILIZATION, 1806*14b24e2bSVaishali Kulkarni DRV_TLV_DEVICE_CPU_CORES_UTILIZATION, 1807*14b24e2bSVaishali Kulkarni DRV_TLV_LAST_VALID_DCC_TLV_RECEIVED, 1808*14b24e2bSVaishali Kulkarni DRV_TLV_NCSI_RX_BYTES_RECEIVED, 1809*14b24e2bSVaishali Kulkarni DRV_TLV_NCSI_TX_BYTES_SENT, 1810*14b24e2bSVaishali Kulkarni /* Category 22: Base Port Data */ 1811*14b24e2bSVaishali Kulkarni DRV_TLV_RX_DISCARDS, 1812*14b24e2bSVaishali Kulkarni DRV_TLV_RX_ERRORS, 1813*14b24e2bSVaishali Kulkarni DRV_TLV_TX_ERRORS, 1814*14b24e2bSVaishali Kulkarni DRV_TLV_TX_DISCARDS, 1815*14b24e2bSVaishali Kulkarni DRV_TLV_RX_FRAMES_RECEIVED, 1816*14b24e2bSVaishali Kulkarni DRV_TLV_TX_FRAMES_SENT, 1817*14b24e2bSVaishali Kulkarni /* Category 23: FC/FCoE Port Data */ 1818*14b24e2bSVaishali Kulkarni DRV_TLV_RX_BROADCAST_PACKETS, 1819*14b24e2bSVaishali Kulkarni DRV_TLV_TX_BROADCAST_PACKETS, 1820*14b24e2bSVaishali Kulkarni /* Category 28: Base Function Data */ 1821*14b24e2bSVaishali Kulkarni DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV4, 1822*14b24e2bSVaishali Kulkarni DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV6, 1823*14b24e2bSVaishali Kulkarni DRV_TLV_TX_DESCRIPTOR_QUEUE_AVG_DEPTH, 1824*14b24e2bSVaishali Kulkarni DRV_TLV_RX_DESCRIPTORS_QUEUE_AVG_DEPTH, 1825*14b24e2bSVaishali Kulkarni DRV_TLV_PF_RX_FRAMES_RECEIVED, 1826*14b24e2bSVaishali Kulkarni DRV_TLV_RX_BYTES_RECEIVED, 1827*14b24e2bSVaishali Kulkarni DRV_TLV_PF_TX_FRAMES_SENT, 1828*14b24e2bSVaishali Kulkarni DRV_TLV_TX_BYTES_SENT, 1829*14b24e2bSVaishali Kulkarni DRV_TLV_IOV_OFFLOAD, 1830*14b24e2bSVaishali Kulkarni DRV_TLV_PCI_ERRORS_CAP_ID, 1831*14b24e2bSVaishali Kulkarni DRV_TLV_UNCORRECTABLE_ERROR_STATUS, 1832*14b24e2bSVaishali Kulkarni DRV_TLV_UNCORRECTABLE_ERROR_MASK, 1833*14b24e2bSVaishali Kulkarni DRV_TLV_CORRECTABLE_ERROR_STATUS, 1834*14b24e2bSVaishali Kulkarni DRV_TLV_CORRECTABLE_ERROR_MASK, 1835*14b24e2bSVaishali Kulkarni DRV_TLV_PCI_ERRORS_AECC_REGISTER, 1836*14b24e2bSVaishali Kulkarni DRV_TLV_TX_QUEUES_EMPTY, 1837*14b24e2bSVaishali Kulkarni DRV_TLV_RX_QUEUES_EMPTY, 1838*14b24e2bSVaishali Kulkarni DRV_TLV_TX_QUEUES_FULL, 1839*14b24e2bSVaishali Kulkarni DRV_TLV_RX_QUEUES_FULL, 1840*14b24e2bSVaishali Kulkarni /* Category 29: FC/FCoE Function Data */ 1841*14b24e2bSVaishali Kulkarni DRV_TLV_FCOE_TX_DESCRIPTOR_QUEUE_AVG_DEPTH, 1842*14b24e2bSVaishali Kulkarni DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_AVG_DEPTH, 1843*14b24e2bSVaishali Kulkarni DRV_TLV_FCOE_RX_FRAMES_RECEIVED, 1844*14b24e2bSVaishali Kulkarni DRV_TLV_FCOE_RX_BYTES_RECEIVED, 1845*14b24e2bSVaishali Kulkarni DRV_TLV_FCOE_TX_FRAMES_SENT, 1846*14b24e2bSVaishali Kulkarni DRV_TLV_FCOE_TX_BYTES_SENT, 1847*14b24e2bSVaishali Kulkarni DRV_TLV_CRC_ERROR_COUNT, 1848*14b24e2bSVaishali Kulkarni DRV_TLV_CRC_ERROR_1_RECEIVED_SOURCE_FC_ID, 1849*14b24e2bSVaishali Kulkarni DRV_TLV_CRC_ERROR_1_TIMESTAMP, 1850*14b24e2bSVaishali Kulkarni DRV_TLV_CRC_ERROR_2_RECEIVED_SOURCE_FC_ID, 1851*14b24e2bSVaishali Kulkarni DRV_TLV_CRC_ERROR_2_TIMESTAMP, 1852*14b24e2bSVaishali Kulkarni DRV_TLV_CRC_ERROR_3_RECEIVED_SOURCE_FC_ID, 1853*14b24e2bSVaishali Kulkarni DRV_TLV_CRC_ERROR_3_TIMESTAMP, 1854*14b24e2bSVaishali Kulkarni DRV_TLV_CRC_ERROR_4_RECEIVED_SOURCE_FC_ID, 1855*14b24e2bSVaishali Kulkarni DRV_TLV_CRC_ERROR_4_TIMESTAMP, 1856*14b24e2bSVaishali Kulkarni DRV_TLV_CRC_ERROR_5_RECEIVED_SOURCE_FC_ID, 1857*14b24e2bSVaishali Kulkarni DRV_TLV_CRC_ERROR_5_TIMESTAMP, 1858*14b24e2bSVaishali Kulkarni DRV_TLV_LOSS_OF_SYNC_ERROR_COUNT, 1859*14b24e2bSVaishali Kulkarni DRV_TLV_LOSS_OF_SIGNAL_ERRORS, 1860*14b24e2bSVaishali Kulkarni DRV_TLV_PRIMITIVE_SEQUENCE_PROTOCOL_ERROR_COUNT, 1861*14b24e2bSVaishali Kulkarni DRV_TLV_DISPARITY_ERROR_COUNT, 1862*14b24e2bSVaishali Kulkarni DRV_TLV_CODE_VIOLATION_ERROR_COUNT, 1863*14b24e2bSVaishali Kulkarni DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_1, 1864*14b24e2bSVaishali Kulkarni DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_2, 1865*14b24e2bSVaishali Kulkarni DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_3, 1866*14b24e2bSVaishali Kulkarni DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_4, 1867*14b24e2bSVaishali Kulkarni DRV_TLV_LAST_FLOGI_TIMESTAMP, 1868*14b24e2bSVaishali Kulkarni DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_1, 1869*14b24e2bSVaishali Kulkarni DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_2, 1870*14b24e2bSVaishali Kulkarni DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_3, 1871*14b24e2bSVaishali Kulkarni DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_4, 1872*14b24e2bSVaishali Kulkarni DRV_TLV_LAST_FLOGI_ACC_TIMESTAMP, 1873*14b24e2bSVaishali Kulkarni DRV_TLV_LAST_FLOGI_RJT, 1874*14b24e2bSVaishali Kulkarni DRV_TLV_LAST_FLOGI_RJT_TIMESTAMP, 1875*14b24e2bSVaishali Kulkarni DRV_TLV_FDISCS_SENT_COUNT, 1876*14b24e2bSVaishali Kulkarni DRV_TLV_FDISC_ACCS_RECEIVED, 1877*14b24e2bSVaishali Kulkarni DRV_TLV_FDISC_RJTS_RECEIVED, 1878*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_SENT_COUNT, 1879*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_ACCS_RECEIVED, 1880*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_RJTS_RECEIVED, 1881*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_1_SENT_DESTINATION_FC_ID, 1882*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_1_TIMESTAMP, 1883*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_2_SENT_DESTINATION_FC_ID, 1884*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_2_TIMESTAMP, 1885*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_3_SENT_DESTINATION_FC_ID, 1886*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_3_TIMESTAMP, 1887*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_4_SENT_DESTINATION_FC_ID, 1888*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_4_TIMESTAMP, 1889*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_5_SENT_DESTINATION_FC_ID, 1890*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_5_TIMESTAMP, 1891*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_1_ACC_RECEIVED_SOURCE_FC_ID, 1892*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_1_ACC_TIMESTAMP, 1893*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_2_ACC_RECEIVED_SOURCE_FC_ID, 1894*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_2_ACC_TIMESTAMP, 1895*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_3_ACC_RECEIVED_SOURCE_FC_ID, 1896*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_3_ACC_TIMESTAMP, 1897*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_4_ACC_RECEIVED_SOURCE_FC_ID, 1898*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_4_ACC_TIMESTAMP, 1899*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_5_ACC_RECEIVED_SOURCE_FC_ID, 1900*14b24e2bSVaishali Kulkarni DRV_TLV_PLOGI_5_ACC_TIMESTAMP, 1901*14b24e2bSVaishali Kulkarni DRV_TLV_LOGOS_ISSUED, 1902*14b24e2bSVaishali Kulkarni DRV_TLV_LOGO_ACCS_RECEIVED, 1903*14b24e2bSVaishali Kulkarni DRV_TLV_LOGO_RJTS_RECEIVED, 1904*14b24e2bSVaishali Kulkarni DRV_TLV_LOGO_1_RECEIVED_SOURCE_FC_ID, 1905*14b24e2bSVaishali Kulkarni DRV_TLV_LOGO_1_TIMESTAMP, 1906*14b24e2bSVaishali Kulkarni DRV_TLV_LOGO_2_RECEIVED_SOURCE_FC_ID, 1907*14b24e2bSVaishali Kulkarni DRV_TLV_LOGO_2_TIMESTAMP, 1908*14b24e2bSVaishali Kulkarni DRV_TLV_LOGO_3_RECEIVED_SOURCE_FC_ID, 1909*14b24e2bSVaishali Kulkarni DRV_TLV_LOGO_3_TIMESTAMP, 1910*14b24e2bSVaishali Kulkarni DRV_TLV_LOGO_4_RECEIVED_SOURCE_FC_ID, 1911*14b24e2bSVaishali Kulkarni DRV_TLV_LOGO_4_TIMESTAMP, 1912*14b24e2bSVaishali Kulkarni DRV_TLV_LOGO_5_RECEIVED_SOURCE_FC_ID, 1913*14b24e2bSVaishali Kulkarni DRV_TLV_LOGO_5_TIMESTAMP, 1914*14b24e2bSVaishali Kulkarni DRV_TLV_LOGOS_RECEIVED, 1915*14b24e2bSVaishali Kulkarni DRV_TLV_ACCS_ISSUED, 1916*14b24e2bSVaishali Kulkarni DRV_TLV_PRLIS_ISSUED, 1917*14b24e2bSVaishali Kulkarni DRV_TLV_ACCS_RECEIVED, 1918*14b24e2bSVaishali Kulkarni DRV_TLV_ABTS_SENT_COUNT, 1919*14b24e2bSVaishali Kulkarni DRV_TLV_ABTS_ACCS_RECEIVED, 1920*14b24e2bSVaishali Kulkarni DRV_TLV_ABTS_RJTS_RECEIVED, 1921*14b24e2bSVaishali Kulkarni DRV_TLV_ABTS_1_SENT_DESTINATION_FC_ID, 1922*14b24e2bSVaishali Kulkarni DRV_TLV_ABTS_1_TIMESTAMP, 1923*14b24e2bSVaishali Kulkarni DRV_TLV_ABTS_2_SENT_DESTINATION_FC_ID, 1924*14b24e2bSVaishali Kulkarni DRV_TLV_ABTS_2_TIMESTAMP, 1925*14b24e2bSVaishali Kulkarni DRV_TLV_ABTS_3_SENT_DESTINATION_FC_ID, 1926*14b24e2bSVaishali Kulkarni DRV_TLV_ABTS_3_TIMESTAMP, 1927*14b24e2bSVaishali Kulkarni DRV_TLV_ABTS_4_SENT_DESTINATION_FC_ID, 1928*14b24e2bSVaishali Kulkarni DRV_TLV_ABTS_4_TIMESTAMP, 1929*14b24e2bSVaishali Kulkarni DRV_TLV_ABTS_5_SENT_DESTINATION_FC_ID, 1930*14b24e2bSVaishali Kulkarni DRV_TLV_ABTS_5_TIMESTAMP, 1931*14b24e2bSVaishali Kulkarni DRV_TLV_RSCNS_RECEIVED, 1932*14b24e2bSVaishali Kulkarni DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_1, 1933*14b24e2bSVaishali Kulkarni DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_2, 1934*14b24e2bSVaishali Kulkarni DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_3, 1935*14b24e2bSVaishali Kulkarni DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_4, 1936*14b24e2bSVaishali Kulkarni DRV_TLV_LUN_RESETS_ISSUED, 1937*14b24e2bSVaishali Kulkarni DRV_TLV_ABORT_TASK_SETS_ISSUED, 1938*14b24e2bSVaishali Kulkarni DRV_TLV_TPRLOS_SENT, 1939*14b24e2bSVaishali Kulkarni DRV_TLV_NOS_SENT_COUNT, 1940*14b24e2bSVaishali Kulkarni DRV_TLV_NOS_RECEIVED_COUNT, 1941*14b24e2bSVaishali Kulkarni DRV_TLV_OLS_COUNT, 1942*14b24e2bSVaishali Kulkarni DRV_TLV_LR_COUNT, 1943*14b24e2bSVaishali Kulkarni DRV_TLV_LRR_COUNT, 1944*14b24e2bSVaishali Kulkarni DRV_TLV_LIP_SENT_COUNT, 1945*14b24e2bSVaishali Kulkarni DRV_TLV_LIP_RECEIVED_COUNT, 1946*14b24e2bSVaishali Kulkarni DRV_TLV_EOFA_COUNT, 1947*14b24e2bSVaishali Kulkarni DRV_TLV_EOFNI_COUNT, 1948*14b24e2bSVaishali Kulkarni DRV_TLV_SCSI_STATUS_CHECK_CONDITION_COUNT, 1949*14b24e2bSVaishali Kulkarni DRV_TLV_SCSI_STATUS_CONDITION_MET_COUNT, 1950*14b24e2bSVaishali Kulkarni DRV_TLV_SCSI_STATUS_BUSY_COUNT, 1951*14b24e2bSVaishali Kulkarni DRV_TLV_SCSI_STATUS_INTERMEDIATE_COUNT, 1952*14b24e2bSVaishali Kulkarni DRV_TLV_SCSI_STATUS_INTERMEDIATE_CONDITION_MET_COUNT, 1953*14b24e2bSVaishali Kulkarni DRV_TLV_SCSI_STATUS_RESERVATION_CONFLICT_COUNT, 1954*14b24e2bSVaishali Kulkarni DRV_TLV_SCSI_STATUS_TASK_SET_FULL_COUNT, 1955*14b24e2bSVaishali Kulkarni DRV_TLV_SCSI_STATUS_ACA_ACTIVE_COUNT, 1956*14b24e2bSVaishali Kulkarni DRV_TLV_SCSI_STATUS_TASK_ABORTED_COUNT, 1957*14b24e2bSVaishali Kulkarni DRV_TLV_SCSI_CHECK_CONDITION_1_RECEIVED_SK_ASC_ASCQ, 1958*14b24e2bSVaishali Kulkarni DRV_TLV_SCSI_CHECK_1_TIMESTAMP, 1959*14b24e2bSVaishali Kulkarni DRV_TLV_SCSI_CHECK_CONDITION_2_RECEIVED_SK_ASC_ASCQ, 1960*14b24e2bSVaishali Kulkarni DRV_TLV_SCSI_CHECK_2_TIMESTAMP, 1961*14b24e2bSVaishali Kulkarni DRV_TLV_SCSI_CHECK_CONDITION_3_RECEIVED_SK_ASC_ASCQ, 1962*14b24e2bSVaishali Kulkarni DRV_TLV_SCSI_CHECK_3_TIMESTAMP, 1963*14b24e2bSVaishali Kulkarni DRV_TLV_SCSI_CHECK_CONDITION_4_RECEIVED_SK_ASC_ASCQ, 1964*14b24e2bSVaishali Kulkarni DRV_TLV_SCSI_CHECK_4_TIMESTAMP, 1965*14b24e2bSVaishali Kulkarni DRV_TLV_SCSI_CHECK_CONDITION_5_RECEIVED_SK_ASC_ASCQ, 1966*14b24e2bSVaishali Kulkarni DRV_TLV_SCSI_CHECK_5_TIMESTAMP, 1967*14b24e2bSVaishali Kulkarni /* Category 30: iSCSI Function Data */ 1968*14b24e2bSVaishali Kulkarni DRV_TLV_PDU_TX_DESCRIPTOR_QUEUE_AVG_DEPTH, 1969*14b24e2bSVaishali Kulkarni DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_AVG_DEPTH, 1970*14b24e2bSVaishali Kulkarni DRV_TLV_ISCSI_PDU_RX_FRAMES_RECEIVED, 1971*14b24e2bSVaishali Kulkarni DRV_TLV_ISCSI_PDU_RX_BYTES_RECEIVED, 1972*14b24e2bSVaishali Kulkarni DRV_TLV_ISCSI_PDU_TX_FRAMES_SENT, 1973*14b24e2bSVaishali Kulkarni DRV_TLV_ISCSI_PDU_TX_BYTES_SENT 1974*14b24e2bSVaishali Kulkarni }; 1975*14b24e2bSVaishali Kulkarni 1976*14b24e2bSVaishali Kulkarni #endif /* MCP_PUBLIC_H */ 1977