/linux/Documentation/devicetree/bindings/interconnect/ |
H A D | qcom,sm8650-rpmh.yaml | 4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8650-rpmh.yaml# 7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8650 21 See also:: include/dt-bindings/interconnect/qcom,sm8650-rpmh.h 26 - qcom,sm8650-aggre1-noc 27 - qcom,sm8650-aggre2-noc 28 - qcom,sm8650-clk-virt 29 - qcom,sm8650-cnoc-main 30 - qcom,sm8650-config-noc 31 - qcom,sm8650-gem-noc 32 - qcom,sm8650-lpass-ag-noc [all …]
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/linux/Documentation/devicetree/bindings/display/msm/ |
H A D | qcom,sm8650-mdss.yaml | 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml# 7 title: Qualcomm SM8650 Display MDSS 13 SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like 20 const: qcom,sm8650-mdss 43 const: qcom,sm8650-dpu 50 const: qcom,sm8650-dp 58 - const: qcom,sm8650-dsi-ctrl 66 const: qcom,sm8650-dsi-phy-4nm 80 compatible = "qcom,sm8650-mdss"; 104 compatible = "qcom,sm8650-dpu"; [all …]
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H A D | qcom,sm8650-dpu.yaml | 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-dpu.yaml# 7 title: Qualcomm SM8650 Display DPU 17 - qcom,sm8650-dpu 61 compatible = "qcom,sm8650-dpu";
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/linux/Documentation/devicetree/bindings/pinctrl/ |
H A D | qcom,sm8650-lpass-lpi-pinctrl.yaml | 4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml# 7 title: Qualcomm SM8650 SoC LPASS LPI TLMM 15 (LPASS) Low Power Island (LPI) of Qualcomm SM8650 SoC. 19 const: qcom,sm8650-lpass-lpi-pinctrl 38 - $ref: "#/$defs/qcom-sm8650-lpass-state" 41 $ref: "#/$defs/qcom-sm8650-lpass-state" 45 qcom-sm8650-lpass-state: 90 compatible = "qcom,sm8650-lpass-lpi-pinctrl";
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H A D | qcom,sm8650-tlmm.yaml | 4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8650-tlmm.yaml# 7 title: Qualcomm Technologies, Inc. SM8650 TLMM block 13 Top Level Mode Multiplexer pin controller in Qualcomm SM8650 SoC. 20 const: qcom,sm8650-tlmm 38 - $ref: "#/$defs/qcom-sm8650-tlmm-state" 41 $ref: "#/$defs/qcom-sm8650-tlmm-state" 45 qcom-sm8650-tlmm-state: 113 compatible = "qcom,sm8650-tlmm";
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/linux/Documentation/devicetree/bindings/clock/ |
H A D | qcom,sm8650-gcc.yaml | 4 $id: http://devicetree.org/schemas/clock/qcom,sm8650-gcc.yaml# 7 title: Qualcomm Global Clock & Reset Controller on SM8650 14 domains on SM8650 16 See also:: include/dt-bindings/clock/qcom,sm8650-gcc.h 20 const: qcom,sm8650-gcc 49 compatible = "qcom,sm8650-gcc";
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H A D | qcom,sm8550-tcsr.yaml | 18 - include/dt-bindings/clock/qcom,sm8650-tcsr.h 25 - qcom,sm8650-tcsr
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H A D | qcom,sm8450-gpucc.yaml | 21 include/dt-bindings/reset/qcom,sm8650-gpucc.h 30 - qcom,sm8650-gpucc
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H A D | qcom,sm8550-dispcc.yaml | 19 - include/dt-bindings/clock/qcom,sm8650-dispcc.h 26 - qcom,sm8650-dispcc
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H A D | qcom,rpmhcc.yaml | 38 - qcom,sm8650-rpmh-clk
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/linux/arch/arm64/boot/dts/qcom/ |
H A D | sm8650-mtp.dts | 9 #include "sm8650.dtsi" 20 model = "Qualcomm Technologies, Inc. SM8650 MTP"; 21 compatible = "qcom,sm8650-mtp", "qcom,sm8650"; 32 compatible = "qcom,sm8650-pmic-glink", 70 compatible = "qcom,sm8650-sndcard", "qcom,sm8450-sndcard"; 71 model = "SM8650-MTP"; 700 firmware-name = "qcom/sm8650/adsp.mbn", 701 "qcom/sm8650/adsp_dtb.mbn"; 707 firmware-name = "qcom/sm8650/cdsp.mbn", 708 "qcom/sm8650/cdsp_dtb.mbn"; [all …]
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/linux/drivers/interconnect/qcom/ |
H A D | sm8650.c | 13 #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> 18 #include "sm8650.h" 1633 { .compatible = "qcom,sm8650-aggre1-noc", .data = &sm8650_aggre1_noc }, 1634 { .compatible = "qcom,sm8650-aggre2-noc", .data = &sm8650_aggre2_noc }, 1635 { .compatible = "qcom,sm8650-clk-virt", .data = &sm8650_clk_virt }, 1636 { .compatible = "qcom,sm8650-config-noc", .data = &sm8650_config_noc }, 1637 { .compatible = "qcom,sm8650-cnoc-main", .data = &sm8650_cnoc_main }, 1638 { .compatible = "qcom,sm8650-gem-noc", .data = &sm8650_gem_noc }, 1639 { .compatible = "qcom,sm8650-lpass-ag-noc", .data = &sm8650_lpass_ag_noc }, 1640 { .compatible = "qcom,sm8650-lpass-lpiaon-noc", .data = &sm8650_lpass_lpiaon_noc }, [all …]
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/linux/drivers/clk/qcom/ |
H A D | tcsrcc-sm8650.c | 14 #include <dt-bindings/clock/qcom,sm8650-tcsr.h> 151 { .compatible = "qcom,sm8650-tcsr" }, 164 .name = "tcsr_cc-sm8650", 181 MODULE_DESCRIPTION("QTI TCSRCC SM8650 Driver");
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H A D | gpucc-sm8650.c | 13 #include <dt-bindings/clock/qcom,sm8650-gpucc.h> 14 #include <dt-bindings/reset/qcom,sm8650-gpucc.h> 634 { .compatible = "qcom,sm8650-gpucc" }, 656 .name = "sm8650-gpucc", 662 MODULE_DESCRIPTION("QTI GPU_CC SM8650 Driver");
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/linux/drivers/pinctrl/qcom/ |
H A D | pinctrl-sm8650-lpass-lpi.c | 213 .compatible = "qcom,sm8650-lpass-lpi-pinctrl", 222 .name = "qcom-sm8650-lpass-lpi-pinctrl", 230 MODULE_DESCRIPTION("Qualcomm SM8650 LPI GPIO pin control driver");
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H A D | Kconfig | 137 tristate "Qualcomm Technologies Inc SM8650 LPASS LPI pin controller driver" 143 (Low Power Island) found on the Qualcomm Technologies Inc SM8650
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H A D | Makefile | 63 obj-$(CONFIG_PINCTRL_SM8650) += pinctrl-sm8650.o 64 obj-$(CONFIG_PINCTRL_SM8650_LPASS_LPI) += pinctrl-sm8650-lpass-lpi.o
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | qcom,sc8280xp-qmp-usb43dp-phy.yaml | 30 - qcom,sm8650-qmp-usb3-dp-phy 133 - qcom,sm8650-qmp-usb3-dp-phy
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/linux/Documentation/devicetree/bindings/firmware/ |
H A D | qcom,scm.yaml | 66 - qcom,scm-sm8650 197 - qcom,scm-sm8650
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/linux/Documentation/devicetree/bindings/cache/ |
H A D | qcom,llcc.yaml | 37 - qcom,sm8650-llcc 196 - qcom,sm8650-llcc
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/linux/sound/soc/qcom/ |
H A D | sc8280xp.c | 192 {.compatible = "qcom,sm8650-sndcard", "sm8650"},
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/linux/include/dt-bindings/clock/ |
H A D | qcom,sm8650-videocc.h | 11 /* SM8650 introduces below new clocks and resets compared to SM8450 */
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/linux/Documentation/devicetree/bindings/ufs/ |
H A D | qcom,ufs.yaml | 43 - qcom,sm8650-ufshc 157 - qcom,sm8650-ufshc
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/linux/Documentation/devicetree/bindings/crypto/ |
H A D | qcom,inline-crypto-engine.yaml | 21 - qcom,sm8650-inline-crypto-engine
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H A D | qcom,prng.yaml | 25 - qcom,sm8650-trng
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