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/linux/Documentation/devicetree/bindings/power/reset/
H A Dkeystone-reset.txt1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
18 reset control registers.
20 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
[all …]
/linux/drivers/scsi/snic/
H A Dsnic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
47 #define SNIC_TAG_DEV_RST BIT(29) /* Tag for device reset */
48 #define SNIC_TAG_IOCTL_DEV_RST BIT(28) /* Tag for User Device Reset */
49 #define SNIC_TAG_MASK (BIT(24) - 1) /* Mask for lookup */
50 #define SNIC_NO_TAG -1
96 (((struct snic_internal_io_state *)scsi_cmd_priv(Cmnd))->rqi)
98 (((struct snic_internal_io_state *)scsi_cmd_priv(Cmnd))->state)
100 (((struct snic_internal_io_state *)scsi_cmd_priv(Cmnd))->abts_status)
102 (((struct snic_internal_io_state *)scsi_cmd_priv(Cmnd))->lr_status)
104 (((struct snic_internal_io_state *)scsi_cmd_priv(Cmnd))->flags)
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/linux/Documentation/ABI/stable/
H A Dsysfs-driver-mlxreg-io1 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic_health
6 0 - health failed, 2 - health OK, 3 - ASIC in booting state.
10 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld1_version
11 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld2_version
20 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/fan_dir
25 forward direction - relevant bit is set 0;
26 reversed direction - relevant bit is set 1.
30 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld3_version
39 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/jtag_enable
48 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/select_iio
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/linux/drivers/ntb/hw/idt/
H A Dntb_hw_idt.h7 * Copyright (C) 2016-2018 T-Platforms JSC All Rights Reserved.
36 * IDT PCIe-switch NTB Linux driver
39 * Serge Semin <fancer.lancer@gmail.com>, <Sergey.Semin@t-platforms.ru>
55 * the supported IDT PCIe-switches
66 * IDT PCIe-switches device IDs
78 * NT-function Configuration Space registers
79 * NOTE 1) The IDT PCIe-switch internal data is little-endian
83 * with byte-enables corresponding to their native size or
86 * So to simplify the driver code, there is only DWORD-sized read/write
107 /* IDT Proprietary NT-port-specific registers */
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/linux/Documentation/devicetree/bindings/soc/socionext/
H A Dsocionext,uniphier-sdctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-sdctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
14 attached outside SDHC, and has some SD related functions such as
15 clock control, reset control, mode switch, and so on.
20 - enum:
21 - socionext,uniphier-pro5-sdctrl
22 - socionext,uniphier-pxs2-sdctrl
[all …]
/linux/Documentation/devicetree/bindings/power/
H A Dallwinner,sun20i-d1-ppu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/allwinner,sun20i-d1-ppu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Samuel Holland <samuel@sholland.org>
13 D1 and related SoCs contain a power domain controller for the CPUs, GPU, and
14 video-related hardware.
19 - allwinner,sun8i-v853-ppu
20 - allwinner,sun20i-d1-ppu
21 - allwinner,sun55i-a523-pck-600
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/linux/arch/arm/mach-omap1/
H A Dreset.c1 // SPDX-License-Identifier: GPL-2.0
3 * OMAP1 reset support
13 /* ARM_SYSST bit shifts related to SoC reset sources */
19 /* Standardized reset source bits (across all OMAP SoCs) */
30 * "Global Software Reset Affects Traffic Controller Frequency". in omap1_restart()
41 * omap1_get_reset_sources - return the source of the SoC's last reset
43 * Returns bits that represent the last reset source for the SoC. The
/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt7988-ethwarp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniel Golle <daniel@makrotopia.org>
14 Ethernet related subsystems found the MT7988 SoC.
15 The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
20 - const: mediatek,mt7988-ethwarp
25 '#clock-cells':
28 '#reset-cells':
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H A Dallwinner,sun9i-a80-mmc-config-clk.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-mmc-config-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 There is one clock/reset output per mmc controller. The number of
18 related to the overall mmc block.
21 "#clock-cells":
27 "#reset-cells":
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H A Dmediatek,mt7621-sysc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
21 [1]: <include/dt-bindings/clock/mt7621-clk.h>.
25 This node is also a reset provider for all the peripherals.
27 Reset related bits are defined in:
28 [2]: <include/dt-bindings/reset/mt7621-reset.h>.
33 - const: mediatek,mt7621-sysc
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/linux/drivers/soc/renesas/
H A Drcar-rst.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen1 RESET/WDT, R-Car Gen2, Gen3, and RZ/G RST Driver
11 #include <linux/soc/renesas/rcar-rst.h>
38 * Most of the R-Car Gen3 SoCs have an ARM Realtime Core.
47 return -EINVAL; in rcar_rst_set_gen3_rproc_boot_addr()
76 /* V3U firmware doesn't enable WDT reset and there won't be updates anymore */
78 .modemr = 0x00, /* MODEMR0 and it has CPG related bits */
83 .modemr = 0x00, /* MODEMR0 and it has CPG related bits */
87 /* RZ/G1 is handled like R-Car Gen2 */
88 { .compatible = "renesas,r8a7742-rst", .data = &rcar_rst_gen2 },
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/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,sc7280-mss-pil.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sibi Sankar <quic_sibis@quicinc.com>
19 - qcom,sc7280-mss-pil
23 - description: MSS QDSP6 registers
24 - description: RMB registers
26 reg-names:
28 - const: qdsp6
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/linux/include/linux/
H A Dresctrl.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 #define RESCTRL_PICK_ANY_CPU -1
36 (_r) && (_r)->rid < RDT_NUM_RESOURCES; \
37 (_r) = resctrl_arch_get_resource((_r)->rid + 1))
41 if ((r)->alloc_capable || (r)->mon_capable)
45 if ((r)->alloc_capable)
49 if ((r)->mon_capable)
62 * enum resctrl_conf_type - The type of configuration.
76 * struct pseudo_lock_region - pseudo-lock region information
78 * pseudo-locked region belongs
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/linux/drivers/pci/controller/dwc/
H A Dpcie-dw-rockchip.c1 // SPDX-License-Identifier: GPL-2.0
6 * http://www.rock-chips.com
8 * Author: Simon Xue <xxm@rock-chips.com>
23 #include <linux/reset.h>
26 #include "pcie-designware.h"
36 #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
45 /* Interrupt Status Register Related to Legacy Interrupt */
48 /* Interrupt Status Register Related to Miscellaneous Operation */
53 /* Interrupt Mask Register Related to Legacy Interrupt */
56 /* Interrupt Mask Register Related to Miscellaneous Operation */
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/linux/drivers/usb/gadget/udc/cdns2/
H A Dcdns2-gadget.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * USBHS-DEV device controller driver header file
14 #include <linux/dma-direction.h>
22 * struct cdns2_ep0_regs - endpoint 0 related registers.
45 /* EP0CS - bitmasks. */
59 /* EP0FIFO - bitmasks. */
70 * struct cdns2_epx_base - base endpoint registers.
87 /* rxcon/txcon - endpoint control register bitmasks. */
88 /* Endpoint buffering: 0 - single buffering ... 3 - quad buffering. */
106 /* rxcs/txcs - endpoint control and status bitmasks. */
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/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,usb-hs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
17 - qcom,usb-hs-phy-apq8064
18 - qcom,usb-hs-phy-msm8660
19 - qcom,usb-hs-phy-msm8960
25 reset-names:
34 reset-names:
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/linux/arch/powerpc/include/asm/
H A Dreg_booke.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright 2009-2010 Freescale Semiconductor, Inc.
12 #include <asm/ppc-opcode.h>
16 #define MSR_UCLE_LG 26 /* User-mode cache lock enable */
23 #define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */
160 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
161 #define SPRN_SLER 0x3BB /* Little-endian real mode */
197 #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
214 #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
215 #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
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/linux/arch/arm64/boot/dts/qcom/
H A Dsm8650-hdk-display-card.dtso1 // SPDX-License-Identifier: BSD-3-Clause
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
14 /dts-v1/;
17 /* Disable HDMI bridge related nodes (mutually exclusive with the display card) */
40 #address-cells = <1>;
41 #size-cells = <0>;
47 reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
49 vddio-supply = <&vreg_l12b_1p8>;
50 vci-supply = <&vreg_l13b_3p0>;
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/linux/include/uapi/linux/
H A Dfpga-dfl.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
38 * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
47 * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
58 * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
60 * Reset the FPGA Port and its AFU. No parameters are supported.
61 * Userspace can do Port reset at any time, e.g. during DMA or PR. But
64 * Return: 0 on success, -errno of failure
70 * DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1,
75 * Return: 0 on success, -errno on failure.
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/linux/Documentation/hwmon/
H A Dltc2947.rst1 Kernel drivers ltc2947-i2c and ltc2947-spi
10 Addresses scanned: -
14 https://www.analog.com/media/en/technical-documentation/data-sheets/LTC2947.pdf
25 register's to read/set energy related values. These banks can be configured
37 The following attributes are supported. Limits are read-write, reset_history
38 is write-only and all the other attributes are read-only.
41 in0_input VP-VM voltage (mV).
46 in0_reset_history Write 1 to reset in1 history
49 in0_label Channel label (VP-VM)
56 in1_reset_history Write 1 to reset in2 history
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/linux/drivers/accel/habanalabs/common/
H A Dhabanalabs.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2023 HabanaLabs, Ltd.
19 #include <linux/dma-direction.h>
28 #include <linux/io-64-nonatomic-lo-hi.h>
30 #include <linux/dma-buf.h>
45 * bits[63:59] - Encode mmap type
46 * bits[45:0] - mmap offset value
51 #define HL_MMAP_TYPE_SHIFT (59 - PAGE_SHIFT)
95 /* Default value for device reset trigger , an invalid value */
110 * enum hl_mmu_page_table_location - mmu page table location
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/linux/drivers/gpu/drm/v3d/
H A Dv3d_drv.h1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2015-2018 Broadcom */
64 * using perfmon related ioctls. A perfmon can be attached to a submit_cl
67 * done. This way, only events related to a specific job will be counted.
91 * values can't be reset, but you can fake a reset by
131 struct reset_control *reset; member
182 * reset at once.
187 * jobs, to keep the sched-fence seqnos in order.
218 return v3d->ver >= V3D_GEN_41; in v3d_has_csd()
221 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev)
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/linux/drivers/reset/sti/
H A Dreset-syscfg.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Inspired by mach-imx/src.c
18 #include "reset-syscfg.h"
21 * struct syscfg_reset_channel - Reset channel regmap configuration
23 * @reset: regmap field for the channel's reset bit.
27 struct regmap_field *reset; member
32 * struct syscfg_reset_controller - A reset controller which groups together
33 * a set of related reset bits, which may be located in different system
36 * @rst: base reset controller structure.
38 * the reset bit puts the hardware into reset.
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
H A Dchip.h1 // SPDX-License-Identifier: ISC
14 * struct brcmf_chip - chip level information.
43 * struct brcmf_core - core related information.
56 * struct brcmf_buscore_ops - buscore specific callbacks.
58 * @read32: read 32-bit value over bus.
59 * @write32: write 32-bit value over bus.
61 * @setup: bus-specific core setup.
63 * The callback should use the provided @rstvec when non-zero.
69 int (*reset)(void *ctx, struct brcmf_chip *chip); member
83 void brcmf_chip_coredisable(struct brcmf_core *core, u32 prereset, u32 reset);
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/linux/Documentation/ABI/testing/
H A Dsysfs-c2port13 The /sys/class/c2port/c2portX/ directory is related to X-th
37 access to the on-board flash of the connected micro.
45 the on-board flash block size of the connected micro.
52 the on-board flash blocks number of the connected micro.
59 the content of the on-board flash of the connected micro.
66 the "erase" command on the on-board flash of the connected
69 What: /sys/class/c2port/c2portX/reset
73 The /sys/class/c2port/c2portX/reset file execute a "reset"

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