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/linux/include/linux/ceph/
H A Dceph_debug.h23 pr_debug("%.*s %12.12s:%-4d : [%pU %llu] " fmt, \
33 no_printk(KERN_DEBUG "[%pU %llu] " fmt, \
46 pr_debug(" [%pU %llu] %s: " fmt, &client->fsid, \
52 pr_notice("[%pU %llu]: " fmt, &client->fsid, \
55 pr_info("[%pU %llu]: " fmt, &client->fsid, \
58 pr_warn("[%pU %llu]: " fmt, &client->fsid, \
61 pr_warn_once("[%pU %llu]: " fmt, &client->fsid, \
64 pr_err("[%pU %llu]: " fmt, &client->fsid, \
67 pr_warn_ratelimited("[%pU %llu]: " fmt, &client->fsid, \
70 pr_err_ratelimited("[%pU %llu]: " fmt, &client->fsid, \
/linux/arch/arm/boot/dts/st/
H A Dst-pincfg.h17 #define PU (1 << 26) macro
30 /* oe = 0, pu = 0, od = 0 */
32 /* oe = 0, pu = 1, od = 0 */
33 #define IN_PU (PU)
34 /* oe = 1, pu = 0, od = 0 */
36 /* oe = 1, pu = 0, od = 1 */
38 /* oe = 1, pu = 1, od = 1 */
39 #define BIDIR_PU (OE | PU | OD)
/linux/mm/
H A Dpercpu-stats.c176 #define PU(X) \ in percpu_stats_show()
182 PU(nr_alloc); in percpu_stats_show()
183 PU(nr_dealloc); in percpu_stats_show()
184 PU(nr_cur_alloc); in percpu_stats_show()
185 PU(nr_max_alloc); in percpu_stats_show()
186 PU(nr_chunks); in percpu_stats_show()
187 PU(nr_max_chunks); in percpu_stats_show()
188 PU(min_alloc_size); in percpu_stats_show()
189 PU(max_alloc_size); in percpu_stats_show()
193 #undef PU in percpu_stats_show()
177 #define PU( percpu_stats_show() macro
[all...]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_parser_rt.c359 rt->pu.gpr_val_upd[idx] = true; in ice_gpr_add()
360 rt->pu.gpr_val[idx] = val; in ice_gpr_add()
378 rt->pu.flg_msk |= BIT_ULL(idx); in ice_flg_add()
380 rt->pu.flg_val |= BIT_ULL(idx); in ice_flg_add()
382 rt->pu.flg_val &= ~BIT_ULL(idx); in ice_flg_add()
441 rt->pu.err_msk |= (u16)BIT(idx); in ice_err_add()
443 rt->pu.flg_val |= (u64)BIT_ULL(idx); in ice_err_add()
445 rt->pu.flg_val &= ~(u64)BIT_ULL(idx); in ice_err_add()
562 struct ice_gpr_pu *pu = &rt->pu; in ice_pu_exe() local
568 if (pu->gpr_val_upd[i]) in ice_pu_exe()
[all …]
/linux/sound/pci/
H A Dazt3328.h5 /* "PU" == "power-up value", as tested on PCI168 PCI rev. 10
24 #define IDX_IO_CODEC_DMA_FLAGS 0x00 /* PU:0x0000 */
40 #define IDX_IO_CODEC_IRQTYPE 0x02 /* PU:0x0001 */
52 /* start address of 1st DMA transfer area, PU:0x00000000 */
54 /* start address of 2nd DMA transfer area, PU:0x00000000 */
56 /* both lengths of DMA transfer areas, PU:0x00000000
59 #define IDX_IO_CODEC_DMA_CURRPOS 0x10 /* current DMA position, PU:0x00000000 */
60 /* offset within current DMA transfer area, PU:0x0000 */
62 #define IDX_IO_CODEC_SOUNDFORMAT 0x16 /* PU:0x0010 */
139 * maybe some buffer limit, but I couldn't find out more, PU:0x00ff: */
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q.dtsi33 /* ARM kHz SOC-PU uV */
50 pu-supply = <&reg_pu>;
70 /* ARM kHz SOC-PU uV */
87 pu-supply = <&reg_pu>;
105 /* ARM kHz SOC-PU uV */
122 pu-supply = <&reg_pu>;
140 /* ARM kHz SOC-PU uV */
157 pu-supply = <&reg_pu>;
H A Dimx6dl.dtsi30 /* ARM kHz SOC-PU uV */
45 pu-supply = <&reg_pu>;
63 /* ARM kHz SOC-PU uV */
78 pu-supply = <&reg_pu>;
H A Dimx6q-cm-fx6.dts192 /* ARM kHz SOC-PU uV */
214 /* ARM kHz SOC-PU uV */
236 /* ARM kHz SOC-PU uV */
258 /* ARM kHz SOC-PU uV */
/linux/fs/orangefs/
H A Dfile.c27 "%s: %pU: Handle is %pU | fs_id %d\n", __func__, in flush_racache()
83 "%s(%pU): GET op %p -> buffer_index %d\n", in wait_for_direct_io()
131 "%s(%pU): offset: %llu total_size: %zd\n", in wait_for_direct_io()
150 "%s(%pU): Calling post_io_request with tag (%llu)\n", in wait_for_direct_io()
230 gossip_err("%s: error in %s handle %pU, returning %zd\n", in wait_for_direct_io()
263 "%s(%pU): Amount %s, returned by the sys-io call:%d\n", in wait_for_direct_io()
275 "%s(%pU): PUT buffer_index %d\n", in wait_for_direct_io()
444 "calling flush_racache on %pU\n", in orangefs_file_release()
H A Dinode.c499 "%s-BEGIN(%pU): count(%d) after estimate_max_iovecs.\n", in orangefs_direct_IO()
506 "%s(%pU): proceeding with offset : %llu, " in orangefs_direct_IO()
528 "%s(%pU): size of each_count(%d)\n", in orangefs_direct_IO()
533 "%s(%pU): BEFORE wait_for_io: offset is %d\n", in orangefs_direct_IO()
541 "%s(%pU): return from wait_for_io:%d\n", in orangefs_direct_IO()
554 "%s(%pU): AFTER wait_for_io: offset is %d\n", in orangefs_direct_IO()
581 "%s(%pU): Value(%d) returned.\n", in orangefs_direct_IO()
687 "%s: %pU: Handle is %pU | fs_id %d | size is %llu\n", in orangefs_setattr_size()
879 gossip_debug(GOSSIP_INODE_DEBUG, "orangefs_update_time: %pU\n", in orangefs_update_time()
1058 "iget handle %pU, fsid %d hash %ld i_ino %lu\n", in orangefs_iget()
[all …]
H A Dacl.c45 "inode %pU, key %s, type %d\n", in orangefs_get_acl()
57 gossip_err("inode %pU retrieving acl's failed with error %d\n", in orangefs_get_acl()
87 "%s: inode %pU, key %s type %d\n", in __orangefs_set_acl()
H A Dsuper.c128 "%s: deallocated %p destroying inode %pU\n", in orangefs_destroy_inode()
327 "fh_to_dentry: handle %pU, fs_id %d\n", in orangefs_fh_to_dentry()
355 "Encoding fh: handle %pU, fsid %u\n", in orangefs_encode_fh()
367 "Encoding parent: handle %pU, fsid %u\n", in orangefs_encode_fh()
432 "get inode %pU, fsid %d\n", in orangefs_fill_sb()
H A Dxattr.c118 "getxattr on inode %pU, name %s " in orangefs_inode_getxattr()
168 "orangefs_inode_getxattr: inode %pU key %s" in orangefs_inode_getxattr()
209 "orangefs_inode_getxattr: inode %pU " in orangefs_inode_getxattr()
345 "setxattr on inode %pU, name %s\n", in orangefs_inode_setxattr()
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-common-v2.c598 * 1. PU + PD
606 int err, pu, pd; in mtk_pinconf_bias_set_pu_pd() local
609 pu = 0; in mtk_pinconf_bias_set_pu_pd()
612 pu = 1; in mtk_pinconf_bias_set_pu_pd()
615 pu = 0; in mtk_pinconf_bias_set_pu_pd()
622 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu); in mtk_pinconf_bias_set_pu_pd()
845 int pu, pd, rsel, err; in mtk_pinconf_bias_get_pu_pd_rsel() local
851 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu); in mtk_pinconf_bias_get_pu_pd_rsel()
859 if (pu == 0 && pd == 0) { in mtk_pinconf_bias_get_pu_pd_rsel()
862 } else if (pu == 1 && pd == 0) { in mtk_pinconf_bias_get_pu_pd_rsel()
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-eyeq5.c266 bool pd, pu; in eq5p_pinconf_get() local
269 pu = eq5p_test_bit(pctrl, bank, EQ5P_PU, offset); in eq5p_pinconf_get()
273 arg = !(pd || pu); in eq5p_pinconf_get()
279 arg = pu; in eq5p_pinconf_get()
310 bool pd, pu; in eq5p_pinctrl_pin_dbg_show() local
349 pu = eq5p_test_bit(pctrl, bank, EQ5P_PU, offset); in eq5p_pinctrl_pin_dbg_show()
350 if (pd && pu) in eq5p_pinctrl_pin_dbg_show()
352 else if (pd && !pu) in eq5p_pinctrl_pin_dbg_show()
354 else if (!pd && pu) in eq5p_pinctrl_pin_dbg_show()
H A Dpinctrl-st.c107 *[26] | pu | [Direction ]
148 #define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU)
149 #define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU)
233 struct regmap_field *alt, *oe, *pu, *od; member
248 const int alt, oe, pu, od, rt; member
350 .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
361 .pu = -1, /* Not Available */
386 struct regmap_field *pull_up = pc->pu; in st_pinconf_set_config()
583 if (pc->pu) { in st_pinconf_get_direction()
584 regmap_field_read(pc->pu, &pu_value); in st_pinconf_get_direction()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dgm200.c34 gm200_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu) in gm200_sor_dp_drive() argument
41 pu &= 0x0f; in gm200_sor_dp_drive()
46 if ((data[2] & 0x00000f00) < (pu << 8) || ln == 0) in gm200_sor_dp_drive()
47 data[2] = (data[2] & ~0x00000f00) | (pu << 8); in gm200_sor_dp_drive()
/linux/drivers/pmdomain/imx/
H A Dgpc.c260 .name = "PU",
371 domain->supply = devm_regulator_get(dev, "pu"); in imx_gpc_old_dt_init()
432 * Disable PU power down by runtime PM if ERR009619 is present. in imx_gpc_probe()
435 * PU domain LDO from power down state. If PRE is in use at that time, in imx_gpc_probe()
439 * it's safe to power down PU in this case. in imx_gpc_probe()
527 dev_err(&pdev->dev, "Failed to remove PU power domain (%pe)\n", in imx_gpc_remove()
/linux/arch/arm64/boot/dts/freescale/
H A Dimx93-tqma9352.dtsi239 /* HYS | PU | FSEL 3 | DSE X6 */
242 /* HYS | FSEL 3 | DSE X6 (external PU) */
258 /* HYS | PU */
293 /* PU | FSEL 1 | DSE X4 */
H A Dimx93-tqma9352-mba93xxca.dts692 /* HYS | PU | FSEL_0 | DSE no drive */
694 /* PU | FSEL_3 | DSE X4 */
701 /* HYS | PU | FSEL_0 | DSE no drive */
703 /* PU | FSEL_3 | DSE X4 */
781 /* HYS | PU | FSEL_0 | no DSE */
878 /* HYS | PU | FSEL_3 | DSE X4 */
880 /* HYS | PU | FSEL_3 | DSE X3 */
895 /* HYS | PU | FSEL_3 | DSE X4 */
H A Dimx93-tqma9352-mba93xxla.dts662 /* HYS | PU | FSEL_0 | DSE no drive */
664 /* PU | FSEL_3 | DSE X4 */
671 /* HYS | PU | FSEL_0 | DSE no drive */
673 /* PU | FSEL_3 | DSE X4 */
840 /* HYS | PU | FSEL_3 | DSE X4 */
842 /* HYS | PU | FSEL_3 | DSE X3 */
857 /* HYS | PU | FSEL_3 | DSE X4 */
H A Dimx93-tqma9352-mba91xxca.dts627 fsl,pins = /* HYS | PU | FSEL_0 | DSE no drive */
629 /* PU | FSEL_3 | DSE X4 */
725 /* HYS | PU | FSEL_3 | DSE X4 */
727 /* HYS | PU | FSEL_3 | DSE X3 */
740 /* HYS | PU | FSEL_3 | DSE X4 */
/linux/arch/arm64/kernel/
H A Dcompat_alignment.c109 * PU = 01 B A
110 * PU = 11 B A
111 * PU = 00 A B
112 * PU = 10 A B
/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-etm.yaml98 TRCPDCR.PU does not have to be set on Qualcomm Technologies Inc. systems
101 watchdog counter is stopped when TRCPDCR.PU is set.
/linux/drivers/gpio/
H A Dgpio-tps68470.c11 * Yuning Pu <yuning.pu@intel.com>

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