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/linux/drivers/media/cec/core/
H A Dcec-pin.c11 #include <media/cec-pin.h>
12 #include "cec-pin-priv.h"
112 static void cec_pin_update(struct cec_pin *pin, bool v, bool force) in cec_pin_update() argument
114 if (!force && v == pin->adap->cec_pin_is_high) in cec_pin_update()
117 pin->adap->cec_pin_is_high = v; in cec_pin_update()
118 if (atomic_read(&pin->work_pin_num_events) < CEC_NUM_PIN_EVENTS) { in cec_pin_update()
121 if (pin->work_pin_events_dropped) { in cec_pin_update()
122 pin->work_pin_events_dropped = false; in cec_pin_update()
125 pin->work_pin_events[pin->work_pin_events_wr] = ev; in cec_pin_update()
126 pin->work_pin_ts[pin->work_pin_events_wr] = ktime_get(); in cec_pin_update()
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dsama5d3_lcd.dtsi60 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
61 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
62 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
63 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
64 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
65 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
66 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
67 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
68 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
69 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
H A Dat91sam9x5_lcd.dtsi63 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
64 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
65 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
66 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
67 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
68 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
69 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
70 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
71 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
72 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynosautov9-pinctrl.dtsi3 * Samsung's ExynosAutov9 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov9 SoC pin-mux and pin-config options are listed as
42 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
47 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
60 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
61 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
66 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
67 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
106 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
107 samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
[all …]
H A Dexynos7870-pinctrl.dtsi3 * Samsung Exynos7870 SoC pin-mux and pin-config device tree source
81 samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
82 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
83 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
84 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
89 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
90 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
91 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
92 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
97 samsung,pin-function = <EXYNOS_PIN_FUNC_6>;
[all …]
H A Dexynos7885-pinctrl.dtsi3 * Samsung Exynos7885 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as
84 samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
85 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
90 samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
91 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
96 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
97 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
98 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
99 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
[all …]
H A Dexynosautov920-pinctrl.dtsi3 * Samsung's ExynosAutov920 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov920 SoC pin-mux and pin-config options are listed as
182 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
183 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
184 samsung,pin-con-pdn = <EXYNOS_PIN_PULL_NONE>;
189 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
190 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
191 samsung,pin-con-pdn = <EXYNOS_PIN_PULL_DOWN>;
196 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
197 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
[all …]
H A Dexynos5433-pinctrl.dtsi3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
14 #define PIN(_pin, _func, _pull, _drv) \ macro
15 pin- ## _pin { \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
23 PIN(_pin, INPUT, _pull, _drv)
26 PIN(_pin, OUTPUT, _pull, _drv)
29 PIN(_pin, 2, _pull, _drv)
[all …]
H A Dexynos7-pinctrl.dtsi3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
189 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
190 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
191 samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
196 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
197 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
198 samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
203 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
204 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
[all …]
H A Dexynos850-pinctrl.dtsi3 * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
108 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
109 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
110 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
116 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
117 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
118 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
124 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
125 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210-pinctrl.dtsi3 * Samsung's S5PV210 SoC device tree source - pin control-related
11 * Samsung's S5PV210 SoC pin banks, pin-mux and pin-config options are
18 pin- ## _pin { \
20 samsung,pin-con-pdn = <S5PV210_PIN_PDN_ ##_mode>; \
21 samsung,pin-pud-pdn = <S5PV210_PIN_PULL_ ##_pull>; \
279 samsung,pin-function = <S5PV210_PIN_FUNC_2>;
280 samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
281 samsung,pin-drv = <S5PV210_PIN_DRV_LV1>;
286 samsung,pin-function = <S5PV210_PIN_FUNC_2>;
287 samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
[all …]
H A Dexynos4x12-pinctrl.dtsi3 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device
15 pin- ## _pin { \
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
128 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
129 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
130 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
135 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
136 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
[all …]
H A Dexynos4210-pinctrl.dtsi3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
10 * Samsung's Exynos4210 SoC pin-mux and pin-config options are listed as device
147 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
148 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
149 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
154 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
155 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
156 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
161 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
162 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
[all …]
H A Dexynos5250-pinctrl.dtsi3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5250 SoC pin-mux and pin-config options are listed as device
202 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
203 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
204 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
209 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
210 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
211 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
216 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
217 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
[all …]
H A Dexynos3250-pinctrl.dtsi3 * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos3250 SoCs pin-mux and pin-config options are listed as device
15 pin- ## _pin { \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \
23 pin- ## _pin { \
25 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
26 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
88 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
[all …]
H A Dexynos5420-pinctrl.dtsi3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
63 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
64 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
65 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
70 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
71 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
72 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
162 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
163 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
[all …]
H A Ds3c64xx-pinctrl.dtsi4 * - pin control-related definitions
8 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
16 * Pin banks
131 * Pin groups
136 samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
137 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
142 samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
143 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
148 samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
149 samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
[all …]
H A Dexynos5260-pinctrl.dtsi3 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
201 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
202 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
203 samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>;
208 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
209 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
210 samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>;
215 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
216 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
[all …]
H A Dexynos5410-pinctrl.dtsi3 * Exynos5410 SoC pin-mux and pin-config device tree source
282 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
283 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
284 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
289 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
290 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
291 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
296 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
297 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
298 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
[all …]
/linux/arch/arm64/boot/dts/exynos/google/
H A Dgs101-pinctrl.dtsi3 * GS101 SoC pin-mux and pin-config device tree source
120 samsung,pin-function = <GS101_PIN_FUNC_2>;
121 samsung,pin-pud = <GS101_PIN_PULL_NONE>;
126 samsung,pin-function = <GS101_PIN_FUNC_2>;
127 samsung,pin-pud = <GS101_PIN_PULL_NONE>;
132 samsung,pin-function = <GS101_PIN_FUNC_2>;
133 samsung,pin-pud = <GS101_PIN_PULL_NONE>;
138 samsung,pin-function = <GS101_PIN_FUNC_2>;
139 samsung,pin-pud = <GS101_PIN_PULL_NONE>;
140 samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
[all …]
/linux/drivers/pinctrl/renesas/
H A Dpinctrl-rza1.c3 * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC
9 * This pin controller/gpio combined driver supports Renesas devices of RZ/A1
57 * Use 16 lower bits [15:0] for pin identifier
58 * Use 16 higher bits [31:16] for pin mux function
70 /* Pin mux flags */
80 * rza1_bidir_pin - describe a single pin that needs bidir flag applied.
83 u8 pin: 4; member
97 * rza1_swio_pin - describe a single pin that needs swio flag applied.
100 u16 pin: 4; member
127 { .pin = 0, .func = 1 },
[all …]
/linux/arch/arm64/boot/dts/tesla/
H A Dfsd-pinctrl.dtsi56 samsung,pin-function = <FSD_PIN_FUNC_2>;
57 samsung,pin-pud = <FSD_PIN_PULL_DOWN>;
58 samsung,pin-drv = <FSD_PIN_DRV_LV4>;
63 samsung,pin-function = <FSD_PIN_FUNC_2>;
64 samsung,pin-pud = <FSD_PIN_PULL_UP>;
65 samsung,pin-drv = <FSD_PIN_DRV_LV4>;
70 samsung,pin-function = <FSD_PIN_FUNC_2>;
71 samsung,pin-pud = <FSD_PIN_PULL_DOWN>;
72 samsung,pin-drv = <FSD_PIN_DRV_LV6>;
77 samsung,pin-function = <FSD_PIN_FUNC_2>;
[all …]
/linux/drivers/dpll/zl3073x/
H A Ddpll.c29 * struct zl3073x_dpll_pin - DPLL pin
30 * @list: this DPLL pin list entry
31 * @dpll: DPLL the pin is registered to
36 * @dir: pin direction
37 * @id: pin id
38 * @prio: pin priority <0, 14>
41 * @pin_state: last saved pin state
42 * @phase_offset: last saved pin phase offset
72 * zl3073x_dpll_is_input_pin - check if the pin is input one
73 * @pin
75 zl3073x_dpll_is_input_pin(struct zl3073x_dpll_pin * pin) zl3073x_dpll_is_input_pin() argument
87 zl3073x_dpll_is_p_pin(struct zl3073x_dpll_pin * pin) zl3073x_dpll_is_p_pin() argument
98 struct zl3073x_dpll_pin *pin = pin_priv; zl3073x_dpll_pin_direction_get() local
108 struct zl3073x_dpll_pin *pin; zl3073x_dpll_pin_get_by_ref() local
129 struct zl3073x_dpll_pin *pin = pin_priv; zl3073x_dpll_input_pin_esync_get() local
170 struct zl3073x_dpll_pin *pin = pin_priv; zl3073x_dpll_input_pin_esync_set() local
200 struct zl3073x_dpll_pin *pin = pin_priv; zl3073x_dpll_input_pin_ffo_get() local
215 struct zl3073x_dpll_pin *pin = pin_priv; zl3073x_dpll_input_pin_frequency_get() local
233 struct zl3073x_dpll_pin *pin = pin_priv; zl3073x_dpll_input_pin_frequency_set() local
409 struct zl3073x_dpll_pin *pin = pin_priv; zl3073x_dpll_input_pin_phase_offset_get() local
469 struct zl3073x_dpll_pin *pin = pin_priv; zl3073x_dpll_input_pin_phase_adjust_get() local
502 struct zl3073x_dpll_pin *pin = pin_priv; zl3073x_dpll_input_pin_phase_adjust_set() local
530 zl3073x_dpll_ref_prio_get(struct zl3073x_dpll_pin * pin,u8 * prio) zl3073x_dpll_ref_prio_get() argument
571 zl3073x_dpll_ref_prio_set(struct zl3073x_dpll_pin * pin,u8 prio) zl3073x_dpll_ref_prio_set() argument
622 zl3073x_dpll_ref_state_get(struct zl3073x_dpll_pin * pin,enum dpll_pin_state * state) zl3073x_dpll_ref_state_get() argument
666 struct zl3073x_dpll_pin *pin = pin_priv; zl3073x_dpll_input_pin_state_on_dpll_get() local
680 struct zl3073x_dpll_pin *pin = pin_priv; zl3073x_dpll_input_pin_state_on_dpll_set() local
750 struct zl3073x_dpll_pin *pin = pin_priv; zl3073x_dpll_input_pin_prio_get() local
762 struct zl3073x_dpll_pin *pin = pin_priv; zl3073x_dpll_input_pin_prio_set() local
791 struct zl3073x_dpll_pin *pin = pin_priv; zl3073x_dpll_output_pin_esync_get() local
859 struct zl3073x_dpll_pin *pin = pin_priv; zl3073x_dpll_output_pin_esync_set() local
922 struct zl3073x_dpll_pin *pin = pin_priv; zl3073x_dpll_output_pin_frequency_get() local
938 struct zl3073x_dpll_pin *pin = pin_priv; zl3073x_dpll_output_pin_frequency_set() local
1017 struct zl3073x_dpll_pin *pin = pin_priv; zl3073x_dpll_output_pin_phase_adjust_get() local
1040 struct zl3073x_dpll_pin *pin = pin_priv; zl3073x_dpll_output_pin_phase_adjust_set() local
1253 struct zl3073x_dpll_pin *pin; zl3073x_dpll_mode_set() local
1376 struct zl3073x_dpll_pin *pin; zl3073x_dpll_pin_alloc() local
1396 zl3073x_dpll_pin_free(struct zl3073x_dpll_pin * pin) zl3073x_dpll_pin_free() argument
1413 zl3073x_dpll_pin_register(struct zl3073x_dpll_pin * pin,u32 index) zl3073x_dpll_pin_register() argument
1486 zl3073x_dpll_pin_unregister(struct zl3073x_dpll_pin * pin) zl3073x_dpll_pin_unregister() argument
1515 struct zl3073x_dpll_pin *pin, *next; zl3073x_dpll_pins_unregister() local
1606 struct zl3073x_dpll_pin *pin; zl3073x_dpll_pins_register() local
1723 zl3073x_dpll_pin_phase_offset_check(struct zl3073x_dpll_pin * pin) zl3073x_dpll_pin_phase_offset_check() argument
1783 zl3073x_dpll_pin_ffo_check(struct zl3073x_dpll_pin * pin) zl3073x_dpll_pin_ffo_check() argument
1825 struct zl3073x_dpll_pin *pin; zl3073x_dpll_changes_check() local
[all...]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.c54 * enum ice_dpll_pin_type - enumerate ice pin types:
55 * @ICE_DPLL_PIN_INVALID: invalid pin type
56 * @ICE_DPLL_PIN_TYPE_INPUT: input pin
57 * @ICE_DPLL_PIN_TYPE_OUTPUT: output pin
58 * @ICE_DPLL_PIN_TYPE_RCLK_INPUT: recovery clock input pin
84 * ice_dpll_is_sw_pin - check if given pin shall be controlled by SW
86 * @index: index of a pin as understood by FW
89 * Check if the pin shall be controlled by SW - instead of providing raw access
90 * for pin control. For E810 NIC with dpll there is additional MUX-related logic
96 * * true - pin controlled by SW
[all …]
/linux/drivers/dpll/
H A Ddpll_core.c74 void dpll_pin_notify(struct dpll_pin *pin, unsigned long action) in dpll_pin_notify() argument
77 .pin = pin, in dpll_pin_notify()
78 .id = pin->id, in dpll_pin_notify()
79 .idx = pin->pin_idx, in dpll_pin_notify()
80 .clock_id = pin->clock_id, in dpll_pin_notify()
81 .fwnode = pin->fwnode, in dpll_pin_notify()
82 .prop = &pin->prop, in dpll_pin_notify()
124 static void dpll_pin_tracker_alloc(struct dpll_pin *pin, dpll_tracker *tracker) in dpll_pin_tracker_alloc() argument
127 ref_tracker_alloc(&pin in dpll_pin_tracker_alloc()
131 dpll_pin_tracker_free(struct dpll_pin * pin,dpll_tracker * tracker) dpll_pin_tracker_free() argument
138 __dpll_pin_hold(struct dpll_pin * pin,dpll_tracker * tracker) __dpll_pin_hold() argument
147 __dpll_pin_put(struct dpll_pin * pin,dpll_tracker * tracker) __dpll_pin_put() argument
187 dpll_xa_ref_pin_add(struct xarray * xa_pins,struct dpll_pin * pin,const struct dpll_pin_ops * ops,void * priv,void * cookie) dpll_xa_ref_pin_add() argument
240 dpll_xa_ref_pin_del(struct xarray * xa_pins,struct dpll_pin * pin,const struct dpll_pin_ops * ops,void * priv,void * cookie) dpll_xa_ref_pin_del() argument
637 struct dpll_pin *pin; dpll_pin_alloc() local
780 dpll_pin_put(struct dpll_pin * pin,dpll_tracker * tracker) dpll_pin_put() argument
795 dpll_pin_fwnode_set(struct dpll_pin * pin,struct fwnode_handle * fwnode) dpll_pin_fwnode_set() argument
820 struct dpll_pin *pin, *ret = NULL; fwnode_dpll_pin_find() local
838 __dpll_pin_register(struct dpll_device * dpll,struct dpll_pin * pin,const struct dpll_pin_ops * ops,void * priv,void * cookie) __dpll_pin_register() argument
872 dpll_pin_register(struct dpll_device * dpll,struct dpll_pin * pin,const struct dpll_pin_ops * ops,void * priv) dpll_pin_register() argument
896 struct dpll_pin *pin, *ref_sync_pin; dpll_pin_ref_sync_pair_del() local
909 __dpll_pin_unregister(struct dpll_device * dpll,struct dpll_pin * pin,const struct dpll_pin_ops * ops,void * priv,void * cookie) __dpll_pin_unregister() argument
930 dpll_pin_unregister(struct dpll_device * dpll,struct dpll_pin * pin,const struct dpll_pin_ops * ops,void * priv) dpll_pin_unregister() argument
960 dpll_pin_on_pin_register(struct dpll_pin * parent,struct dpll_pin * pin,const struct dpll_pin_ops * ops,void * priv) dpll_pin_on_pin_register() argument
1015 dpll_pin_on_pin_unregister(struct dpll_pin * parent,struct dpll_pin * pin,const struct dpll_pin_ops * ops,void * priv) dpll_pin_on_pin_unregister() argument
1042 dpll_pin_ref_sync_pair_add(struct dpll_pin * pin,struct dpll_pin * ref_sync_pin) dpll_pin_ref_sync_pair_add() argument
1096 dpll_pin_on_dpll_priv(struct dpll_device * dpll,struct dpll_pin * pin) dpll_pin_on_dpll_priv() argument
1109 dpll_pin_on_pin_priv(struct dpll_pin * parent,struct dpll_pin * pin) dpll_pin_on_pin_priv() argument
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