| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | amlogic,meson-g12a-usb-ctrl.yaml | 113 - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used
115 - const: usb3-phy0 # USB3 PHY if USB3_0 is used
132 - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used
152 - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used
214 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
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| /linux/drivers/phy/allwinner/ |
| H A D | phy-sun4i-usb.c | 80 /* A83T specific control bits for PHY0 */
129 /* phy0 / otg related variables */
471 /* For phy0 only turn on Vbus if we don't have an ext. Vbus */ in sun4i_usb_phy_power_on()
503 * phy0 vbus typically slowly discharges, sometimes this causes the in sun4i_usb_phy_power_off()
574 /* Host mode. Route phy0 to EHCI/OHCI */ in sun4i_usb_phy0_reroute()
577 /* Peripheral mode. Route phy0 to MUSB */ in sun4i_usb_phy0_reroute()
587 struct phy *phy0 = data->phys[0].phy; in sun4i_usb_phy0_id_vbus_det_scan() local
592 if (!phy0) in sun4i_usb_phy0_id_vbus_det_scan()
595 phy = phy_get_drvdata(phy0); in sun4i_usb_phy0_id_vbus_det_scan()
599 mutex_lock(&phy0->mutex); in sun4i_usb_phy0_id_vbus_det_scan()
[all …]
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| /linux/arch/arm64/boot/dts/broadcom/stingray/ |
| H A D | stingray-usb.dtsi | 29 phy-names = "phy0", "phy1";
39 phy-names = "phy0", "phy1";
63 phy-names = "phy0", "phy1", "phy2";
73 phy-names = "phy0";
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | qcom,sm8450-dispcc.yaml | 30 - description: Byte clock from DSI PHY0
31 - description: Pixel clock from DSI PHY0
34 - description: Link clock from DP PHY0
35 - description: VCO DIV clock from DP PHY0
|
| H A D | qcom,sm8550-dispcc.yaml | 35 - description: Byte clock from DSI PHY0
36 - description: Pixel clock from DSI PHY0
39 - description: Link clock from DP PHY0
40 - description: VCO DIV clock from DP PHY0
|
| H A D | qcom,sm6115-dispcc.yaml | 27 - description: Byte clock from DSI PHY0
28 - description: Pixel clock from DSI PHY0
|
| H A D | qcom,gcc-msm8953.yaml | 27 - description: Byte clock from DSI PHY0
28 - description: Pixel clock from DSI PHY0
|
| H A D | qcom,sm4450-dispcc.yaml | 32 - description: Byte clock from DSI PHY0
33 - description: Pixel clock from DSI PHY0
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | qcom-emac.txt | 48 phy-handle = <&phy0>;
52 phy0: ethernet-phy@0 {
97 phy-handle = <&phy0>;
101 phy0: ethernet-phy@4 {
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| /linux/arch/riscv/boot/dts/microchip/ |
| H A D | mpfs-polarberry.dts | 34 * phy0 is connected to mac0, but the port itself is on the (optional) carrier
39 phy-handle = <&phy0>;
52 phy0: ethernet-phy@4 { label
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | fsl-ls1028a-kontron-sl28-var1.dts | 28 phy0: ethernet-phy@4 { label
51 /* Delete the phy-handle to the old phy0 label */
56 phy-handle = <&phy0>;
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| /linux/drivers/phy/nuvoton/ |
| H A D | phy-ma35d1-usb2.c | 45 * USB PHY0 is in operation mode already in ma35_usb_phy_power_on()
55 * reset USB PHY0. in ma35_usb_phy_power_on()
56 * wait until USB PHY0 60 MHz UTMI Interface Clock ready in ma35_usb_phy_power_on()
61 /* make USB PHY0 enter operation mode */ in ma35_usb_phy_power_on()
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| /linux/drivers/staging/media/max96712/ |
| H A D | max96712.c | 133 /* Configure a 3-lane C-PHY using PHY0 and PHY1. */ in max96712_mipi_configure()
140 /* Configure a 4-lane D-PHY using PHY0 and PHY1. */ in max96712_mipi_configure()
144 /* Configure lane mapping for PHY0 and PHY1. */ in max96712_mipi_configure()
148 /* Configure lane polarity for PHY0 and PHY1. */ in max96712_mipi_configure()
154 /* Set link frequency for PHY0 and PHY1. */ in max96712_mipi_configure()
160 /* Enable PHY0 and PHY1 */ in max96712_mipi_configure()
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| /linux/arch/arm64/boot/dts/marvell/ |
| H A D | armada-8040-mcbin.dts | 20 phy0: ethernet-phy@0 { label
36 phy = <&phy0>;
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| H A D | cn9130-db-comexpress.dtsi | 49 phy = <&phy0>;
60 phy0: ethernet-phy@0 { label
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| /linux/arch/arm/boot/dts/rockchip/ |
| H A D | rk3036-evb.dts | 18 phy = <&phy0>;
29 phy0: ethernet-phy@0 { label
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| /linux/arch/arm64/boot/dts/toshiba/ |
| H A D | tmpv7708-visrobo-vrb.dts | 43 phy-handle = <&phy0>;
50 phy0: ethernet-phy@1 { label
|
| H A D | tmpv7708-rm-mbrc.dts | 43 phy-handle = <&phy0>;
50 phy0: ethernet-phy@1 { label
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| /linux/arch/arm/boot/dts/st/ |
| H A D | stm32mp151a-prtt1a.dts | 16 phy-handle = <&phy0>;
21 phy0: ethernet-phy@0 { label
|
| H A D | stm32mp151a-prtt1s.dts | 16 phy-handle = <&phy0>;
51 phy0: ethernet-phy@0 { label
|
| /linux/arch/arm64/boot/dts/renesas/ |
| H A D | cat875.dtsi | 20 phy-handle = <&phy0>;
24 phy0: ethernet-phy@0 { label
|
| H A D | hihope-rzg2-ex.dtsi | 21 phy-handle = <&phy0>;
26 phy0: ethernet-phy@0 { label
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | nvidia,tegra20-usb-phy.yaml | 32 PHY0 and PHY2 share power and ground, PHY0 contains shared registers.
33 PHY0 and PHY2 must specify two register sets, where the first set is
34 PHY own registers and the second set is the PHY0 registers.
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| /linux/arch/powerpc/boot/dts/ |
| H A D | cm5200.dts | 51 phy-handle = <&phy0>;
55 phy0: ethernet-phy@0 { label
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| /linux/arch/arm/boot/dts/intel/ixp/ |
| H A D | intel-ixp42x-ixdp425.dts | 47 phy-handle = <&phy0>;
53 phy0: ethernet-phy@0 { label
|