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/illumos-gate/usr/src/cmd/fm/eversholt/files/i386/i86pc/
H A Damd64.esc41 #define SET_ADDR (setpayloadprop("asru-physaddr", payloadprop("IA32_MCi_ADDR")))
43 #define SET_OFFSET (setpayloadprop("asru-offset", \
44 payloadprop("resource[0].hc-specific.offset")))
48 * payload - regardless of type (e.g., nvlist or nvlist array) or value.
57 * "prop foo@chip/memory-controller/dimm/rank -> blah@chip/core/strand"
60 * the lhs path and rhs path do not match, expands to the cross-product of
61 * all dimms, ranks and cpus on the same chip (since chip appears in the
66 asru(chip/memory-controller/dimm/rank)) \
68 asru(chip/memory-controller/dimm)))
72 * correctable (from a mem_ce ereport) is single-bit or multi-bit. For a
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/illumos-gate/usr/src/man/man9e/
H A Dmac.9e33 framework provides a means for implementing high-performance networking
75 .Ss High-Level Design
76 At a high-level, a device driver is chiefly concerned with three general
78 .Bl -enum -offset indent
94 Configuration of a device, such as whether auto-negotiation should be
138 structure and the corresponding NULL-terminated
204 .Bd -literal -offset indent
303 .Bl -bullet -offset indent -compact
346 In addition to the per-packet flow described below, there are certain
356 .Bl -enum -offset indent
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/illumos-gate/usr/src/uts/intel/io/intel_nhm/
H A Dintel_nhmdrv.c109 rt = -1; in inhm_mc_snapshot_update()
121 int chip; in inhm_mc_ioctl() local
128 chip = getminor(dev) % MAX_CPU_NODES; in inhm_mc_ioctl()
129 if (inhm_mc_nvl[chip] == NULL || in inhm_mc_ioctl()
135 if (inhm_mc_nvl[chip]) in inhm_mc_ioctl()
137 inhm_create_nvl(chip); in inhm_mc_ioctl()
143 mcs.mcs_size = (uint32_t)inhm_mc_snapshotsz[chip]; in inhm_mc_ioctl()
151 if (ddi_copyout(inhm_mc_snapshot[chip], (void *)arg, in inhm_mc_ioctl()
152 inhm_mc_snapshotsz[chip], mode) < 0) in inhm_mc_ioctl()
203 (void) snprintf(buf, sizeof (buf), "mc-intel-%d", i); in inhm_mc_attach()
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/illumos-gate/usr/src/man/man4d/
H A Dbnxe.4d16 bnxe \- QLogic NetXtreme II 10 Gigabit Ethernet Device Driver
26 Ethernet driver is a multi-threaded, loadable,
27 clonable, GLDv3-based driver supporting the Data Link Provider Interface,
36 Functions include chip initialization, frame transmit and receive,
74 "l2chip"
75 for layer 2 chip stats,
100 % kstat -m bnxe -i 0 -l
H A Dqede.4d25 Ethernet driver is a multi-threaded, loadable, clonable, GLDv3-based
36 Functions include chip initialization, frame transmit and receive,
71 .Bl -tag -width Em
75 for layer 2 chip stats
93 .Bd -literal -offset indent
94 # kstat -m qede -i 0 -l
H A Dchxge.4d8 chxge \- Chelsio Ethernet network interface controllers
18 The \fBchxge\fR Ethernet driver is a multi-threaded, loadable, clonable,
23 include chip initialization, frame transmit and receive, and error recovery and
28 The cloning, character-special device \fB/dev/chxge\fR is used to access NIC
63 The sap length value is -2, meaning the physical address component is
64 followed immediately by a 2-byte sap component within the DLSAP address.
98 x86 platform kernel module. (32-bit).
107 x86 platform kernel module. (64-bit).
H A Dntxn.4d8 ntxn \- NetXen 10/1 Gigabit Ethernet network driver
18 The \fBntxn\fR 10/1 Gigabit Ethernet driver is a multi-threaded, loadable,
19 clonable, GLD-based STREAMS driver supporting the Data Link Provider Interface,
23 The \fBntxn\fR driver functions include chip initialization, frames transmit
24 and receive, promiscuous and multicast support, TCP and UDP checksum off-load
28 The \fBntxn\fR driver and hardware support the 10GBASE CX4, 10GBASE-SR/W, LR/W,
29 and 10/100/1000BASE-T physical layers.
33 The cloning character-special device, \fB/dev/ntxn\fR, is used to access all
72 SAP (Service Access Point) length value is -2, meaning the physical address
73 component is followed immediately by a 2-byte SAP component within the DLSAP
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H A Dccid.4d19 .Nd chip card interface device USB client class driver
31 driver is a USB CCID (chip card interface device) class device driver.
140 To facilitate non-blocking operation, the underlying file descriptor may
149 .Bl -tag -width POLLRDNORM
165 Because transactions are on a per-slot basis, it is still possible for a
171 .Bl -bullet -offset indent
200 command, opening the device node read-only is sufficient.
233 If a multi-threaded application opens a slot once and shares it among multiple
242 Consequently, all threads in a multi-threaded application share the transaction
281 .Bl -tag -width Fa
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H A Dhxge.4d8 hxge \- Sun Blade 10 Gigabit Ethernet network driver
15 The \fBhxge\fR Gigabit Ethernet driver is a multi-threaded, loadable, clonable,
16 GLD-based STREAMS driver supporting the Data Link Provider Interface,
20 The Shared PCI-Express 10 Gb networking interface provides network I/O
25 The \fBhxge\fR driver functions include chip initialization, frame transmit and
29 The cloning character-special device, \fB/dev/hxge\fR, is used to access Sun
43 initialized on first attach and de-initialized (stopped) at last detach
52 Maximum SDU is 1500 (ETHERMTU - defined in <\fBsys/ethernet.h\fR>).
76 \fBSAP\fR length value is \fI-2\fR, meaning the physical address component is
77 followed immediately by a 2-byte \fBSAP\fR component within the \fBDLSAP\fR
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H A Dnxge.4d8 nxge \- Sun 10/1 Gigabit Ethernet network driver
18 The \fBnxge\fR Gigabit Ethernet driver is a multi-threaded, loadable, clonable,
19 GLD-based STREAMS driver supporting the Data Link Provider Interface,
21 Gigabit Ethernet fiber XFP low profile adapter and the 10/100/1000BASE-T x8
25 The \fBnxge\fR driver functions include chip initialization, frame transmit and
30 The \fBnxge\fR device provides fully-compliant \fIIEEE 802.3ae\fR 10Gb/s full
31 duplex operation using XFP-based 10GigE optics (NIU, dual 10 Gigabit fiber XFP
32 adapter). The Sun Ethernet hardware supports the \fIIEEE 802.3x\fR frame-based
36 For the 10/100/1000BASE-T adapter, the \fBnxge\fR driver and hardware support
37 auto-negotiation, a protocol specified by the \fI1000 Base-T\fR standard.
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/illumos-gate/usr/src/lib/fm/topo/modules/i86pc/chip/
H A Dchip.c54 #include "chip.h"
61 * system. For each chip found, the necessary nodes (one or more cores, and
74 { PGNAME(CHIP), TOPO_STABILITY_PRIVATE, TOPO_STABILITY_PRIVATE, 1 };
118 topo_mod_dprintf(mod, "initializing chip enumerator\n"); in _topo_init()
123 return (-1); /* mod errno set */ in _topo_init()
138 static int r = -1; in is_xpv()
141 if (r != -1) in is_xpv()
227 return (-1); in create_strand()
233 return (-1); in create_strand()
238 return (-1); in create_strand()
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H A Dchip_label.c99 * uni-socket x86/x64 platforms. This method assumes a direct linear
103 * format: a string containing a printf-like format with a single %d token
137 return (-1); in simple_dimm_label()
147 return (-1); in simple_dimm_label()
156 * multi-socket x86/x64 platforms. It takes the following two arguments:
158 * format: a string containing a printf-like format with a two %d tokens
168 * order: "reverse" or "forward" - sets the direction of the correlation
171 * dimms_per_chip: the number of DIMM slots per chip
179 tnode_t *chip; in simple_dimm_label_mp() local
211 return (-1); in simple_dimm_label_mp()
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/illumos-gate/usr/src/uts/intel/sys/
H A Di8272A.h74 /* MSR - Main Status Register */
75 #define MS_RQM 0x80 /* request for master - chip needs attention */
77 #define MS_NDM 0x20 /* non-dma mode - 1 during execution phase */
125 #define FO_NSC 0x18 /* identify National chip */
128 #define FO_MT 0x80 /* multi-track operation */
158 * controller chip values
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_devinfo.c45 return pdev->vars.last_recycling_timestamp; in lm_get_timestamp_of_recent_cid_recycling()
54 return pdev->params.max_supported_toe_cons; in lm_get_max_supported_toe_cons()
63 return (pdev->params.l4_rss_is_possible != L4_RSS_DISABLED); in lm_get_toe_rss_possibility()
102 if (pdev->hw_info.mcp_detected == 1) in lm_get_iscsi_boot_info_block()
106 iscsi_info_block_hdr_ptr->signature = val ; in lm_get_iscsi_boot_info_block()
112 SET_FLAGS(iscsi_info_block_hdr_ptr->boot_flags, BOOT_INFO_FLAGS_UEFI_BOOT ); in lm_get_iscsi_boot_info_block()
116 RESET_FLAGS(iscsi_info_block_hdr_ptr->boot_flags, BOOT_INFO_FLAGS_UEFI_BOOT ); in lm_get_iscsi_boot_info_block()
122 iscsi_info_block_hdr_ptr->signature = 0; in lm_get_iscsi_boot_info_block()
136 if (pdev->hw_info.mcp_detected == 1) in lm_get_ibft_physical_addr_for_efi()
140 //iscsi_info_block_hdr_ptr->signature = val ; in lm_get_ibft_physical_addr_for_efi()
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H A Dlm_hw_init_reset.c34 * This file contains functions that handle chip init and reset
126 } reg_valid; /* 1 if valid for chip 0 o/`w */
137 const u8_t bus_num = INST_ID_TO_BUS_NUM(PFDEV(pdev)->vars.inst_id) ; in lm_reset_set_inprogress()
145 const u8_t bus_num = INST_ID_TO_BUS_NUM(PFDEV(pdev)->vars.inst_id) ; in lm_reset_clear_inprogress()
153 const u8_t bus_num = INST_ID_TO_BUS_NUM(PFDEV(pdev)->vars.inst_id) ; in lm_pm_reset_is_inprogress()
177 if (!pdev->params.enable_error_recovery || CHIP_IS_E1x(pdev)) in lm_er_handling_pending()
193 pdev->panic || in lm_reset_is_inprogress()
200 *------------------------------------------------------------------------
201 * FLR in progress handling -
202 *-------------------------------------------------------------------------
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/illumos-gate/usr/src/uts/intel/io/mc-amd/
H A Dmcamd_drv.c62 * Set to prevent mc-amd from attaching.
68 * dimms. Unfortunately, no memory-controller register indicates the
70 * of slots per cpu, and chip-select lines per slot, The following may be set
86 * The values range from 0x00-0x16 as described in the BKDG. Zero
106 if (mc->mc_snapshot == NULL) in mc_snapshot_destroy()
109 kmem_free(mc->mc_snapshot, mc->mc_snapshotsz); in mc_snapshot_destroy()
110 mc->mc_snapshot = NULL; in mc_snapshot_destroy()
111 mc->mc_snapshotsz = 0; in mc_snapshot_destroy()
112 mc->mc_snapshotgen++; in mc_snapshot_destroy()
120 if (mc->mc_snapshot != NULL) in mc_snapshot_update()
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/illumos-gate/usr/src/uts/sun4u/io/
H A Denvctrl_targets.c35 #define EHC_FAILURE (-1)
65 * PCF8591 Chip Used for temperature sensors
68 * A0-A2 valid range is 0-7
70 * ------------------------------------------------
72 * ------------------------------------------------
89 * CONTROL OF CHIP
92 * ---------------------------------------------
94 * ---------------------------------------------
124 * Address map of this chip
126 * -------------------------------------------
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/illumos-gate/usr/src/uts/sun4u/io/px/
H A Dpx_lib4u.h71 /* IO chip type */
78 #define PX_CHIP_TYPE(pxu_p) ((pxu_p)->chip_type)
120 #define PX2CB(px_p) (((pxu_t *)px_p->px_plat_p)->px_cb_p)
130 uint64_t eq_rec_rsvd0 : 1, /* DW 0 - 63 */
131 eq_rec_fmt_type : 7, /* DW 0 - 62:56 */
132 eq_rec_len : 10, /* DW 0 - 55:46 */
133 eq_rec_addr0 : 14, /* DW 0 - 45:32 */
134 eq_rec_rid : 16, /* DW 0 - 31:16 */
135 eq_rec_data0 : 16; /* DW 0 - 15:00 */
136 uint64_t eq_rec_addr1 : 48, /* DW 1 - 63:16 */
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/illumos-gate/usr/src/uts/common/sys/
H A Dpcic_var.h137 #define PCS_CARD_16BIT 0x0080 /* set in 16-bit mode */
142 #define PCS_CARD_ISCARDBUS 0x1000 /* NJH - 32 bit (CARDBUS) card */
148 #define PCIC_MAX_SOCKETS 4 /* 2 per chip up to 2 chips per IO addr */
204 uint32_t pc_base; /* first possible mem-addr */
227 #define PCF_1SOCKET 0x00000100 /* Chip only has one socket */
230 #define PCF_DEBOUNCE 0x00002000 /* Chip has hardware debounce enabled */
232 #define PCF_EXTBUFF 0x00008000 /* Chip strapped for external buffers */
262 #define PCIC_INTR_MODE_ISA 00 /* default- use ISA mode */
332 * there are several variants of the 82365 chip from different "clone"
334 * handled. The following defines are used to identify the chip being
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H A Ddevfm.h43 #define FM_VERSIONS_VERSION "fm-versions-version"
44 #define FM_PAGE_OP_VERSION "page-operation-version"
45 #define FM_CPU_OP_VERSION "cpu-operation-version"
46 #define FM_CPU_INFO_VERSION "cpu-info-version"
47 #define FM_TOPO_LEGACY_VERSION "topo-legacy-version"
48 #define FM_CACHE_INFO_VERSION "cache-info-version"
117 * When Multi-Chip-Module(MCM) support is added
147 * topology modules can have more information than just the cache-id. While it's
150 * platform specific given that ARMv8-A/ARMv9-A doesn't define a way to get this
154 * appropriately. If a cache is fully-associative, we expects the number of sets
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/illumos-gate/usr/src/uts/intel/io/
H A Ddevfm_machdep.c38 #define ANY_ID (uint_t)-1
92 wp->chipid = chipid; in walk_init()
93 wp->coreid = coreid; in walk_init()
94 wp->strandid = strandid; in walk_init()
99 if ((wp->cbfunc = cbfunc) == NULL) { in walk_init()
100 wp->hdls = kmem_alloc(sizeof (cmi_hdl_t) * INIT_HDLS, KM_SLEEP); in walk_init()
101 wp->nhdl_max = INIT_HDLS; in walk_init()
102 wp->nhdl = 0; in walk_init()
109 if (wp->cbfunc == NULL) in walk_fini()
110 kmem_free(wp->hdls, sizeof (cmi_hdl_t) * wp->nhdl_max); in walk_fini()
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/illumos-gate/usr/src/uts/sun4u/lw2plus/io/
H A Dlombus.c28 * packet-based protocol over a serial link connected to one of the serial
29 * ports of the SuperIO (SIO) chip.
32 * registers signify - only the clients need this information.
69 #define HANDLE_ADDR(hdlp) (hdlp->ah_addr)
70 #define HANDLE_FAULT(hdlp) (hdlp->ah_fault)
71 #define HANDLE_MAPLEN(hdlp) (hdlp->ah_len)
72 #define HANDLE_PRIVATE(hdlp) (hdlp->ah_bus_private)
80 #define HANDLE_ADDR(hdlp) (hdlp->ahi_common.ah_addr)
81 #define HANDLE_FAULT(hdlp) (hdlp->ahi_fault)
82 #define HANDLE_MAPLEN(hdlp) (hdlp->ahi_common.ah_len)
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/illumos-gate/usr/src/man/man8/
H A Dcfgadm_usb.89 cfgadm_usb \- USB hardware-specific commands for cfgadm
12 \fB/usr/sbin/cfgadm\fR [\fB-f\fR] [\fB-y\fR | \fB-n\fR] [\fB-v\fR] \fB-c\fR \fIfunction\fR \fIap_id…
17 \fB/usr/sbin/cfgadm\fR \fB-f\fR [\fB-y\fR | \fB-n\fR] [\fB-v\fR] [\fB-o\fR \fIhardware_options\fR]
18 \fB-x\fR \fIhardware_function\fR \fIap_id\fR...
23 \fB/usr/sbin/cfgadm\fR \fB-v\fR [\fB-a\fR] [\fB-s\fR \fIlisting_option\fR]
24 [\fB-l\fR [\fIap_id\fR | \fIap_type\fR...]]
29 \fB/usr/sbin/cfgadm\fR \fB-v\fR \fB-h\fR [\fIap_id\fR]...
33 The Universal Serial Bus (\fBUSB\fR) hardware-specific library
111 example# \fBcfgadm -l\fR
113 usb0/1 USB-hub connected configured ok
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/illumos-gate/usr/src/uts/common/sys/fibre-channel/fca/emlxs/
H A Demlxs_adapters.h23 * Copyright (c) 2004-2012 Emulex. All rights reserved.
75 LPe1100X, /* Generic Multi Channel */
107 LPe1600X, /* Generic Multi Channel FC */
110 LPe16002_FC_SP1, /* Oracle excluded - Spare */
111 LPe16002_FC_SP2, /* Oracle excluded - Spare */
114 LPe31000_M6_L, /* Single port 16Gb, Lenovo-branded */
116 LPe3200X, /* Generic Multi Channel FC */
131 OCe1510X, /* Generic Multi Channel FCOE */
134 LPe16002_FE_SP1, /* Oracle excluded - Spare */
135 LPe16002_FE_SP2, /* Oracle excluded - Spare */
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/illumos-gate/usr/src/uts/intel/os/
H A Dcpuid.c54 * multi-processing (SMT), etc.
56 * ------------------------
58 * ------------------------
80 * AMD adds non-Intel compatible
104 * various extensions. For example, AMD-
122 * Some leaves are broken down into sub-leaves. This means that the value
124 * example, Intel uses the value in %ecx on leaf 7 to indicate a sub-leaf to get
130 * program is in 64-bit mode. When executing in 64-bit mode, the upper
134 * ----------------------
136 * ----------------------
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