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/linux/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v5_0_2.c57 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),
58 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),
59 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR),
60 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR),
61 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS),
62 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),
63 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),
64 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),
65 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE),
66 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),
[all …]
H A Djpeg_v5_0_1.c59 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),
60 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),
61 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR),
62 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR),
63 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS),
64 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),
65 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),
66 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),
67 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE),
68 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),
[all …]
H A Djpeg_v4_0_5.c50 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),
51 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),
52 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR),
53 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR),
54 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL),
55 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE),
56 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS),
57 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),
58 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),
59 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),
[all …]
H A Djpeg_v4_0_3.c63 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),
64 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),
65 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_SYS_INT_STATUS),
66 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR),
67 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR),
68 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS),
69 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),
70 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),
71 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),
72 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE),
[all …]
H A Djpeg_v5_0_0.c38 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),
39 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),
40 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR),
41 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR),
42 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL),
43 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE),
44 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS),
45 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),
46 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),
47 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),
[all …]
H A Djpeg_v3_0.c38 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS),
39 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT),
40 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR),
41 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR),
42 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL),
43 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE),
44 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS),
45 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE),
46 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG),
47 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE),
[all …]
H A Damdgpu_jpeg.c42 INIT_DELAYED_WORK(&adev->jpeg.idle_work, amdgpu_jpeg_idle_work_handler); in amdgpu_jpeg_sw_init()
43 mutex_init(&adev->jpeg.jpeg_pg_lock); in amdgpu_jpeg_sw_init()
44 atomic_set(&adev->jpeg.total_submission_cnt, 0); in amdgpu_jpeg_sw_init()
48 adev->jpeg.indirect_sram = true; in amdgpu_jpeg_sw_init()
50 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { in amdgpu_jpeg_sw_init()
51 if (adev->jpeg.harvest_config & (1U << i)) in amdgpu_jpeg_sw_init()
54 if (adev->jpeg.indirect_sram) { in amdgpu_jpeg_sw_init()
58 &adev->jpeg.inst[i].dpg_sram_bo, in amdgpu_jpeg_sw_init()
59 &adev->jpeg.inst[i].dpg_sram_gpu_addr, in amdgpu_jpeg_sw_init()
60 &adev->jpeg.inst[i].dpg_sram_cpu_addr); in amdgpu_jpeg_sw_init()
[all …]
H A Djpeg_v2_5.c40 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS),
41 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT),
42 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR),
43 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR),
44 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL),
45 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE),
46 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS),
47 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE),
48 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG),
49 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE),
[all …]
H A Djpeg_v5_3_0.c54 adev->jpeg.num_jpeg_inst = 1; in jpeg_v5_3_0_early_init()
55 adev->jpeg.num_jpeg_rings = 1; in jpeg_v5_3_0_early_init()
64 * jpeg_v5_3_0_sw_init - sw init for JPEG block
76 /* JPEG TRAP */ in jpeg_v5_3_0_sw_init()
78 VCN_5_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v5_3_0_sw_init()
90 ring = adev->jpeg.inst->ring_dec; in jpeg_v5_3_0_sw_init()
96 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v5_3_0_sw_init()
101 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; in jpeg_v5_3_0_sw_init()
102 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); in jpeg_v5_3_0_sw_init()
105 adev->jpeg.supported_reset = in jpeg_v5_3_0_sw_init()
[all …]
H A Djpeg_v4_0.c40 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),
41 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),
42 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR),
43 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR),
44 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL),
45 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE),
46 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS),
47 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),
48 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),
49 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),
[all …]
H A Djpeg_v2_0.c36 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS),
37 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT),
38 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR),
39 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR),
40 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL),
41 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE),
42 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS),
43 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE),
44 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG),
45 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE),
[all …]
/linux/drivers/media/platform/samsung/s5p-jpeg/
H A Djpeg-core.c2 /* linux/drivers/media/platform/samsung/s5p-jpeg/jpeg-core.c
31 #include "jpeg-core.h"
32 #include "jpeg-hw-s5p.h"
33 #include "jpeg-hw-exynos4.h"
34 #include "jpeg-hw-exynos3250.h"
35 #include "jpeg-regs.h"
590 switch (ctx->jpeg->variant->version) { in s5p_jpeg_to_user_subsampling()
767 struct s5p_jpeg *jpeg = ctx->jpeg; in exynos4_jpeg_parse_decode_h_tbl() local
799 exynos4_jpeg_select_dec_h_tbl(jpeg->regs, c, in exynos4_jpeg_parse_decode_h_tbl()
807 struct s5p_jpeg *jpeg = ctx->jpeg; in exynos4_jpeg_parse_huff_tbl() local
[all …]
H A Djpeg-regs.h2 /* linux/drivers/media/platform/samsung/s5p-jpeg/jpeg-regs.h
4 * Register definition file for Samsung JPEG codec driver
18 /* JPEG mode register */
29 /* JPEG operation status register */
45 /* JPEG restart interval register upper byte */
48 /* JPEG restart interval register lower byte */
51 /* JPEG vertical resolution register upper byte */
54 /* JPEG vertical resolution register lower byte */
57 /* JPEG horizontal resolution register upper byte */
60 /* JPEG horizontal resolution register lower byte */
[all …]
H A Djpeg-core.h2 /* linux/drivers/media/platform/samsung/s5p-jpeg/jpeg-core.h
14 #include <media/jpeg.h>
19 #define S5P_JPEG_M2M_NAME "s5p-jpeg"
23 /* JPEG compression quality setting */
27 /* JPEG RGB to YCbCr conversion matrix coefficients */
95 * struct s5p_jpeg - JPEG IP abstraction
102 * @regs: JPEG IP registers mapping
103 * @irq: JPEG IP irq
104 * @irq_ret: JPEG IP irq result value
105 * @clocks: JPEG IP clock(s)
[all …]
H A DMakefile2 s5p-jpeg-objs := jpeg-core.o jpeg-hw-exynos3250.o jpeg-hw-exynos4.o jpeg-hw-s5p.o
3 obj-$(CONFIG_VIDEO_SAMSUNG_S5P_JPEG) += s5p-jpeg.o
/linux/Documentation/devicetree/bindings/media/
H A Dimg,e5010-jpeg-enc.yaml4 $id: http://devicetree.org/schemas/media/img,e5010-jpeg-enc.yaml#
7 title: Imagination E5010 JPEG Encoder
13 The E5010 is a JPEG encoder from Imagination Technologies implemented on
15 inputs to JPEG and M-JPEG. It supports baseline JPEG Encoding up to
22 - const: ti,am62a-jpeg-enc
23 - const: img,e5010-jpeg-enc
24 - const: img,e5010-jpeg-enc
66 jpeg-encoder@fd20000 {
67 compatible = "img,e5010-jpeg-enc";
H A Drenesas,jpu.yaml7 title: Renesas JPEG Processing Unit
13 The JPEG processing unit (JPU) incorporates the JPEG codec with an encoding
14 and decoding function conforming to the JPEG baseline process, so that the
15 JPU can encode image data and decode JPEG data quickly.
58 jpeg-codec@fe980000 {
H A Dmediatek,mt8195-jpegenc.yaml7 title: MediaTek JPEG Encoder
13 MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs
42 The jpeg encoder hardware device node which should be added as subnodes to
43 the main jpeg node.
/linux/Documentation/userspace-api/media/v4l/
H A Dvidioc-g-jpegcomp.rst39 :ref:`JPEG class controls <jpeg-controls>` for image quality and JPEG
47 itself, and it'll be stored in the JPEG-encoded fields (eg; interlacing
52 and the restart interval information (all JPEG-specific stuff) should be
53 stored in the JPEG-encoded fields. These define how the JPEG field is
69 :ref:`V4L2_CID_JPEG_COMPRESSION_QUALITY <jpeg-quality-control>`
89 - See :ref:`jpeg-markers`. Deprecated. If
90 :ref:`V4L2_CID_JPEG_ACTIVE_MARKER <jpeg-active-marker-control>`
98 .. flat-table:: JPEG Markers Flags
H A Dpixfmt-reserved.rst61 - JPEG-Light format (Pegasus Lossless JPEG) used in Divio webcams NW
97 - JPEG compressed RGGB Bayer format used by the gspca driver.
102 - OV511 JPEG format used by the gspca driver.
107 - OV518 JPEG format used by the gspca driver.
112 - Pixart 73xx JPEG format used by the gspca driver.
205 contains interleaved JPEG and UYVY image data, followed by meta
207 actual pointer array follows immediately the interleaved JPEG/UYVY
211 The first plane can start either with JPEG or UYVY data chunk. The
213 multiplied by 2. The size of a JPEG chunk depends on the image and
225 In order to extract UYVY and JPEG frames an application can
[all …]
H A Dext-ctrls-jpeg.rst7 JPEG Control Reference
10 The JPEG class includes controls for common features of JPEG encoders
18 JPEG Control IDs
22 The JPEG class descriptor. Calling
83 Specify which JPEG markers are included in compressed stream. This
105 For more details about JPEG specification, refer to :ref:`itu-t81`,
106 :ref:`jfif`, :ref:`w3c-jpeg-jfif`.
/linux/drivers/media/platform/nxp/imx-jpeg/
H A Dmxc-jpeg-hw.c3 * i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver
10 #include "mxc-jpeg-hw.h"
23 dev_dbg(dev, " MXC JPEG NEXT_DESCPT_PTR 0x%x\n", in print_descriptor_info()
25 dev_dbg(dev, " MXC JPEG BUF_BASE0 0x%x\n", desc->buf_base0); in print_descriptor_info()
26 dev_dbg(dev, " MXC JPEG BUF_BASE1 0x%x\n", desc->buf_base1); in print_descriptor_info()
27 dev_dbg(dev, " MXC JPEG LINE_PITCH %d\n", desc->line_pitch); in print_descriptor_info()
28 dev_dbg(dev, " MXC JPEG STM_BUFBASE 0x%x\n", desc->stm_bufbase); in print_descriptor_info()
29 dev_dbg(dev, " MXC JPEG STM_BUFSIZE %d\n", desc->stm_bufsize); in print_descriptor_info()
30 dev_dbg(dev, " MXC JPEG IMGSIZE %x (%d x %d)\n", desc->imgsize, in print_descriptor_info()
32 dev_dbg(dev, " MXC JPEG STM_CTRL 0x%x\n", desc->stm_ctrl); in print_descriptor_info()
H A DMakefile2 mxc-jpeg-encdec-objs := mxc-jpeg-hw.o mxc-jpeg.o
3 obj-$(CONFIG_VIDEO_IMX8_JPEG) += mxc-jpeg-encdec.o
/linux/drivers/media/platform/mediatek/jpeg/
H A DMakefile3 mtk-jpeg-enc-hw.o \
4 mtk-jpeg-dec-hw.o
9 mtk-jpeg-enc-hw-y := mtk_jpeg_enc_hw.o
10 mtk-jpeg-dec-hw-y := mtk_jpeg_dec_hw.o
H A DKconfig3 tristate "Mediatek JPEG Codec driver"
12 Mediatek jpeg codec driver provides HW capability to decode
13 JPEG format
16 module will be called mtk-jpeg

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