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/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gmu.c20 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) in a6xx_gmu_fault() argument
22 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_fault()
27 gmu->hung = true; in a6xx_gmu_fault()
38 struct a6xx_gmu *gmu = data; in a6xx_gmu_irq() local
41 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); in a6xx_gmu_irq()
42 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); in a6xx_gmu_irq()
45 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); in a6xx_gmu_irq()
47 a6xx_gmu_fault(gmu); in a6xx_gmu_irq()
51 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); in a6xx_gmu_irq()
54 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", in a6xx_gmu_irq()
[all …]
H A Da6xx_gmu.h23 * These define the different GMU wake up options - these define how both the
24 * CPU and the GMU bring up the hardware
27 /* THe GMU has already been booted and the rentention registers are active */
30 /* the GMU is coming up for the first time or back from a power collapse */
34 * These define the level of control that the GMU has - the higher the number
35 * the more things that the GMU hardware controls on its own.
38 /* The GMU does not do any idle state management */
41 /* The GMU manages SPTP power collapse */
44 /* The GMU does automatic IFPC (intra-frame power collapse) */
50 /* For serializing communication with the GMU: */
[all …]
H A Da6xx_hfi.c28 static int a6xx_hfi_queue_read(struct a6xx_gmu *gmu, in a6xx_hfi_queue_read() argument
44 * If we are to assume that the GMU firmware is in fact a rational actor in a6xx_hfi_queue_read()
59 if (!gmu->legacy) in a6xx_hfi_queue_read()
66 static int a6xx_hfi_queue_write(struct a6xx_gmu *gmu, in a6xx_hfi_queue_write() argument
90 if (!gmu->legacy) { in a6xx_hfi_queue_write()
98 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01); in a6xx_hfi_queue_write()
102 static int a6xx_hfi_wait_for_ack(struct a6xx_gmu *gmu, u32 id, u32 seqnum, in a6xx_hfi_wait_for_ack() argument
105 struct a6xx_hfi_queue *queue = &gmu->queues[HFI_RESPONSE_QUEUE]; in a6xx_hfi_wait_for_ack()
110 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, in a6xx_hfi_wait_for_ack()
114 DRM_DEV_ERROR(gmu->dev, in a6xx_hfi_wait_for_ack()
[all …]
H A Da6xx_gpu.c24 /* Check that the GMU is idle */ in _a6xx_check_idle()
25 if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu)) in _a6xx_check_idle()
212 * For PM4 the GMU register offsets are calculated from the base of the in a6xx_submit()
412 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_set_hwcg() local
433 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, in a6xx_set_hwcg()
435 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, in a6xx_set_hwcg()
437 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, in a6xx_set_hwcg()
467 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); in a6xx_set_hwcg()
474 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); in a6xx_set_hwcg()
865 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in hw_init() local
[all …]
H A Da6xx_gpu.h37 struct a6xx_gmu gmu; member
100 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu);
102 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu);
104 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
105 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
H A Da6xx_gpu_state.c155 if (!a6xx_gmu_sptprac_is_on(&a6xx_gpu->gmu)) in a6xx_crashdumper_run()
1172 /* Read a block of GMU registers */
1181 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in _a6xx_get_gmu_registers() local
1201 val = gmu_read_rscc(gmu, offset); in _a6xx_get_gmu_registers()
1203 val = gmu_read(gmu, offset); in _a6xx_get_gmu_registers()
1224 /* Get the CX GMU registers from AHB */ in a6xx_get_gmu_registers()
1230 if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) in a6xx_get_gmu_registers()
1268 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_snapshot_gmu_hfi_history() local
1271 BUILD_BUG_ON(ARRAY_SIZE(gmu->queues) != ARRAY_SIZE(a6xx_state->hfi_queue_history)); in a6xx_snapshot_gmu_hfi_history()
1273 for (i = 0; i < ARRAY_SIZE(gmu->queues); i++) { in a6xx_snapshot_gmu_hfi_history()
[all …]
H A Da6xx_hfi.h49 /* This is the outgoing queue to the GMU */
52 /* THis is the incoming response queue from the GMU */
H A Da6xx_gpu_state.h345 /* GMU GX */
354 /* GMU CX */
364 /* GMU AO */
H A Dadreno_gpu.c536 /* Skip loading GMU firwmare with GMU Wrapper */ in adreno_load_fw()
1092 /* Only handle the core clock when GMU is not in use (or is absent). */ in adreno_gpu_init()
/linux/Documentation/devicetree/bindings/display/msm/
H A Dgmu.yaml6 $id: http://devicetree.org/schemas/display/msm/gmu.yaml#
9 title: GMU attached to certain Adreno GPUs
15 These bindings describe the Graphics Management Unit (GMU) that is attached
16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
24 - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'
25 - const: qcom,adreno-gmu
27 - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
28 - const: qcom,adreno-gmu
29 - const: qcom,adreno-gmu-wrapper
49 - description: GMU HFI interrupt
[all …]
H A Dgpu.yaml130 qcom,gmu:
133 For GMU attached devices a phandle to the GMU device that will
206 - const: gmu
207 description: CX GMU clock
227 then: # Starting with A6xx, the clocks are usually defined in the GMU node
291 // Example a6xx (with GMU):
328 qcom,gmu = <&gmu>;
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8992.dtsi31 gmu-sram@0 {
H A Dsm6350.dtsi1362 qcom,gmu = <&gmu>;
1446 gmu: gmu@3d6a000 { label
1447 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
1451 reg-names = "gmu",
1458 "gmu";
1466 "gmu",
H A Dqcm2290.dtsi1451 "gmu",
1462 qcom,gmu = <&gmu_wrapper>;
1531 gmu_wrapper: gmu@596a000 {
1532 compatible = "qcom,adreno-gmu-wrapper";
1534 reg-names = "gmu";
H A Dsm8350.dtsi1909 qcom,gmu = <&gmu>;
1974 gmu: gmu@3d6a000 { label
1975 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
1980 reg-names = "gmu", "rscc", "gmu_pdc";
1984 interrupt-names = "hfi", "gmu";
1993 clock-names = "gmu",
H A Dsc8180x.dtsi2277 qcom,gmu = <&gmu>;
2322 gmu: gmu@2c6a000 { label
2323 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2328 reg-names = "gmu",
2334 interrupt-names = "hfi", "gmu";
2341 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
H A Dsm6115.dtsi1694 /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */
1705 "gmu",
1713 qcom,gmu = <&gmu_wrapper>;
1779 gmu_wrapper: gmu@596a000 {
1780 compatible = "qcom,adreno-gmu-wrapper";
1782 reg-names = "gmu";
H A Dsc7180.dtsi2174 qcom,gmu = <&gmu>;
2268 gmu: gmu@506a000 { label
2269 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2272 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2275 interrupt-names = "hfi", "gmu";
2280 clock-names = "gmu", "cxo", "axi", "memnoc";
H A Dsm8150.dtsi2253 qcom,gmu = <&gmu>;
2306 gmu: gmu@2c6a000 { label
2307 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2312 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2316 interrupt-names = "hfi", "gmu";
2323 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
H A Dsdm845.dtsi4839 * controlled entirely by the GMU
4848 qcom,gmu = <&gmu>;
4925 gmu: gmu@506a000 { label
4926 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4931 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4935 interrupt-names = "hfi", "gmu";
4941 clock-names = "gmu", "cxo", "axi", "memnoc";
H A Dsm8450.dtsi2179 qcom,gmu = <&gmu>;
2253 gmu: gmu@3d6a000 { label
2254 compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu";
2258 reg-names = "gmu", "rscc", "gmu_pdc";
2262 interrupt-names = "hfi", "gmu";
2272 "gmu",
2354 clock-names = "gmu",
H A Dsm8150-mtp.dts353 &gmu {
/linux/drivers/clk/qcom/
H A Dgdsc.c586 * On SDM845+ the GPU GX domain is *almost* entirely controlled by the GMU
591 * the GMU crashes it could leave the GX on. In order to successfully bring back
600 * driver. During power up, nothing will happen from the CPU (and the GMU will
/linux/Documentation/devicetree/bindings/sram/
H A Dqcom,ocmem.yaml120 gmu-sram@0 {
/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu.yaml506 - const: gmu
515 - description: GMU clock

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