Searched full:en1 (Results 1 – 13 of 13) sorted by relevance
40 (EN0, EN1), and 3 master sequencing timers called FPS0, FPS1 and FPS2.42 register to have a hardware enable source (EN1 or EN2) or a software enable79 hardware input to PMIC i.e. EN0, EN1 or87 for hardware input pin EN1.
36 tsp_en1_default_state: tsp-en1-default-state {
86 tsp_en1_default_state: tsp-en1-default-state {
551 tsp_en1_default_state: tsp-en1-default-state {
93 * MUX can program the pin to be in EN1/2/3 pin mode in lp87565_gpio_request()
655 struct extent_node *en = NULL, *en1 = NULL; in __update_extent_tree_range() local706 next_en = en1 = NULL; in __update_extent_tree_range()729 en1 = __insert_extent_tree(sbi, et, &ei, in __update_extent_tree_range()731 next_en = en1; in __update_extent_tree_range()
830 * Regulator can not be control from multiple external input EN1, EN2 in tps65910_set_ext_sleep_config()852 /* External EN1 control */ in tps65910_set_ext_sleep_config()861 "Error in configuring external control EN1\n"); in tps65910_set_ext_sleep_config()
539 usb2phy_ac_en1_default: usb2phy-ac-en1-default-state {
845 /* External sleep controls through EN1/EN2/EN3/SLEEP inputs */
207 usb-vbus-en1-pn5 {
704 usb-vbus-en1-pn5 {
1080 int coreid = data->irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ in octeon_irq_ciu_wd_enable()
3327 Field 1 EN1