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/linux/drivers/memory/tegra/
H A Dtegra20-emc.c216 * There are multiple sources in the EMC driver which could request
237 struct tegra_emc *emc = data; in tegra20_emc_isr() local
241 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra20_emc_isr()
247 dev_err_ratelimited(emc->dev, in tegra20_emc_isr()
251 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra20_emc_isr()
256 static struct emc_timing *tegra20_emc_find_timing(struct tegra_emc *emc, in tegra20_emc_find_timing() argument
262 for (i = 0; i < emc->num_timings; i++) { in tegra20_emc_find_timing()
263 if (emc->timings[i].rate >= rate) { in tegra20_emc_find_timing()
264 timing = &emc->timings[i]; in tegra20_emc_find_timing()
270 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra20_emc_find_timing()
[all …]
H A Dtegra210-emc-core.c21 #include "tegra210-emc.h"
69 next->trim_perch_regs[EMC ## chan ## \
561 struct tegra210_emc *emc = timer_container_of(emc, timer, training); in tegra210_emc_train() local
564 if (!emc->last) in tegra210_emc_train()
567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train()
569 if (emc->sequence->periodic_compensation) in tegra210_emc_train()
570 emc->sequence->periodic_compensation(emc); in tegra210_emc_train()
572 spin_unlock_irqrestore(&emc->lock, flags); in tegra210_emc_train()
574 mod_timer(&emc->training, in tegra210_emc_train()
575 jiffies + msecs_to_jiffies(emc->training_interval)); in tegra210_emc_train()
[all …]
H A Dtegra210-emc-cc-r21021.c14 #include "tegra210-emc.h"
36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__) argument
108 emc_dbg(emc, EMA_UPDATES, "%s: (s=%u) EMA: %u\n", \
133 static void tegra210_emc_get_clktree_delay(struct tegra210_emc *emc, in tegra210_emc_get_clktree_delay() argument
136 struct tegra210_emc_timing *curr = emc->last; in tegra210_emc_get_clktree_delay()
145 tegra210_emc_start_periodic_compensation(emc); in tegra210_emc_get_clktree_delay()
148 for (d = 0; d < emc->num_devices; d++) { in tegra210_emc_get_clktree_delay()
150 msb = tegra210_emc_mrr_read(emc, 2 - d, 19); in tegra210_emc_get_clktree_delay()
151 lsb = tegra210_emc_mrr_read(emc, 2 - d, 18); in tegra210_emc_get_clktree_delay()
153 for (c = 0; c < emc->num_channels; c++) { in tegra210_emc_get_clktree_delay()
[all …]
H A DMakefile17 obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o
18 obj-$(CONFIG_TEGRA30_EMC) += tegra30-emc.o
19 obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
20 obj-$(CONFIG_TEGRA210_EMC_TABLE) += tegra210-emc-table.o
21 obj-$(CONFIG_TEGRA210_EMC) += tegra210-emc.o
22 obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-emc.o
23 obj-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186-emc.o
24 obj-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra186-emc.o
25 obj-$(CONFIG_ARCH_TEGRA_264_SOC) += tegra186-emc.o
27 tegra210-emc-y := tegra210-emc-core.o tegra210-emc-cc-r21021.o
H A DKconfig21 This driver is for the External Memory Controller (EMC) found on
22 Tegra20 chips. The EMC controls the external DRAM on the board.
33 This driver is for the External Memory Controller (EMC) found on
34 Tegra30 chips. The EMC controls the external DRAM on the board.
45 This driver is for the External Memory Controller (EMC) found on
46 Tegra124 chips. The EMC controls the external DRAM on the board.
59 This driver is for the External Memory Controller (EMC) found on
60 Tegra210 chips. The EMC controls the external DRAM on the board.
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-jetson-tk1-emc.dtsi7 emc-timings-3 {
14 clock-names = "emc-parent";
21 clock-names = "emc-parent";
28 clock-names = "emc-parent";
35 clock-names = "emc-parent";
42 clock-names = "emc-parent";
49 clock-names = "emc-parent";
56 clock-names = "emc-parent";
63 clock-names = "emc-parent";
70 clock-names = "emc-parent";
[all …]
H A Dtegra124-apalis-emc.dtsi11 emc-timings-1 {
18 clock-names = "emc-parent";
25 clock-names = "emc-parent";
32 clock-names = "emc-parent";
39 clock-names = "emc-parent";
46 clock-names = "emc-parent";
53 clock-names = "emc-parent";
60 clock-names = "emc-parent";
67 clock-names = "emc-parent";
74 clock-names = "emc-parent";
[all …]
H A Dtegra124-nyan-blaze-emc.dtsi7 emc-timings-1 {
14 clock-names = "emc-parent";
21 clock-names = "emc-parent";
28 clock-names = "emc-parent";
35 clock-names = "emc-parent";
42 clock-names = "emc-parent";
49 clock-names = "emc-parent";
56 clock-names = "emc-parent";
63 clock-names = "emc-parent";
72 clock-names = "emc-parent";
[all …]
H A Dtegra30-asus-tf300t.dts146 emc-timings-0 {
211 emc-timings-1 {
276 emc-timings-2 {
343 emc-timings-0 {
350 nvidia,emc-auto-cal-interval = <0x001fffff>;
351 nvidia,emc-mode-1 = <0x80100003>;
352 nvidia,emc-mode-2 = <0x80200008>;
353 nvidia,emc-mode-reset = <0x80001221>;
354 nvidia,emc-zcal-cnt-long = <0x00000040>;
355 nvidia,emc-cfg-dyn-self-ref;
[all …]
H A Dtegra30-asus-tf300tg.dts220 emc-timings-0 {
285 emc-timings-1 {
350 emc-timings-2 {
417 emc-timings-0 {
424 nvidia,emc-auto-cal-interval = <0x001fffff>;
425 nvidia,emc-mode-1 = <0x80100003>;
426 nvidia,emc-mode-2 = <0x80200048>;
427 nvidia,emc-mode-reset = <0x80001221>;
428 nvidia,emc-zcal-cnt-long = <0x00000040>;
429 nvidia,emc-cfg-dyn-self-ref;
[all …]
H A Dtegra30-asus-tf700t.dts141 emc-timings-0 {
206 emc-timings-1 {
273 emc-timings-0 {
280 nvidia,emc-auto-cal-interval = <0x001fffff>;
281 nvidia,emc-mode-1 = <0x80100003>;
282 nvidia,emc-mode-2 = <0x80200008>;
283 nvidia,emc-mode-reset = <0x80001221>;
284 nvidia,emc-zcal-cnt-long = <0x00000040>;
285 nvidia,emc-cfg-dyn-self-ref;
286 nvidia,emc-cfg-periodic-qrst;
[all …]
H A Dtegra30-asus-tf201.dts112 emc-timings-0 {
167 emc-timings-1 {
224 emc-timings-0 {
231 nvidia,emc-auto-cal-interval = <0x001fffff>;
232 nvidia,emc-mode-1 = <0x00010022>;
233 nvidia,emc-mode-2 = <0x00020001>;
234 nvidia,emc-mode-reset = <0x00000000>;
235 nvidia,emc-zcal-cnt-long = <0x00000009>;
236 nvidia,emc-cfg-periodic-qrst;
238 nvidia,emc-configuration = < 0x00000001
[all …]
H A Dtegra30-asus-tf300tl.dts240 emc-timings-0 {
305 emc-timings-1 {
372 emc-timings-0 {
379 nvidia,emc-auto-cal-interval = <0x001fffff>;
380 nvidia,emc-mode-1 = <0x80100003>;
381 nvidia,emc-mode-2 = <0x80200048>;
382 nvidia,emc-mode-reset = <0x80001221>;
383 nvidia,emc-zcal-cnt-long = <0x00000040>;
384 nvidia,emc-cfg-dyn-self-ref;
385 nvidia,emc-cfg-periodic-qrst;
[all …]
H A Dtegra124-nyan-big-emc.dtsi7 emc-timings-1 {
14 clock-names = "emc-parent";
21 clock-names = "emc-parent";
28 clock-names = "emc-parent";
35 clock-names = "emc-parent";
42 clock-names = "emc-parent";
49 clock-names = "emc-parent";
56 clock-names = "emc-parent";
63 clock-names = "emc-parent";
70 clock-names = "emc-parent";
[all …]
H A Dtegra124-xiaomi-mocha.dts105 emc-timings-0 {
112 clock-names = "emc-parent";
119 clock-names = "emc-parent";
126 clock-names = "emc-parent";
133 clock-names = "emc-parent";
140 clock-names = "emc-parent";
147 clock-names = "emc-parent";
154 clock-names = "emc-parent";
161 clock-names = "emc-parent";
168 clock-names = "emc-parent";
[all …]
H A Dtegra30-pegatron-chagall.dts1543 emc-timings-0 {
1598 emc-timings-1 {
1653 emc-timings-2 {
1708 emc-timings-3 {
1765 emc-timings-0 {
1772 nvidia,emc-auto-cal-interval = <0x001fffff>;
1773 nvidia,emc-mode-1 = <0x00010022>;
1774 nvidia,emc-mode-2 = <0x00020001>;
1775 nvidia,emc-mode-reset = <0x00000000>;
1776 nvidia,emc-zcal-cnt-long = <0x00000009>;
[all …]
H A Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
159 emc-timings-1 {
315 emc-timings-0 {
321 nvidia,emc-auto-cal-interval = <0x001fffff>;
322 nvidia,emc-mode-1 = <0x80100003>;
323 nvidia,emc-mode-2 = <0x80200008>;
324 nvidia,emc-mode-reset = <0x80001221>;
325 nvidia,emc-zcal-cnt-long = <0x00000040>;
326 nvidia,emc-cfg-dyn-self-ref;
327 nvidia,emc-cfg-periodic-qrst;
[all …]
H A Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi13 emc-timings-0 {
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
21 nvidia,emc-zcal-cnt-long = <0x00000040>;
22 nvidia,emc-cfg-periodic-qrst;
24 nvidia,emc-configuration = <
118 emc-timings-1 {
122 nvidia,emc-auto-cal-interval = <0x001fffff>;
[all …]
H A Dtegra20-acer-a500-picasso.dts705 emc-tables@0 {
712 emc-table@25000 {
714 compatible = "nvidia,tegra20-emc-table";
716 nvidia,emc-registers = <0x00000002 0x00000006
730 emc-table@50000 {
732 compatible = "nvidia,tegra20-emc-table";
734 nvidia,emc-registers = <0x00000003 0x00000007
748 emc-table@75000 {
750 compatible = "nvidia,tegra20-emc-table";
752 nvidia,emc-registers = <0x00000005 0x0000000a
[all …]
/linux/drivers/clk/tegra/
H A Dclk-tegra20-emc.c3 * Based on drivers/clk/tegra/clk-emc.c
10 #define pr_fmt(fmt) "tegra-emc-clk: " fmt
57 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_recalc_rate() local
60 val = readl_relaxed(emc->reg); in emc_recalc_rate()
68 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_get_parent() local
70 return readl_relaxed(emc->reg) >> CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT; in emc_get_parent()
75 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_set_parent() local
78 val = readl_relaxed(emc->reg); in emc_set_parent()
84 if (index == EMC_SRC_PLL_M && div == 0 && emc->want_low_jitter) in emc_set_parent()
89 if (emc->mc_same_freq) in emc_set_parent()
[all …]
H A Dclk-tegra210-emc.c53 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_get_parent() local
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
66 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_recalc_rate() local
74 * This can lead to wrong results being reported for the EMC clock if in tegra210_clk_emc_recalc_rate()
75 * the parent and/or parent rate have changed as part of the EMC rate in tegra210_clk_emc_recalc_rate()
81 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_recalc_rate()
92 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_determine_rate() local
93 struct tegra210_clk_emc_provider *provider = emc->provider; in tegra210_clk_emc_determine_rate()
115 static struct clk *tegra210_clk_emc_find_parent(struct tegra210_clk_emc *emc, in tegra210_clk_emc_find_parent() argument
118 struct clk_hw *parent = clk_hw_get_parent_by_index(&emc->hw, index); in tegra210_clk_emc_find_parent()
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra124-emc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
30 - const: emc
51 "^emc-timings-[0-9]+$":
71 nvidia,emc-auto-cal-config:
77 nvidia,emc-auto-cal-config2:
83 nvidia,emc-auto-cal-config3:
89 nvidia,emc-auto-cal-interval:
96 nvidia,emc-bgbias-ctl0:
[all …]
H A Dnvidia,tegra30-emc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
23 const: nvidia,tegra30-emc
53 "^emc-timings-[0-9]+$":
71 nvidia,emc-auto-cal-interval:
78 nvidia,emc-mode-1:
83 nvidia,emc-mode-2:
88 nvidia,emc-mode-reset:
[all …]
H A Dnvidia,tegra20-emc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
16 service the request stream sent from Memory Controller. The EMC also has
18 parameters and initialization settings. Tegra20 EMC supports multiple JEDEC
23 const: nvidia,tegra20-emc
61 If present, the emc-tables@ sub-nodes will be addressed.
64 emc-table:
68 const: nvidia,tegra20-emc-table
82 nvidia,emc-registers:
84 EMC timing characterization data. These are the registers
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-lpc18xx.c142 [FUNC_EMC] = "emc",
242 LPC_P(1,0, GPIO, CTIN, EMC, R, R, SSP0, SGPIO, R, 0, ND);
243 LPC_P(1,1, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
244 LPC_P(1,2, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
245 LPC_P(1,3, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
246 LPC_P(1,4, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
247 LPC_P(1,5, GPIO, CTOUT, R, EMC, USB0, SSP1, SGPIO, SDMMC, 0, ND);
248 LPC_P(1,6, GPIO, CTIN, R, EMC, R, R, SGPIO, SDMMC, 0, ND);
249 LPC_P(1,7, GPIO, UART1, CTOUT, EMC, USB0, R, R, R, 0, ND);
250 LPC_P(1,8, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
[all …]

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