| /freebsd/sys/contrib/device-tree/Bindings/display/panel/ |
| H A D | advantech,idk-2121wr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/advantech,idk-212
[all...] |
| H A D | panel-common-dual.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-common-dual.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Dual-Link Display Panels
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 Properties common for Panel IC supporting dual link panels. Devices might
15 support also single link.
18 - $ref: panel-common.yaml#
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| H A D | sharp,lq101r1sx01.txt | 3 This panel requires a dual-channel DSI host to operate. It supports two modes:
4 - left-right: each channel drives the left or right half of the screen
5 - even-odd: each channel drives the even or odd lines of the screen
8 driven by the first link (DSI-LINK1), left or even, is considered the primary
10 to the peripheral driven by the second link (DSI-LINK2, right or odd).
12 Note that in video mode the DSI-LINK1 interface always provides the left/even
13 pixels and DSI-LINK2 always provides the right/odd pixels. In command mode it
14 is possible to program either link to drive the left/even or right/odd pixels
19 - compatible: should be "sharp,lq101r1sx01"
20 - reg: DSI virtual channel of the peripheral
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| H A D | sharp,lq101r1sx01.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <treding@nvidia.com>
13 This panel requires a dual-channel DSI host to operate. It supports two modes:
14 - left-right: each channel drives the left or right half of the screen
15 - even-odd: each channel drives the even or odd lines of the screen
18 driven by the first link (DSI-LINK1), left or even, is considered the primary
20 to the peripheral driven by the second link (DSI-LINK2, right or odd).
22 Note that in video mode the DSI-LINK1 interface always provides the left/even
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| H A D | jdi,lpm102a188a.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
13 This panel requires a dual-channel DSI host to operate. It supports two modes:
14 - left-right: each channel drives the left or right half of the screen
15 - even-odd: each channel drives the even or odd lines of the screen
18 driven by the first link (DSI-LINK1) is considered the primary peripheral
20 peripheral driven by the second link (DSI-LINK2).
23 - $ref: panel-common.yaml#
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| /freebsd/sys/contrib/device-tree/Bindings/display/connector/ |
| H A D | dvi-connector.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/connector/dvi-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
14 const: dvi-connector
18 hpd-gpios:
22 ddc-i2c-bus:
23 description: phandle link to the I2C controller used for DDC EDID probing
34 dual-link:
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| H A D | dvi-connector.txt | 5 - compatible: "dvi-connector"
8 - label: a symbolic name for the connector
9 - ddc-i2c-bus: phandle to the i2c bus that is connected to DVI DDC
10 - analog: the connector has DVI analog pins
11 - digital: the connector has DVI digital pins
12 - dual-link: the connector has pins for DVI dual-link
13 - hpd-gpios: HPD GPIO number
16 - Video port for DVI input
21 -------
24 compatible = "dvi-connector";
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| /freebsd/sys/contrib/device-tree/Bindings/display/bridge/ |
| H A D | toshiba,tc358775.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinay Simha BN <simhavcs@gmail.com>
15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
25 - toshiba,tc358765
26 - toshiba,tc358775
32 vdd-supply:
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| H A D | thine,thc63lvd1024.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS
15 streams to parallel data outputs. The chip supports single/dual input/output
19 Single or dual operation mode, output data mapping and DDR output modes are
30 The device can operate in single or dual input and output modes.
33 and port@1 shall not contain any endpoint. In dual input mode,
[all …]
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| H A D | lontium,lt9211.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
13 The LT9211 are bridge devices which convert Single/Dual-Link DSI/LVDS
14 or Single DPI to Single/Dual-Link DSI/LVDS or Single DPI.
19 - lontium,lt9211
27 reset-gpios:
31 vccio-supply:
41 Primary MIPI DSI port-1 for MIPI input or
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| H A D | fsl,imx8qxp-ldb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
23 LDB split mode to support a dual link LVDS display. The channel indexes
29 in dual mode or split mode. In dual mode, the two channels output identical
41 - fsl,imx8qm-ldb
42 - fsl,imx8qxp-ldb
44 "#address-cells":
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| H A D | ti,sn65dsi83.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
14 to 1x Single-link LVDS
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
17 to 1x Dual-link or 2x Single-link LVDS
23 - ti,sn65dsi83
24 - ti,sn65dsi84
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| /freebsd/share/man/man4/ |
| H A D | sk.4 | 15 .\" 4. Neither the name of the author nor the names of any co-contributors
36 .Nd "SysKonnect SK-984x and SK-982x PCI Gigabit Ethernet adapter driver"
41 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
55 driver provides support for the SysKonnect SK-984x and SK-982x series PCI
65 allowing dual-port NIC configurations.
67 The SK-982x 1000baseT adapters also include a Broadcom BCM5400 1000baseTX
73 driver configures dual port SysKonnect adapters such that each XMAC
79 second port on dual port adapters for failover purposes: if the link
98 .Bl -tag -width xxxxxxxxxxxxxxxxxxxx
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| H A D | run.4 | 1 .\"-
2 .\" SPDX-License-Identifier: ISC
30 .Bd -ragged -offset indent
41 .Bd -ragged -offset indent
48 .Bd -literal -offset indent
59 an RT2720 (1T2R) or RT2750 (dual-band 1T2R) radio transceiver.
62 an RT2820 (2T3R) or RT2850 (dual-band 2T3R) radio transceiver.
64 The RT3000U is a single-chip solution based on an RT3070 MAC/BBP and
65 an RT3020 (1T1R), RT3021 (1T2R) or RT3022 (2T2R) single-band radio
68 The RT3900E is a single-chip USB 2.0 802.11n solution.
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| H A D | uath.4 | 2 .\" SPDX-License-Identifier: ISC
29 .Bd -ragged -offset indent
41 .Bd -literal -offset indent
51 and an AR2112 Radio-on-a-Chip that can operate between 2300 and 2500 MHz
55 and an AR5112 dual band Radio-on-a-Chip that can operate between 2300 and
58 The AR5005UG and AR5005UX chipsets both have an integrated 32-bit MIPS
59 R4000-class processor that runs a firmware and manages, among other things,
86 .Bl -column "TRENDware International TEW-444UB" "AR5005UX"
91 .\".It Li "D-Link DWL-AG132" Ta AR5005UX
92 .It Li "D-Link DWL-G132" Ta AR5005UG
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| /freebsd/share/misc/ |
| H A D | pci_vendors | 5 # Date: 2024-11-25 03:15:02
8 # the PCI ID Project at https://pci-ids.ucw.cz/.
14 # (version 2 or higher) or the 3-clause BSD License.
25 # device device_name <-- single tab
26 # subvendor subdevice subsystem_name <-- two tabs
30 # This is a relabelled RTL-8139
31 8139 AT-2500TX V3 Ethernet
41 7a09 PCI-to-PCI Bridge
50 7a19 PCI-to-PCI Bridge
55 7a29 PCI-to-PCI Bridge
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| /freebsd/sys/contrib/device-tree/Bindings/connector/ |
| H A D | usb-connector.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/connector/usb-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ro
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| /freebsd/sys/contrib/device-tree/Bindings/display/msm/ |
| H A D | dsi.txt | 5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
25 - assigned-clocks: Parents of "byte" and "pixel" for the given platform.
26 - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
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| /freebsd/sys/dev/e1000/ |
| H A D | README | 9 - Overview
10 - Identifying Your Adapter
11 - Building and Installation
12 - Additional Features and Configurations
13 - Known Issues/Troubleshooting
14 - Support
15 - License
21 been developed for use with all community-supported versions of FreeBSD.
33 - The igb driver supports all 82575 and 82576-based gigabit network connections.
34 - The em driver supports all other gigabit network connections.
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| /freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
| H A D | x1e80100-qcp.dts | 1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
12 #include "x1e80100-pmics.dtsi"
16 compatible = "qcom,x1e80100-qcp", "qcom,x1e80100";
22 wcd938x: audio-codec {
23 compatible = "qcom,wcd9385-codec";
25 pinctrl-names = "default";
26 pinctrl-0 = <&wcd_default>;
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| H A D | x1e80100-lenovo-yoga-slim7x.dts | 1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
12 #include "x1e80100-pmics.dtsi"
16 compatible = "lenovo,yoga-slim7x", "qcom,x1e80100";
18 pmic-glink {
19 compatible = "qcom,x1e80100-pmic-glink",
20 "qcom,sm8550-pmic-glink",
21 "qcom,pmic-glink";
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| H A D | x1e80100-crd.dts | 1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/gpio-keys.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
14 #include "x1e80100-pmics.dtsi"
18 compatible = "qcom,x1e80100-crd", "qcom,x1e80100";
24 wcd938x: audio-codec {
25 compatible = "qcom,wcd9385-codec";
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/display/imx/ |
| H A D | ldb.txt | 1 Device-Tree bindings for LVDS Display Bridge (ldb)
6 The LVDS Display Bridge device tree node contains up to two lvds-channel
10 - #address-cells : should be <1>
11 - #size-cells : should be <0>
12 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
16 - gpr : should be <&gpr> on i.MX53 and i.MX6q.
17 The phandle points to the iomuxc-gpr region containing the LVDS
19 - clocks, clock-names : phandles to the LDB divider and selector clocks and to
21 Documentation/devicetree/bindings/clock/clock-bindings.txt
23 "di0_pll" - LDB LVDS channel 0 mux
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| /freebsd/sys/contrib/device-tree/src/arm64/ti/ |
| H A D | k3-j784s4-evm-usxgmii-exp1-exp2.dtso | 1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
3 * DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1
4 * and ENET-2 Expansion slots of J784S4 EVM.
6 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/phy/phy-cadence.h>
14 #include <dt-bindings/phy/phy.h>
16 #include "k3-serdes.h"
20 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
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| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | st,stm32mp25-lvds.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32mp25-lvds.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
15 LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC)
19 - LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input
21 - LVDS PHY: parallelize the data and drives the LVDS data lanes
22 - LVDS wrapper: handles top-level settings
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