| /linux/Documentation/devicetree/bindings/ptp/ |
| H A D | brcm,ptp-dte.txt | 1 * Broadcom Digital Timing Engine(DTE) based PTP clock
9 "brcm,ptp-dte"
11 "brcm,iproc-ptp-dte" - for iproc based SoC's
12 - reg: address and length of the DTE block's NCO registers
16 ptp: ptp-dte@180af650 {
17 compatible = "brcm,iproc-ptp-dte", "brcm,ptp-dte";
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| /linux/drivers/iommu/ |
| H A D | rockchip-iommu.c | 100 phys_addr_t (*pt_address)(u32 dte);
161 * | DTE | -> +-----+
175 * Each DTE has a PT address and a valid bit:
186 static inline phys_addr_t rk_dte_pt_address(u32 dte) in rk_dte_pt_address() argument
188 return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK; in rk_dte_pt_address()
207 static inline phys_addr_t rk_dte_pt_address_v2(u32 dte) in rk_dte_pt_address_v2() argument
209 u64 dte_v2 = dte; in rk_dte_pt_address_v2()
218 static inline bool rk_dte_is_pt_valid(u32 dte) in rk_dte_is_pt_valid() argument
220 return dte & RK_DTE_PT_VALID; in rk_dte_is_pt_valid()
308 * | DTE index | PTE index | Page offset |
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| H A D | sun50i-iommu.c | 152 * 4096 4-bytes Directory Table Entries (DTE), each pointing to a Page
197 static phys_addr_t sun50i_dte_get_pt_address(u32 dte) in sun50i_dte_get_pt_address() argument
199 return (phys_addr_t)dte & SUN50I_DTE_PT_ADDRESS_MASK; in sun50i_dte_get_pt_address()
202 static bool sun50i_dte_is_pt_valid(u32 dte) in sun50i_dte_is_pt_valid() argument
204 return (dte & SUN50I_DTE_PT_ATTRS) == SUN50I_DTE_PT_VALID; in sun50i_dte_is_pt_valid()
563 u32 dte; in sun50i_dte_get_page_table() local
566 dte = *dte_addr; in sun50i_dte_get_page_table()
567 if (sun50i_dte_is_pt_valid(dte)) { in sun50i_dte_get_page_table()
568 phys_addr_t pt_phys = sun50i_dte_get_pt_address(dte); in sun50i_dte_get_page_table()
576 dte = sun50i_mk_dte(virt_to_phys(page_table)); in sun50i_dte_get_page_table()
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| /linux/net/x25/ |
| H A D | x25_facilities.c | 32 * @dte_facs: ITU DTE facilities, updated as DTE facilities are found
266 struct x25_facilities *new, struct x25_dte_facilities *dte) in x25_negotiate_facilities() argument
275 memset(dte, 0, sizeof(*dte)); in x25_negotiate_facilities()
277 len = x25_parse_facilities(skb, &theirs, dte, &x25->vc_facil_mask); in x25_negotiate_facilities()
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| /linux/drivers/ptp/ |
| H A D | ptp_dte.c | 40 /* ptp dte priv structure */
218 .name = "DTE PTP timer",
318 { .compatible = "brcm,ptp-dte", },
325 .name = "ptp-dte",
335 MODULE_DESCRIPTION("Broadcom DTE PTP Clock driver");
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| H A D | Kconfig | 43 tristate "Broadcom DTE as PTP clock"
50 (DTE) in the Broadcom SoC's as a PTP clock.
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| /linux/Documentation/devicetree/bindings/serial/ |
| H A D | fsl-imx-uart.yaml | 75 fsl,dte-mode:
78 Indicate the uart works in DTE mode. The uart works in DCE mode by default.
152 fsl,dte-mode;
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-class-led-trigger-tty | 29 DCE is ready to accept data from the DTE.
49 DTE is receiving a carrier from the DCE.
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| /linux/include/uapi/linux/ |
| H A D | x25.h | 67 * DTE/DCE subscription options.
111 * ITU DTE facilities
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| H A D | atmsap.h | 36 #define ATM_L2_ISO7776 0x11 /* ISO 7776 DTE-DTE */
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| /linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx6qdl-apalis.dtsi | 812 fsl,dte-mode;
820 fsl,dte-mode;
828 fsl,dte-mode;
835 fsl,dte-mode;
1276 /* DTE mode */
1293 /* DTE mode */
1310 /* DTE mode */
1325 /* DTE mode */
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| H A D | imx6dl-eckelmann-ci4x10.dts | 332 fsl,dte-mode;
343 fsl,dte-mode;
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| H A D | imx6ull-colibri.dtsi | 274 fsl,dte-mode;
282 fsl,dte-mode;
289 fsl,dte-mode;
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| H A D | imx6qdl-colibri.dtsi | 671 fsl,dte-mode;
680 fsl,dte-mode;
689 fsl,dte-mode;
1049 /* DTE mode */
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| H A D | mba6ulx.dtsi | 344 /* for DTE mode, add below change */
345 /* fsl,dte-mode; */
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| H A D | imx6q-arm2.dts | 209 fsl,dte-mode;
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| /linux/drivers/net/wan/ |
| H A D | wanxl.c | 9 * - Only DTE (external clock) support with NRZ and NRZI encodings
112 const char *cable, *pm, *dte = "", *dsr = "", *dcd = ""; in wanxl_cable_intr() local
163 dte = (value & STATUS_CABLE_DCE) ? " DCE" : " DTE"; in wanxl_cable_intr()
166 pm, dte, cable, dsr, dcd); in wanxl_cable_intr()
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| /linux/drivers/iommu/amd/ |
| H A D | iommu.c | 587 pr_err("DTE[%d]: %016llx\n", i, dev_table[devid].data[i]); in dump_dte_entry()
1903 /* Encode GCR3 table into DTE */ in set_dte_entry()
1955 /* Update and flush DTE for the given device */
2056 /* Clear DTE and flush the entry */ in do_detach()
2134 /* Updated here so that it gets reflected in DTE */ in detach_device()
2353 * Since DTE[Mode]=0 is prohibited on SNP-enabled system, in do_iommu_domain_alloc()
2432 /* Clear DTE and flush the entry */ in blocked_domain_attach_device()
2645 /* Flush device DTE */ in amd_iommu_set_dirty_tracking()
2788 * - SNP is enabled, because it prohibits DTE[Mode]=0. in amd_iommu_def_domain_type()
2911 u64 dte; in set_dte_irq_entry() local
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| /linux/Documentation/virt/kvm/devices/ |
| H A D | arm-vgic-its.rst | 156 Device Table Entry (DTE)::
166 corresponds to the DeviceID offset to the next DTE, capped by
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| /linux/include/uapi/linux/hdlc/ |
| H A D | ioctl.h | 9 #define CLOCK_EXT 1 /* External TX and RX clock - DTE */
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| /linux/arch/arm/boot/dts/nvidia/ |
| H A D | tegra20-trimslice.dts | 98 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
213 "dte", "gma", "gmc", "gmd", "gpu",
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| H A D | tegra20-tamonten.dtsi | 92 nvidia,pins = "dtb", "dtc", "dte";
206 "dtc", "dte", "gpu", "sdio1",
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | nvidia,tegra20-pinmux.yaml | 36 dap2, dap3, dap4, ddc, dta, dtb, dtc, dtd, dte, dtf, gma,
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | si_dpm.h | 185 /* DTE stuff */
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| /linux/Documentation/networking/pse-pd/ |
| H A D | introduction.rst | 55 Summary of Clause 33: Data Terminal Equipment (DTE) Power via Media Dependent Interface (MDI)
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