Searched full:clock1 (Results 1 – 8 of 8) sorted by relevance
| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | renesas,sdhi.yaml | 159 - description: IMCLK, SDHI channel main clock1.
161 4 times that of SDHI channel main clock1.
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| /linux/Documentation/devicetree/bindings/ata/ |
| H A D | snps,dwc-ahci.yaml | 66 clocks = <&clock1>, <&clock2>;
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| /linux/drivers/clk/x86/ |
| H A D | clk-fch.c | 19 /* Auxiliary clock1 enable bit */
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| /linux/Documentation/devicetree/bindings/regulator/ |
| H A D | fixed-regulator.yaml | 142 clocks = <&clock1>;
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| /linux/sound/soc/codecs/ |
| H A D | wm8903.c | 1459 u16 clock1 = snd_soc_component_read(component, WM8903_CLOCK_RATES_1); in wm8903_hw_params()
1480 clock1 &= ~WM8903_SAMPLE_RATE_MASK; in wm8903_hw_params()
1481 clock1 |= sample_rates[dsp_config].value; in wm8903_hw_params()
1535 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK | in wm8903_hw_params()
1537 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT; in wm8903_hw_params()
1538 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT; in wm8903_hw_params()
1576 snd_soc_component_write(component, WM8903_CLOCK_RATES_1, clock1); in wm8903_hw_params()
1457 u16 clock1 = snd_soc_component_read(component, WM8903_CLOCK_RATES_1); wm8903_hw_params() local
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | idt,versaclock5.yaml | 107 Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_display.c | 4791 bool intel_fuzzy_clock_check(int clock1, int clock2) in intel_fuzzy_clock_check() argument
4795 if (clock1 == clock2) in intel_fuzzy_clock_check()
4798 if (!clock1 || !clock2) in intel_fuzzy_clock_check()
4801 diff = abs(clock1 - clock2); in intel_fuzzy_clock_check()
4803 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) in intel_fuzzy_clock_check()
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| /linux/sound/ppc/ |
| H A D | snd_ps3_reg.h | 367 Sets the divide ration of Master Clock1 (clock output from
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