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/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3588s.dtsi6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
443 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
454 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
465 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB
423 cru: clock-controller@fd7c0000 { global() label
[all...]
H A Drk3399.dtsi6 #include <dt-bindings/clock/rk3399-cru.h>
79 clocks = <&cru ARMCLKL>;
91 clocks = <&cru ARMCLKL>;
103 clocks = <&cru ARMCLKL>;
115 clocks = <&cru ARMCLKL>;
127 clocks = <&cru ARMCLKB>;
145 clocks = <&cru ARMCLKB>;
189 clocks = <&cru SCLK_DDRC>;
236 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCI
1467 cru: clock-controller@ff760000 { global() label
[all...]
H A Drk356x.dtsi6 #include <dt-bindings/clock/rk3568-cru.h>
257 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
258 <&cru CLK_SATA1_RXOOB>;
271 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
272 <&cru CLK_SATA2_RXOOB>;
286 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
287 <&cru ACLK_USB3OTG
418 cru: clock-controller@fdd20000 { global() label
[all...]
H A Drk3588.dtsi24 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
26 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
27 assigned-clock-parents = <&cru PLL_AUPLL>;
31 resets = <&cru SRST_M_I2S8_8CH_TX>;
41 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
43 assigned-clocks = <&cru CLK_I2S6_8CH_TX_SR
[all...]
H A Drk3328.dtsi6 #include <dt-bindings/clock/rk3328-cru.h>
44 clocks = <&cru ARMCLK>;
57 clocks = <&cru ARMCLK>;
70 clocks = <&cru ARMCLK>;
83 clocks = <&cru ARMCLK>;
219 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
231 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
243 clocks = <&cru SCLK_I2S
778 cru: clock-controller@ff440000 { global() label
[all...]
H A Drk3368.dtsi6 #include <dt-bindings/clock/rk3368-cru.h>
186 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
187 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
191 resets = <&cru SRST_MMC0>;
200 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
201 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPL
747 cru: clock-controller@ff760000 { global() label
[all...]
H A Dpx30.dtsi6 #include <dt-bindings/clock/px30-cru.h>
46 clocks = <&cru ARMCLK>;
58 clocks = <&cru ARMCLK>;
70 clocks = <&cru ARMCLK>;
82 clocks = <&cru ARMCLK>;
269 clocks = <&cru HCLK_HOST>,
270 <&cru HCLK_OTG>,
271 <&cru SCLK_OTG_ADP>;
277 clocks = <&cru HCLK_SDMMC>,
278 <&cru SCLK_SDMM
828 cru: clock-controller@ff2b0000 { global() label
[all...]
H A Drk3568.dtsi14 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
15 <&cru CLK_SATA0_RXOOB>;
55 <&cru PCLK_PCIE30PHY>;
57 resets = <&cru SRST_PCIE30PHY>;
68 clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
69 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
70 <&cru CLK_PCIE30X1_AUX_NDFT>;
102 resets = <&cru SRST_PCIE30X1_POWERUP>;
121 clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
122 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
[all …]
H A Drk3308.dtsi7 #include <dt-bindings/clock/rk3308-cru.h>
51 clocks = <&cru ARMCLK>;
196 assigned-clocks = <&cru USB480M>;
198 clocks = <&cru SCLK_USBPHY_REF>;
240 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
253 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
266 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C
747 cru: clock-controller@ff500000 { global() label
[all...]
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk322x.dtsi7 #include <dt-bindings/clock/rk3228-cru.h>
36 resets = <&cru SRST_CORE0>;
40 clocks = <&cru ARMCLK>;
48 resets = <&cru SRST_CORE1>;
58 resets = <&cru SRST_CORE2>;
68 resets = <&cru SRST_CORE3>;
144 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
157 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8C
484 cru: clock-controller@110e0000 { global() label
[all...]
H A Drk3288.dtsi7 #include <dt-bindings/clock/rk3288-cru.h>
70 resets = <&cru SRST_CORE0>;
74 clocks = <&cru ARMCLK>;
81 resets = <&cru SRST_CORE1>;
85 clocks = <&cru ARMCLK>;
92 resets = <&cru SRST_CORE2>;
96 clocks = <&cru ARMCLK>;
103 resets = <&cru SRST_CORE3>;
107 clocks = <&cru ARMCLK>;
208 clocks = <&cru PCLK_TIME
862 cru: clock-controller@ff760000 { global() label
[all...]
H A Drv1126.dtsi6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
42 clocks = <&cru ARMCLK>;
50 clocks = <&cru ARMCLK>;
58 clocks = <&cru ARMCLK>;
66 clocks = <&cru ARMCLK>;
185 clocks = <&cru HCLK_EMMC>,
186 <&cru CLK_EMMC>,
187 <&cru HCLK_NANDC>,
188 <&cru CLK_NANDC>,
189 <&cru HCLK_SF
214 cru: clock-controller@ff490000 { global() label
[all...]
H A Drk3xxx.dtsi46 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
48 assigned-clocks = <&cru ACLK_GPU>;
50 resets = <&cru SRST_GPU>;
60 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
61 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
82 clocks = <&cru CORE_PERI>;
96 clocks = <&cru CORE_PER
[all...]
H A Drk3066a.dtsi9 #include <dt-bindings/clock/rk3066a-cru.h>
41 clocks = <&cru ARMCLK>;
73 clocks = <&cru ACLK_LCDC0>,
74 <&cru DCLK_LCDC0>,
75 <&cru HCLK_LCDC0>;
78 resets = <&cru SRST_LCDC0_AXI>,
79 <&cru SRST_LCDC0_AHB>,
80 <&cru SRST_LCDC0_DCLK>;
99 clocks = <&cru ACLK_LCDC1>,
100 <&cru DCLK_LCDC
202 cru: clock-controller@20000000 { global() label
[all...]
H A Drk3036.dtsi7 #include <dt-bindings/clock/rk3036-cru.h>
44 resets = <&cru SRST_CORE0>;
50 clocks = <&cru ARMCLK>;
57 resets = <&cru SRST_CORE1>;
114 assigned-clocks = <&cru SCLK_GPU>;
116 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
119 resets = <&cru SRST_GPU>;
128 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODE
328 cru: clock-controller@20000000 { global() label
[all...]
H A Drv1108.dtsi6 #include <dt-bindings/clock/rv1108-cru.h>
36 clocks = <&cru ARMCLK>;
103 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
118 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
133 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
147 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C
449 cru: clock-controller@20200000 { global() label
[all...]
H A Drk3188.dtsi9 #include <dt-bindings/clock/rk3188-cru.h>
27 clocks = <&cru ARMCLK>;
29 resets = <&cru SRST_CORE0>;
37 resets = <&cru SRST_CORE1>;
45 resets = <&cru SRST_CORE2>;
53 resets = <&cru SRST_CORE3>;
119 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
122 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
136 clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
139 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
[all …]
H A Drk3128.dtsi6 #include <dt-bindings/clock/rk3128-cru.h>
52 clocks = <&cru ARMCLK>;
53 resets = <&cru SRST_CORE0>;
62 resets = <&cru SRST_CORE1>;
70 resets = <&cru SRST_CORE2>;
78 resets = <&cru SRST_CORE3>;
184 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
187 resets = <&cru SRST_GPU>;
204 clocks = <&cru ACLK_CI
186 cru: clock-controller@20000000 { global() label
[all...]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Drockchip-dwmac.txt20 - clocks: <&cru SCLK_MAC>: clock selector for main clock, from PLL or PHY.
21 <&cru SCLK_MAC_PLL>: PLL clock for SCLK_MAC
22 <&cru SCLK_MAC_RX>: clock gate for RX
23 <&cru SCLK_MAC_TX>: clock gate for TX
24 <&cru SCLK_MACREF>: clock gate for RMII referce clock
25 <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output
26 <&cru ACLK_GMAC>: AXI clock gate for GMAC
27 <&cru PCLK_GMAC>: APB clock gate for GMAC
38 - assigned-clocks: main clock, should be <&cru SCLK_MAC>;
40 can be <&ext_gmac> or <&cru SCLK_MAC_PLL>.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-rockchip-typec.txt11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
12 <&cru SCLK_UPHY1_TCPDCORE>;
43 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
44 <&cru SCLK_UPHY0_TCPDPHY_REF>;
46 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
48 resets = <&cru SRST_UPHY0>,
49 <&cru SRST_UPHY0_PIPE_L00>,
50 <&cru SRST_P_UPHY0_TCPHY>;
67 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
68 <&cru SCLK_UPHY1_TCPDPHY_REF>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Drockchip,rk3399-pcie-ep.yaml42 #include <dt-bindings/clock/rk3399-cru.h>
52 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
53 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
58 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
59 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
60 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
H A Drockchip-pcie-ep.txt45 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
46 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
53 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
54 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
55 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
H A Drockchip,rk3399-pcie.yaml82 #include <dt-bindings/clock/rk3399-cru.h>
93 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
94 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
108 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
109 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
110 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Drockchip,rk3128-cru.txt9 - compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru"
10 "rockchip,rk3126-cru" - controller compatible with RK3126 SoC.
11 "rockchip,rk3128-cru" - controller compatible with RK3128 SoC.
24 preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be
39 cru: cru@20000000 {
40 compatible = "rockchip,rk3128-cru";
56 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Drockchip,rk3399-dwc3.yaml73 #include <dt-bindings/clock/rk3399-cru.h>
86 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
87 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
88 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
92 resets = <&cru SRST_A_USB3_OTG0>;
99 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
100 <&cru SCLK_USB3OTG0_SUSPEND>;

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