Lines Matching full:cru
7 #include <dt-bindings/clock/rk3308-cru.h>
51 clocks = <&cru ARMCLK>;
196 assigned-clocks = <&cru USB480M>;
198 clocks = <&cru SCLK_USBPHY_REF>;
240 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
253 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
266 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
279 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
292 clocks = <&cru PCLK_WDT>;
301 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
314 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
327 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
340 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
353 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
368 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
383 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
398 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
410 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
421 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
432 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
443 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
454 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
465 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
476 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
487 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
498 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
509 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
520 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
531 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
543 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
551 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
554 resets = <&cru SRST_SARADC_P>;
565 clocks = <&cru ACLK_DMAC0>;
576 clocks = <&cru ACLK_DMAC1>;
585 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>;
589 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>;
603 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>;
607 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>;
616 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>;
630 clocks = <&cru HCLK_OTG>;
645 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
655 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
666 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
667 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
681 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
682 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
694 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
695 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
709 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
711 assigned-clocks = <&cru SCLK_NANDC>;
724 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
725 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>,
726 <&cru SCLK_MAC>, <&cru ACLK_MAC>,
727 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>;
735 resets = <&cru SRST_MAC_A>;
745 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
752 cru: clock-controller@ff500000 {
753 compatible = "rockchip,rk3308-cru";
760 assigned-clocks = <&cru SCLK_RTC32K>;
805 clocks = <&cru PCLK_GPIO0>;
816 clocks = <&cru PCLK_GPIO1>;
827 clocks = <&cru PCLK_GPIO2>;
838 clocks = <&cru PCLK_GPIO3>;
849 clocks = <&cru PCLK_GPIO4>;