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/linux/arch/arm/boot/dts/samsung/
H A Dexynos4412.dtsi1 // SPDX-License-Identifier: GPL-2.0
23 #address-cells = <1>;
24 #size-cells = <0>;
26 cpu-map {
29 cpu = <&cpu0>;
32 cpu = <&cpu1>;
35 cpu = <&cpu2>;
38 cpu = <&cpu3>;
43 cpu0: cpu@a00 {
44 device_type = "cpu";
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H A Dexynos4212.dtsi1 // SPDX-License-Identifier: GPL-2.0
23 #address-cells = <1>;
24 #size-cells = <0>;
26 cpu-map {
29 cpu = <&cpu0>;
32 cpu = <&cpu1>;
37 cpu0: cpu@a00 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a9";
42 clock-names = "cpu";
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/linux/arch/arm64/boot/dts/apple/
H A Dt600x-common.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #address-cells = <2>;
12 #size-cells = <2>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
25 cpu = <&cpu_e00>;
28 cpu = <&cpu_e01>;
34 cpu = <&cpu_p00>;
37 cpu = <&cpu_p01>;
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/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
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H A Dopp-v2-kryo-cpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
13 - $ref: opp-v2-base.yaml#
17 the CPU frequencies subset and voltage value of each OPP varies based on
22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
25 operating-points-v2 table when it is parsed by the OPP framework.
30 - operating-points-v2-krait-cpu
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/linux/Documentation/trace/
H A Dtimerlat-tracer.rst6 find sources of wakeup latencies of real-time threads. Like cyclictest,
13 -----
28 # _-----=> irqs-off
29 # / _----=> need-resched
30 # | / _---=> hardirq/softirq
31 # || / _--=> preempt-depth
34 # TASK-PID CPU# |||| TIMESTAMP ID CONTEXT LATENCY
36 <idle>-0 [000] d.h1 54.029328: #1 context irq timer_latency 932 ns
37 <...>-867 [000] .... 54.029339: #1 context thread timer_latency 11700 ns
38 <idle>-0 [001] dNh1 54.029346: #1 context irq timer_latency 2833 ns
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am625.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 /dts-v1/;
12 #include "k3-am62.dtsi"
16 #address-cells = <1>;
17 #size-cells = <0>;
19 cpu-map {
22 cpu = <&cpu0>;
26 cpu = <&cpu1>;
30 cpu = <&cpu2>;
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H A Dk3-am62a7.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 /dts-v1/;
12 #include "k3-am62a.dtsi"
16 #address-cells = <1>;
17 #size-cells = <0>;
19 cpu-map {
22 cpu = <&cpu0>;
26 cpu = <&cpu1>;
30 cpu = <&cpu2>;
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/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-a33.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include "sun8i-a23-a33.dtsi"
46 #include <dt-bindings/thermal/thermal.h>
49 cpu0_opp_table: opp-table-cpu {
50 compatible = "operating-points-v2";
51 opp-shared;
53 opp-120000000 {
54 opp-hz = /bits/ 64 <120000000>;
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H A Dsun8i-a83t.dtsi6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
48 #include <dt-bindings/clock/sun8i-de2.h>
49 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
51 #include <dt-bindings/reset/sun8i-de2.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
53 #include <dt-bindings/thermal/thermal.h>
56 interrupt-parent = <&gic>;
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/linux/Documentation/devicetree/bindings/powerpc/opal/
H A Dpower-mgt.txt1 IBM Power-Management Bindings
6 node @power-mgt in the device-tree by the firmware.
9 ----------------
12 - name: The name of the idle state as defined by the firmware.
14 - flags: indicating some aspects of this idle states such as the
15 extent of state-loss, whether timebase is stopped on this
18 - exit-latency: The latency involved in transitioning the state of the
19 CPU from idle to running.
21 - target-residency: The minimum time that the CPU needs to reside in
22 this idle state in order to accrue power-savings
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/linux/arch/x86/mm/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/cpu.h>
18 #include <asm/nospec-branch.h>
39 * TLB flushing, formerly SMP-only
70 * Instead we have a small per-cpu array of ASIDs and cache the last few mm's
71 * that came by on this CPU, allowing cheaper switch_mm between processes on
72 * this CPU.
77 * ASID - [0, TLB_NR_DYN_ASIDS-1]
78 * the canonical identifier for an mm, dynamically allocated on each CPU
79 * [TLB_NR_DYN_ASIDS, MAX_ASID_AVAILABLE-1]
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/linux/tools/perf/scripts/python/
H A Dfutex-contention.py18 '/scripts/python/Perf-Trace-Util/lib/Perf/Trace')
25 lock_waits = {} # long-lived stats on (tid,lock) blockage elapsed time
26 process_names = {} # long-lived pid-to-execname mapping
29 def syscalls__sys_enter_futex(event, ctxt, cpu, s, ns, tid, comm, callchain, argument
37 thread_blocktime[tid] = nsecs(s, ns)
40 def syscalls__sys_exit_futex(event, ctxt, cpu, s, ns, tid, comm, callchain, argument
43 elapsed = nsecs(s, ns) - thread_blocktime[tid]
56 print("%s[%d] lock %x contended %d times, %d avg ns [max: %d ns, min %d ns]" %
H A Dpowerpc-hcalls.py1 # SPDX-License-Identifier: GPL-2.0+
13 '/scripts/python/Perf-Trace-Util/lib/Perf/Trace')
30 # cpu: {
159 print_ptrn = '%-28s%10s%10s%10s%10s'
162 print(print_ptrn % ('hcall', 'count', 'min(ns)', 'max(ns)', 'avg(ns)'))
163 print('-' * 68)
173 def powerpc__hcall_exit(name, context, cpu, sec, nsec, pid, comm, callchain, argument
175 if (cpu in d_enter and opcode in d_enter[cpu]):
176 diff = nsecs(sec, nsec) - d_enter[cpu][opcode]
193 del d_enter[cpu][opcode]
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H A Dparallel-perf.py2 # SPDX-License-Identifier: GPL-2.0
5 # options --cpu and --time so that each job processes a different chunk
20 glb_prog_name = "parallel-perf.py"
88 return [ f"Non-empty error file {self.stderr_name}" ]
139 x = "0" * (10 - len(x)) + x
140 return x[:len(x) - 9] + "." + x[-9:]
150 max_len = len(str(cpus[-1]))
151 cpu_dir_fmt = f"cpu-%.{max_len}u"
154 for cpu in cpus:
155 if cpu >= 0:
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/linux/Documentation/gpu/nova/core/
H A Dfalcon.rst1 .. SPDX-License-Identifier: GPL-2.0
10 interactions of nova-core driver with the Falcon.
12 NVIDIA GPUs embed small RISC-like microcontrollers called Falcon cores, which
15 processor) and SEC2 (the security engine)) and also may integrate a RISC-V core.
16 This core is capable of running both RISC-V and Falcon code.
22 small DMA engine (via the FBIF - "Frame Buffer Interface") to load code from
23 system memory. The nova-core driver must reset and configure the Falcon, load
24 its firmware via DMA, and start its CPU.
28 Falcons can run in Non-secure (NS), Light Secure (LS), or Heavy Secure (HS)
32 --------------------------------------------------------
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/linux/kernel/locking/
H A Dqspinlock_stat.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 * PV specific per-cpu counter
30 * Average kick latency (ns) = pv_latency_kick/pv_kick_unlock
32 * Average wake latency (ns) = pv_latency_wake/pv_kick_wake
40 int cpu, id, len; in lockevent_read() local
44 * Get the counter ID stored in file->f_inode->i_private in lockevent_read()
46 id = (long)file_inode(file)->i_private; in lockevent_read()
49 return -EBADF; in lockevent_read()
51 for_each_possible_cpu(cpu) { in lockevent_read()
52 sum += per_cpu(lockevents[id], cpu); in lockevent_read()
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/linux/arch/powerpc/boot/
H A Dsimpleboot.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * The simple platform -- for booting when firmware doesn't supply a device
28 const u32 *na, *ns, *reg, *timebase; in platform_init() local
36 /* Find the #address-cells and #size-cells properties */ in platform_init()
40 na = fdt_getprop(_dtb_start, node, "#address-cells", &size); in platform_init()
42 fatal("Cannot find #address-cells property"); in platform_init()
43 ns = fdt_getprop(_dtb_start, node, "#size-cells", &size); in platform_init()
44 if (!ns || (size != 4)) in platform_init()
45 fatal("Cannot find #size-cells property"); in platform_init()
48 node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type", in platform_init()
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/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8996pro.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 /delete-node/ opp-table-cluster0;
10 /delete-node/ opp-table-cluster1;
18 cluster0_opp: opp-table-cluster0 {
19 compatible = "operating-points-v2-kryo-cpu";
20 nvmem-cells = <&speedbin_efuse>;
21 opp-shared;
23 opp-307200000 {
24 opp-hz = /bits/ 64 <307200000>;
25 opp-supported-hw = <0x70>;
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/linux/Documentation/devicetree/bindings/reserved-memory/
H A Dnvidia,tegra264-bpmp-shmem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra CPU-NS - BPMP IPC reserved memory
10 - Peter De Schrijver <pdeschrijver@nvidia.com>
13 Define a memory region used for communication between CPU-NS and BPMP.
15 has to be known to both CPU-NS and BPMP for correct IPC operation.
16 The memory region is defined using a child node under /reserved-memory.
17 The sub-node is named shmem@<address>.
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/linux/tools/testing/selftests/seccomp/
H A Dseccomp_benchmark.c39 i = finish.tv_sec - start.tv_sec; in timing()
41 i += finish.tv_nsec - start.tv_nsec; in timing()
43 ksft_print_msg("%lu.%09lu - %lu.%09lu = %llu (%.1fs)\n", in timing()
71 i = finish.tv_sec - start.tv_sec; in calibrate()
73 i += finish.tv_nsec - start.tv_nsec; in calibrate()
140 /* Pin to a single CPU so the benchmark won't bounce around the system. */
143 long cpu; in affinity() local
150 * choose the highest CPU instead of the lowest. in affinity()
152 for (cpu = ncores - in affinity()
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/linux/include/linux/
H A Dpsi_types.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 * For IO and CPU stalls the presence of running/oncpu tasks
67 /* Only per-CPU, to weigh the CPU in the global average: */
75 /* Flag whether to re-arm avgs_work, see details in get_recent_times() */
94 /* Period time sampling buckets for each state of interest (ns) */
109 /* Window size in ns */
112 /* Start time of the current window in ns */
126 /* User-spacified threshold in ns */
148 * Time last event was generated. Used for rate-limiting
156 /* Trigger type - PSI_AVGS for unprivileged, PSI_POLL for RT */
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/linux/include/linux/sched/
H A Dcputime.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 *utime = t->utime; in task_cputime()
20 *stime = t->stime; in task_cputime()
26 return t->gtime; in task_gtime()
35 *utimescaled = t->utimescaled; in task_cputime_scaled()
36 *stimescaled = t->stimescaled; in task_cputime_scaled()
53 * Thread group CPU time accounting.
59 * The following are functions that support scheduler-internal time accounting.
65 * get_running_cputimer - return &tsk->signal->cputimer if cputimers are active
73 struct thread_group_cputimer *cputimer = &tsk->signal->cputimer; in get_running_cputimer()
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/linux/Documentation/devicetree/bindings/thermal/
H A Dbrcm,ns-thermal.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/thermal/brcm,ns-thermal.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafał Miłecki <rafal@milecki.pl>
16 - $ref: thermal-sensor.yaml#
20 const: brcm,ns-thermal
26 "#thermal-sensor-cells":
32 - reg
35 - |
[all …]
/linux/drivers/of/
H A Daddress.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/dma-direct.h> /* for bus_dma_region */
34 int na, int ns, int pna, int fna);
54 int na, int ns, int pna, int fna) in of_bus_default_map() argument
58 cp = of_read_number(range + fna, na - fna); in of_bus_default_map()
59 s = of_read_number(range + na + pna, ns); in of_bus_default_map()
60 da = of_read_number(addr + fna, na - fna); in of_bus_default_map()
66 return da - cp; in of_bus_default_map()
75 addr[na - 2] = cpu_to_be32(a >> 32); in of_bus_default_translate()
76 addr[na - 1] = cpu_to_be32(a & 0xffffffffu); in of_bus_default_translate()
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