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/linux/Documentation/devicetree/bindings/mmc/
H A Dsamsung,s3c6410-sdhci.yaml74 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
/linux/include/dt-bindings/clock/
H A Dexynos5250.h84 #define CLK_SDMMC0 280 macro
H A Dexynos4.h135 #define CLK_SDMMC0 297 macro
H A Dexynos3250.h205 #define CLK_SDMMC0 199 macro
H A Drk3568-cru.h241 #define CLK_SDMMC0 177 macro
/linux/drivers/clk/rockchip/
H A Dclk-rk3568.c898 COMPOSITE_NODIV(CLK_SDMMC0, "clk_sdmmc0", clk_sdmmc_p, 0,
901 MMC(SCLK_SDMMC0_DRV, "sdmmc0_drv", "clk_sdmmc0", RK3568_SDMMC0_CON0, 1),
902 MMC(SCLK_SDMMC0_SAMPLE, "sdmmc0_sample", "clk_sdmmc0", RK3568_SDMMC0_CON1, 1),
/linux/arch/arm/boot/dts/samsung/
H A Dexynos3250.dtsi555 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
H A Dexynos4.dtsi322 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
H A Dexynos5250.dtsi555 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
/linux/drivers/clk/samsung/
H A Dclk-exynos5250.c564 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0),
H A Dclk-exynos3250.c650 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
H A Dclk-exynos4.c843 GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5,
/linux/arch/arm64/boot/dts/rockchip/
H A Drk356x.dtsi1068 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,