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/linux/drivers/mtd/nand/raw/ingenic/
H A Djz4725b_bch.c3 * JZ4725B BCH controller driver
59 /* Timeout for BCH calculation/correction. */
62 static inline void jz4725b_bch_config_set(struct ingenic_ecc *bch, u32 cfg) in jz4725b_bch_config_set() argument
64 writel(cfg, bch->base + BCH_BHCSR); in jz4725b_bch_config_set()
67 static inline void jz4725b_bch_config_clear(struct ingenic_ecc *bch, u32 cfg) in jz4725b_bch_config_clear() argument
69 writel(cfg, bch->base + BCH_BHCCR); in jz4725b_bch_config_clear()
72 static int jz4725b_bch_reset(struct ingenic_ecc *bch, in jz4725b_bch_reset() argument
78 writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT); in jz4725b_bch_reset()
80 /* Initialise and enable BCH. */ in jz4725b_bch_reset()
81 jz4725b_bch_config_clear(bch, 0x1f); in jz4725b_bch_reset()
[all …]
H A Djz4780_bch.c3 * JZ4780 BCH controller driver
59 /* Timeout for BCH calculation/correction. */
62 static void jz4780_bch_reset(struct ingenic_ecc *bch, in jz4780_bch_reset() argument
68 writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT); in jz4780_bch_reset()
70 /* Set up BCH count register. */ in jz4780_bch_reset()
73 writel(reg, bch->base + BCH_BHCNT); in jz4780_bch_reset()
75 /* Initialise and enable BCH. */ in jz4780_bch_reset()
80 writel(reg, bch->base + BCH_BHCR); in jz4780_bch_reset()
83 static void jz4780_bch_disable(struct ingenic_ecc *bch) in jz4780_bch_disable() argument
85 writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT); in jz4780_bch_disable()
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H A DKconfig8 based boards, using the BCH controller for hardware error correction.
16 tristate "Hardware BCH support for JZ4740 SoC"
26 tristate "Hardware BCH support for JZ4725B SoC"
29 Enable this driver to support the BCH error-correction hardware
33 will be called jz4725b-bch.
36 tristate "Hardware BCH support for JZ4780 SoC"
39 Enable this driver to support the BCH error-correction hardware
43 will be called jz4780-bch.
H A Dingenic_ecc.c105 * ingenic,bch-controller property in of_ingenic_ecc_get()
108 np = of_parse_phandle(of_node, "ingenic,bch-controller", 0); in of_ingenic_ecc_get()
/linux/drivers/mtd/nand/
H A Decc-sw-bch.c4 * using binary BCH codes. It relies on the generic BCH library lib/bch.c.
15 #include <linux/mtd/nand-ecc-sw-bch.h>
30 bch_encode(engine_conf->bch, buf, nand->ecc.ctx.conf.step_size, code); in nand_ecc_sw_bch_calculate()
57 count = bch_decode(engine_conf->bch, NULL, step_size, read_ecc, in nand_ecc_sw_bch_correct()
79 * nand_ecc_sw_bch_cleanup - Cleanup software BCH ECC resources
86 bch_free(engine_conf->bch); in nand_ecc_sw_bch_cleanup()
92 * nand_ecc_sw_bch_init - Initialize software BCH ECC engine
95 * Returns: a pointer to a new NAND BCH control structure, or NULL upon failure
97 * Initialize NAND BCH error correction. @nand.ecc parameters 'step_size' and
98 * 'bytes' are used to compute the following BCH parameters:
[all …]
H A DKconfig27 more strength correction and in this case BCH or RS will be
39 bool "Software BCH ECC engine"
40 select BCH
44 This enables support for software BCH error correction. Binary BCH
/linux/drivers/md/bcache/
H A Dfeatures.h40 BCH##_FEATURE_COMPAT_##flagname) != 0); \
45 BCH##_FEATURE_COMPAT_##flagname; \
50 ~BCH##_FEATURE_COMPAT_##flagname; \
59 BCH##_FEATURE_RO_COMPAT_##flagname) != 0); \
64 BCH##_FEATURE_RO_COMPAT_##flagname; \
69 ~BCH##_FEATURE_RO_COMPAT_##flagname; \
78 BCH##_FEATURE_INCOMPAT_##flagname) != 0); \
83 BCH##_FEATURE_INCOMPAT_##flagname; \
88 ~BCH##_FEATURE_INCOMPAT_##flagname; \
/linux/include/linux/mtd/
H A Dnand-ecc-sw-bch.h5 * This file is the header for the NAND BCH ECC implementation.
12 #include <linux/bch.h>
15 * struct nand_ecc_sw_bch_conf - private software BCH ECC engine structure
21 * @bch: BCH control structure
30 struct bch_control *bch; member
/linux/include/linux/
H A Dbch.h3 * Generic binary BCH encoding/decoding library
12 * Bose-Chaudhuri-Hocquenghem (BCH) codes.
20 * struct bch_control - BCH control structure
61 void bch_free(struct bch_control *bch);
63 void bch_encode(struct bch_control *bch, const uint8_t *data,
66 int bch_decode(struct bch_control *bch, const uint8_t *data, unsigned int len,
/linux/drivers/mtd/nand/raw/gpmi-nand/
H A Dgpmi-nand.h26 * struct bch_geometry - BCH geometry description.
134 /* BCH */
149 bool bch; member
166 /* BCH : Status Block Completion Codes */
/linux/drivers/mtd/nand/raw/
H A Darasan-nand-controller.c13 #include <linux/bch.h>
164 * @errloc: Array of errors located with soft BCH
166 * @bch: BCH structure
187 struct bch_control *bch; member
388 * The hardware BCH ECC engine is known to be inconstent in BCH mode and never
390 * software BCH implementation in the read path.
448 * For each step, compute by softare the BCH syndrome over the raw data. in anfc_read_page_hw_ecc()
463 bf = bch_decode(anand->bch, raw_buf, chip->ecc.size, in anfc_read_page_hw_ecc()
1186 anand->bch = bch_init(bch_gf_mag, ecc->strength, bch_prim_poly, true); in anfc_init_hw_ecc_controller()
1187 if (!anand->bch) in anfc_init_hw_ecc_controller()
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H A Dnandsim.c98 static unsigned int bch; variable
130 module_param(bch, uint, 0400);
164 MODULE_PARM_DESC(bch, "Enable BCH ecc and set how many bits should "
2217 chip->ecc.algo = bch ? NAND_ECC_ALGO_BCH : NAND_ECC_ALGO_HAMMING; in ns_attach_chip()
2219 if (!bch) in ns_attach_chip()
2223 NS_ERR("BCH ECC support is disabled\n"); in ns_attach_chip()
2229 eccbytes = ((bch * 13) + 7) / 8; in ns_attach_chip()
2233 NS_ERR("BCH not available on small page devices\n"); in ns_attach_chip()
2238 NS_ERR("Invalid BCH value %u\n", bch); in ns_attach_chip()
2243 chip->ecc.strength = bch; in ns_attach_chip()
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H A Dnuvoton-ma35d1-nand-controller.c73 /* Define for the BCH hardware ECC engine */
77 /* define the BCH parity code length for 512 bytes data pattern */
80 /* define the BCH parity code length for 1024 bytes data pattern */
256 /* Set BCH algorithm */ in ma35_nand_hwecc_init()
282 /* Correct data by BCH alrogithm */
365 * For example, for BCH T12, the first parity code = 512 + 32 - 23 = 521. in ma35_nfi_correct()
H A Domap_elm.c98 * @bch_type: Type of BCH ecc
473 * to be saved for all BCH schemes*/ in elm_context_save()
568 MODULE_DESCRIPTION("ELM driver for BCH error correction");
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4_pci_id_tbl.h101 CH_PCI_ID_TABLE_FENTRY(0x4004), /* T420-bch */
102 CH_PCI_ID_TABLE_FENTRY(0x4005), /* T440-bch */
128 CH_PCI_ID_TABLE_FENTRY(0x5004), /* T520-bch */
129 CH_PCI_ID_TABLE_FENTRY(0x5005), /* T540-bch */
/linux/drivers/spi/
H A Dspi-amlogic-spifc-a4.c76 #define CMD_MEM2NAND(bch, pages) (OP_M2N | ((bch) << 14) | (pages)) argument
77 #define CMD_NAND2MEM(bch, pages) (OP_N2M | ((bch) << 14) | (pages)) argument
171 u32 bch; member
206 #define AML_ECC_DATA(sz, s, b) { .stepsize = (sz), .strength = (s), .bch = (b) }
708 cmd |= CMD_NAND2MEM(ecc_cfg->bch, ecc_cfg->nsteps); in aml_sfc_read_page_hwecc()
773 cmd |= CMD_MEM2NAND(ecc_cfg->bch, ecc_cfg->nsteps); in aml_sfc_write_page_hwecc()
962 nand->ecc.ctx.conf.flags |= BIT(ecc_caps[i].bch); in aml_sfc_ecc_init_ctx()
996 ecc_cfg->bch = nand->ecc.ctx.conf.flags & BIT(ECC_DEFAULT_BCH_MODE) ? 1 : 2; in aml_sfc_ecc_init_ctx()
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm5301x-nand-cs0-bch4.dtsi9 nand-ecc-algo = "bch";
H A Dbcm5301x-nand-cs0-bch1.dtsi11 nand-ecc-algo = "bch";
H A Dbcm5301x-nand-cs0-bch8.dtsi14 nand-ecc-algo = "bch";
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-conn.dtsi31 conn_bch_clk: clock-conn-bch {
368 reg-names = "gpmi-nand", "bch";
372 interrupt-names = "bch";
/linux/include/linux/platform_data/
H A Delm.h3 * BCH Error Location Module
/linux/Documentation/devicetree/bindings/mtd/
H A Dti,elm.yaml14 errors and the location of the error based on BCH algorithms
H A Dmediatek,nand-ecc-engine.yaml56 bch: ecc@1100e000 {
/linux/arch/mips/boot/dts/ingenic/
H A Djz4780.dtsi572 bch: bch@134d0000 { label
573 compatible = "ingenic,jz4780-bch";
H A Djz4725b.dtsi360 bch: ecc-controller@130d0000 { label
361 compatible = "ingenic,jz4725b-bch";

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