Searched full:arria5 (Results 1 – 7 of 7) sorted by relevance
| /linux/Documentation/devicetree/bindings/arm/ |
| H A D | altera.yaml | 20 - altr,socfpga-arria5-socdk
21 - const: altr,socfpga-arria5
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| /linux/arch/arm/boot/dts/intel/socfpga/ |
| H A D | socfpga_arria5_socdk.dts | 10 compatible = "altr,socfpga-arria5-socdk", "altr,socfpga-arria5", "altr,socfpga";
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | altr,socfpga-stmmac.yaml | 14 Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, Agilex5 and Agilex7
126 On Cyclone5/Arria5, the register shift represents the PHY mode
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| /linux/Documentation/devicetree/bindings/reset/ |
| H A D | altr,rst-mgr.yaml | 15 - description: Cyclone5/Arria5/Arria10
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| /linux/Documentation/devicetree/bindings/arm/altera/ |
| H A D | socfpga-clk-manager.yaml | 14 tree of clocks, pll's, and clock gates for the Cyclone5, Arria5 and Arria10
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| /linux/drivers/edac/ |
| H A D | altera_edac.h | 197 /******* Cyclone5 and Arria5 Defines *******/
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| H A D | altera_edac.c | 1726 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
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