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/linux/Documentation/devicetree/bindings/net/pcs/
H A Dsnps,dw-xpcs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/pcs/snps,dw-xpcs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Serge Semin <fancer.lancer@gmail.com>
17 optionally synthesized with a vendor-specific interface connected to
21 The PCS CSRs can be accessible either over the Ethernet MDIO bus or directly
22 by means of the APB3/MCI interfaces. In the later case the XPCS can be mapped
28 - description: Synopsys DesignWare XPCS with none or unknown PMA
29 const: snps,dw-xpcs
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/linux/Documentation/devicetree/bindings/hwmon/
H A Dbaikal,bt1-pvt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/hwmon/baikal,bt1-pvt.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 PVT Sensor
11 - Serge Semin <fancer.lancer@gmail.com>
14 Baikal-T1 SoC provides an embedded process, voltage and temperature
17 which may cause the system instability and even damages. The IP-block
19 control wrapper, which provides a MMIO registers-based access to the
20 sensor core functionality (APB3-bus based) and exposes an additional
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/linux/drivers/net/pcs/
H A Dpcs-xpcs-plat.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/pcs/pcs-xpcs.h>
22 #include "pcs-xpcs.h"
29 struct mii_bus *bus; member
62 ret = pm_runtime_resume_and_get(&pxpcs->pdev->dev); in xpcs_mmio_read_reg_indirect()
66 switch (pxpcs->reg_width) { in xpcs_mmio_read_reg_indirect()
68 writel(page, pxpcs->reg_base + (DW_VR_CSR_VIEWPORT << 2)); in xpcs_mmio_read_reg_indirect()
69 ret = readl(pxpcs->reg_base + (ofs << 2)); in xpcs_mmio_read_reg_indirect()
72 writew(page, pxpcs->reg_base + (DW_VR_CSR_VIEWPORT << 1)); in xpcs_mmio_read_reg_indirect()
73 ret = readw(pxpcs->reg_base + (ofs << 1)); in xpcs_mmio_read_reg_indirect()
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/linux/drivers/hwmon/
H A Dbt1-pvt.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 Process, Voltage, Temperature sensor driver
18 #include <linux/hwmon-sysfs.h>
34 #include "bt1-pvt.h"
44 PVT_SENSOR_INFO(1, "CPU Core Low-Vt", hwmon_in, LVT, LTHRES),
45 PVT_SENSOR_INFO(2, "CPU Core High-Vt", hwmon_in, HVT, HTHRES),
46 PVT_SENSOR_INFO(3, "CPU Core Standard-Vt", hwmon_in, SVT, STHRES),
51 * to PVT data and vice-versa are following:
52 * N = 1.8322e-8*(T^4) + 2.343e-5*(T^3) + 8.7018e-3*(T^2) + 3.9269*(T^1) +
54 * T = -1.6743e-11*(N^4) + 8.1542e-8*(N^3) + -1.8201e-4*(N^2) +
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/linux/drivers/clk/
H A Dclk-stm32h7.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/stm32h7-clks.h>
139 /* Micro-controller output clock parent */
178 bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy)); in ready_gate_clk_enable()
183 } while (bit_status && --timeout); in ready_gate_clk_enable()
201 bit_status = !!(readl(gate->reg) & BIT(rgate->bit_rdy)); in ready_gate_clk_disable()
206 } while (bit_status && --timeout); in ready_gate_clk_disable()
227 return ERR_PTR(-ENOMEM); in clk_register_ready_gate()
235 rgate->bit_rdy = bit_rdy; in clk_register_ready_gate()
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/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-dev.c9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
125 #include "xgbe-common.h"
129 return pdata->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; in xgbe_get_max_frame()
138 DBGPR("-->xgbe_usec_to_riwt\n"); in xgbe_usec_to_riwt()
140 rate = pdata->sysclk_rate; in xgbe_usec_to_riwt()
150 DBGPR("<--xgbe_usec_to_riwt\n"); in xgbe_usec_to_riwt()
161 DBGPR("-->xgbe_riwt_to_usec\n"); in xgbe_riwt_to_usec()
163 rate = pdata->sysclk_rate; in xgbe_riwt_to_usec()
173 DBGPR("<--xgbe_riwt_to_usec\n"); in xgbe_riwt_to_usec()
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