1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,qcs615-camcc.h> 8#include <dt-bindings/clock/qcom,qcs615-dispcc.h> 9#include <dt-bindings/clock/qcom,qcs615-gcc.h> 10#include <dt-bindings/clock/qcom,qcs615-gpucc.h> 11#include <dt-bindings/clock/qcom,qcs615-videocc.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a55"; 35 reg = <0x0 0x0>; 36 enable-method = "psci"; 37 power-domains = <&cpu_pd0>; 38 power-domain-names = "psci"; 39 capacity-dmips-mhz = <1024>; 40 dynamic-power-coefficient = <100>; 41 next-level-cache = <&l2_0>; 42 clocks = <&cpufreq_hw 0>; 43 qcom,freq-domain = <&cpufreq_hw 0>; 44 #cooling-cells = <2>; 45 operating-points-v2 = <&cpu0_opp_table>; 46 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 47 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 48 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 49 50 l2_0: l2-cache { 51 compatible = "cache"; 52 cache-level = <2>; 53 cache-unified; 54 next-level-cache = <&l3_0>; 55 }; 56 }; 57 58 cpu1: cpu@100 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a55"; 61 reg = <0x0 0x100>; 62 enable-method = "psci"; 63 power-domains = <&cpu_pd1>; 64 power-domain-names = "psci"; 65 capacity-dmips-mhz = <1024>; 66 dynamic-power-coefficient = <100>; 67 next-level-cache = <&l2_100>; 68 clocks = <&cpufreq_hw 0>; 69 qcom,freq-domain = <&cpufreq_hw 0>; 70 operating-points-v2 = <&cpu0_opp_table>; 71 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 72 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 73 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 74 75 l2_100: l2-cache { 76 compatible = "cache"; 77 cache-level = <2>; 78 cache-unified; 79 next-level-cache = <&l3_0>; 80 }; 81 }; 82 83 cpu2: cpu@200 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a55"; 86 reg = <0x0 0x200>; 87 enable-method = "psci"; 88 power-domains = <&cpu_pd2>; 89 power-domain-names = "psci"; 90 capacity-dmips-mhz = <1024>; 91 dynamic-power-coefficient = <100>; 92 next-level-cache = <&l2_200>; 93 clocks = <&cpufreq_hw 0>; 94 qcom,freq-domain = <&cpufreq_hw 0>; 95 operating-points-v2 = <&cpu0_opp_table>; 96 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 97 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 98 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 99 100 l2_200: l2-cache { 101 compatible = "cache"; 102 cache-level = <2>; 103 cache-unified; 104 next-level-cache = <&l3_0>; 105 }; 106 }; 107 108 cpu3: cpu@300 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a55"; 111 reg = <0x0 0x300>; 112 enable-method = "psci"; 113 power-domains = <&cpu_pd3>; 114 power-domain-names = "psci"; 115 capacity-dmips-mhz = <1024>; 116 dynamic-power-coefficient = <100>; 117 next-level-cache = <&l2_300>; 118 clocks = <&cpufreq_hw 0>; 119 qcom,freq-domain = <&cpufreq_hw 0>; 120 operating-points-v2 = <&cpu0_opp_table>; 121 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 122 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 123 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 124 125 l2_300: l2-cache { 126 compatible = "cache"; 127 cache-level = <2>; 128 cache-unified; 129 next-level-cache = <&l3_0>; 130 }; 131 }; 132 133 cpu4: cpu@400 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a55"; 136 reg = <0x0 0x400>; 137 enable-method = "psci"; 138 power-domains = <&cpu_pd4>; 139 power-domain-names = "psci"; 140 capacity-dmips-mhz = <1024>; 141 dynamic-power-coefficient = <100>; 142 next-level-cache = <&l2_400>; 143 clocks = <&cpufreq_hw 0>; 144 qcom,freq-domain = <&cpufreq_hw 0>; 145 operating-points-v2 = <&cpu0_opp_table>; 146 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 147 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 148 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 149 150 l2_400: l2-cache { 151 compatible = "cache"; 152 cache-level = <2>; 153 cache-unified; 154 next-level-cache = <&l3_0>; 155 }; 156 }; 157 158 cpu5: cpu@500 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a55"; 161 reg = <0x0 0x500>; 162 enable-method = "psci"; 163 power-domains = <&cpu_pd5>; 164 power-domain-names = "psci"; 165 capacity-dmips-mhz = <1024>; 166 dynamic-power-coefficient = <100>; 167 next-level-cache = <&l2_500>; 168 clocks = <&cpufreq_hw 0>; 169 qcom,freq-domain = <&cpufreq_hw 0>; 170 operating-points-v2 = <&cpu0_opp_table>; 171 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 172 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 173 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 174 175 l2_500: l2-cache { 176 compatible = "cache"; 177 cache-level = <2>; 178 cache-unified; 179 next-level-cache = <&l3_0>; 180 }; 181 }; 182 183 cpu6: cpu@600 { 184 device_type = "cpu"; 185 compatible = "arm,cortex-a76"; 186 reg = <0x0 0x600>; 187 enable-method = "psci"; 188 power-domains = <&cpu_pd6>; 189 power-domain-names = "psci"; 190 capacity-dmips-mhz = <1740>; 191 dynamic-power-coefficient = <404>; 192 next-level-cache = <&l2_600>; 193 clocks = <&cpufreq_hw 1>; 194 qcom,freq-domain = <&cpufreq_hw 1>; 195 #cooling-cells = <2>; 196 operating-points-v2 = <&cpu6_opp_table>; 197 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 198 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 199 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 200 201 l2_600: l2-cache { 202 compatible = "cache"; 203 cache-level = <2>; 204 cache-unified; 205 next-level-cache = <&l3_0>; 206 }; 207 }; 208 209 cpu7: cpu@700 { 210 device_type = "cpu"; 211 compatible = "arm,cortex-a76"; 212 reg = <0x0 0x700>; 213 enable-method = "psci"; 214 power-domains = <&cpu_pd7>; 215 power-domain-names = "psci"; 216 capacity-dmips-mhz = <1740>; 217 dynamic-power-coefficient = <404>; 218 next-level-cache = <&l2_700>; 219 clocks = <&cpufreq_hw 1>; 220 qcom,freq-domain = <&cpufreq_hw 1>; 221 operating-points-v2 = <&cpu6_opp_table>; 222 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 223 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 224 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 225 226 l2_700: l2-cache { 227 compatible = "cache"; 228 cache-level = <2>; 229 cache-unified; 230 next-level-cache = <&l3_0>; 231 }; 232 }; 233 234 cpu-map { 235 cluster0 { 236 core0 { 237 cpu = <&cpu0>; 238 }; 239 240 core1 { 241 cpu = <&cpu1>; 242 }; 243 244 core2 { 245 cpu = <&cpu2>; 246 }; 247 248 core3 { 249 cpu = <&cpu3>; 250 }; 251 252 core4 { 253 cpu = <&cpu4>; 254 }; 255 256 core5 { 257 cpu = <&cpu5>; 258 }; 259 260 core6 { 261 cpu = <&cpu6>; 262 }; 263 264 core7 { 265 cpu = <&cpu7>; 266 }; 267 }; 268 }; 269 270 l3_0: l3-cache { 271 compatible = "cache"; 272 cache-level = <3>; 273 cache-unified; 274 }; 275 }; 276 277 cpu0_opp_table: opp-table-cpu0 { 278 compatible = "operating-points-v2"; 279 opp-shared; 280 281 opp-300000000 { 282 opp-hz = /bits/ 64 <300000000>; 283 opp-peak-kBps = <(300000 * 4) (300000 * 16)>; 284 }; 285 286 opp-576000000 { 287 opp-hz = /bits/ 64 <576000000>; 288 opp-peak-kBps = <(300000 * 4) (576000 * 16)>; 289 }; 290 291 opp-748800000 { 292 opp-hz = /bits/ 64 <748800000>; 293 opp-peak-kBps = <(300000 * 4) (576000 * 16)>; 294 }; 295 296 opp-998400000 { 297 opp-hz = /bits/ 64 <998400000>; 298 opp-peak-kBps = <(451000 * 4) (806400 * 16)>; 299 }; 300 301 opp-1209600000 { 302 opp-hz = /bits/ 64 <1209600000>; 303 opp-peak-kBps = <(547000 * 4) (1017600 * 16)>; 304 }; 305 306 opp-1363200000 { 307 opp-hz = /bits/ 64 <1363200000>; 308 opp-peak-kBps = <(768000 * 4) (1209600 * 16)>; 309 }; 310 311 opp-1516800000 { 312 opp-hz = /bits/ 64 <1516800000>; 313 opp-peak-kBps = <(768000 * 4) (1209600 * 16)>; 314 }; 315 316 opp-1593600000 { 317 opp-hz = /bits/ 64 <1593600000>; 318 opp-peak-kBps = <(1017000 * 4) (1363200 * 16)>; 319 }; 320 }; 321 322 cpu6_opp_table: opp-table-cpu6 { 323 compatible = "operating-points-v2"; 324 opp-shared; 325 326 opp-300000000 { 327 opp-hz = /bits/ 64 <300000000>; 328 opp-peak-kBps = <(451000 * 4) (300000 * 16)>; 329 }; 330 331 opp-652800000 { 332 opp-hz = /bits/ 64 <652800000>; 333 opp-peak-kBps = <(451000 * 4) (576000 * 16)>; 334 }; 335 336 opp-768000000 { 337 opp-hz = /bits/ 64 <768000000>; 338 opp-peak-kBps = <(451000 * 4) (576000 * 16)>; 339 }; 340 341 opp-979200000 { 342 opp-hz = /bits/ 64 <979200000>; 343 opp-peak-kBps = <(547000 * 4) (806400 * 16)>; 344 }; 345 346 opp-1017600000 { 347 opp-hz = /bits/ 64 <1017600000>; 348 opp-peak-kBps = <(547000 * 4) (806400 * 16)>; 349 }; 350 351 opp-1094400000 { 352 opp-hz = /bits/ 64 <109440000>; 353 opp-peak-kBps = <(1017600 * 4) (940800 * 16)>; 354 }; 355 356 opp-1209600000 { 357 opp-hz = /bits/ 64 <1209600000>; 358 opp-peak-kBps = <(1017600 * 4) (1017600 * 16)>; 359 }; 360 361 opp-1363200000 { 362 opp-hz = /bits/ 64 <1363200000>; 363 opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>; 364 }; 365 366 opp-1516800000 { 367 opp-hz = /bits/ 64 <1516800000>; 368 opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>; 369 }; 370 371 opp-1708800000 { 372 opp-hz = /bits/ 64 <1708800000>; 373 opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>; 374 }; 375 376 opp-1900800000 { 377 opp-hz = /bits/ 64 <1900800000>; 378 opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>; 379 }; 380 }; 381 382 dummy_eud: dummy-sink { 383 compatible = "arm,coresight-dummy-sink"; 384 385 in-ports { 386 port { 387 eud_in: endpoint { 388 remote-endpoint = <&replicator_swao_out1>; 389 }; 390 }; 391 }; 392 }; 393 394 idle-states { 395 entry-method = "psci"; 396 397 little_cpu_sleep_0: cpu-sleep-0-0 { 398 compatible = "arm,idle-state"; 399 idle-state-name = "silver-power-collapse"; 400 arm,psci-suspend-param = <0x40000003>; 401 entry-latency-us = <549>; 402 exit-latency-us = <901>; 403 min-residency-us = <1774>; 404 local-timer-stop; 405 }; 406 407 little_cpu_sleep_1: cpu-sleep-0-1 { 408 compatible = "arm,idle-state"; 409 idle-state-name = "silver-rail-power-collapse"; 410 arm,psci-suspend-param = <0x40000004>; 411 entry-latency-us = <702>; 412 exit-latency-us = <915>; 413 min-residency-us = <4001>; 414 local-timer-stop; 415 }; 416 417 big_cpu_sleep_0: cpu-sleep-1-0 { 418 compatible = "arm,idle-state"; 419 idle-state-name = "gold-power-collapse"; 420 arm,psci-suspend-param = <0x40000003>; 421 entry-latency-us = <523>; 422 exit-latency-us = <1244>; 423 min-residency-us = <2207>; 424 local-timer-stop; 425 }; 426 427 big_cpu_sleep_1: cpu-sleep-1-1 { 428 compatible = "arm,idle-state"; 429 idle-state-name = "gold-rail-power-collapse"; 430 arm,psci-suspend-param = <0x40000004>; 431 entry-latency-us = <526>; 432 exit-latency-us = <1854>; 433 min-residency-us = <5555>; 434 local-timer-stop; 435 }; 436 }; 437 438 domain-idle-states { 439 cluster_sleep_0: cluster-sleep-0 { 440 compatible = "domain-idle-state"; 441 arm,psci-suspend-param = <0x41000044>; 442 entry-latency-us = <2752>; 443 exit-latency-us = <3048>; 444 min-residency-us = <6118>; 445 }; 446 447 cluster_sleep_1: cluster-sleep-1 { 448 compatible = "domain-idle-state"; 449 arm,psci-suspend-param = <0x41001344>; 450 entry-latency-us = <3263>; 451 exit-latency-us = <4562>; 452 min-residency-us = <8467>; 453 }; 454 455 cluster_sleep_2: cluster-sleep-2 { 456 compatible = "domain-idle-state"; 457 arm,psci-suspend-param = <0x4100b344>; 458 entry-latency-us = <3638>; 459 exit-latency-us = <6562>; 460 min-residency-us = <9826>; 461 }; 462 }; 463 464 memory@80000000 { 465 device_type = "memory"; 466 /* We expect the bootloader to fill in the size */ 467 reg = <0 0x80000000 0 0>; 468 }; 469 470 firmware { 471 scm { 472 compatible = "qcom,scm-qcs615", "qcom,scm"; 473 qcom,dload-mode = <&tcsr 0x13000>; 474 }; 475 }; 476 477 camnoc_virt: interconnect-0 { 478 compatible = "qcom,qcs615-camnoc-virt"; 479 #interconnect-cells = <2>; 480 qcom,bcm-voters = <&apps_bcm_voter>; 481 }; 482 483 mc_virt: interconnect-2 { 484 compatible = "qcom,qcs615-mc-virt"; 485 #interconnect-cells = <2>; 486 qcom,bcm-voters = <&apps_bcm_voter>; 487 }; 488 489 smp2p-adsp { 490 compatible = "qcom,smp2p"; 491 qcom,smem = <443>, <429>; 492 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING 0>; 493 /* On this platform, bit 26 (normally SLPI) is repurposed for ADSP */ 494 mboxes = <&apss_shared 26>; 495 496 qcom,local-pid = <0>; 497 qcom,remote-pid = <2>; 498 499 adsp_smp2p_out: master-kernel { 500 qcom,entry-name = "master-kernel"; 501 #qcom,smem-state-cells = <1>; 502 }; 503 504 adsp_smp2p_in: slave-kernel { 505 qcom,entry-name = "slave-kernel"; 506 interrupt-controller; 507 #interrupt-cells = <2>; 508 }; 509 }; 510 511 smp2p-cdsp { 512 compatible = "qcom,smp2p"; 513 qcom,smem = <94>, <432>; 514 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING 0>; 515 mboxes = <&apss_shared 6>; 516 517 qcom,local-pid = <0>; 518 qcom,remote-pid = <5>; 519 520 cdsp_smp2p_out: master-kernel { 521 qcom,entry-name = "master-kernel"; 522 #qcom,smem-state-cells = <1>; 523 }; 524 525 cdsp_smp2p_in: slave-kernel { 526 qcom,entry-name = "slave-kernel"; 527 interrupt-controller; 528 #interrupt-cells = <2>; 529 }; 530 531 }; 532 533 qup_opp_table: opp-table-qup { 534 compatible = "operating-points-v2"; 535 536 opp-75000000 { 537 opp-hz = /bits/ 64 <75000000>; 538 required-opps = <&rpmhpd_opp_low_svs>; 539 }; 540 541 opp-100000000 { 542 opp-hz = /bits/ 64 <100000000>; 543 required-opps = <&rpmhpd_opp_svs>; 544 }; 545 546 opp-128000000 { 547 opp-hz = /bits/ 64 <128000000>; 548 required-opps = <&rpmhpd_opp_nom>; 549 }; 550 }; 551 552 pmu-a55 { 553 compatible = "arm,cortex-a55-pmu"; 554 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 555 }; 556 557 pmu-a76 { 558 compatible = "arm,cortex-a76-pmu"; 559 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 560 }; 561 562 psci { 563 compatible = "arm,psci-1.0"; 564 method = "smc"; 565 566 cpu_pd0: power-domain-cpu0 { 567 #power-domain-cells = <0>; 568 power-domains = <&cluster_pd>; 569 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 570 }; 571 572 cpu_pd1: power-domain-cpu1 { 573 #power-domain-cells = <0>; 574 power-domains = <&cluster_pd>; 575 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 576 }; 577 578 cpu_pd2: power-domain-cpu2 { 579 #power-domain-cells = <0>; 580 power-domains = <&cluster_pd>; 581 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 582 }; 583 584 cpu_pd3: power-domain-cpu3 { 585 #power-domain-cells = <0>; 586 power-domains = <&cluster_pd>; 587 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 588 }; 589 590 cpu_pd4: power-domain-cpu4 { 591 #power-domain-cells = <0>; 592 power-domains = <&cluster_pd>; 593 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 594 }; 595 596 cpu_pd5: power-domain-cpu5 { 597 #power-domain-cells = <0>; 598 power-domains = <&cluster_pd>; 599 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 600 }; 601 602 cpu_pd6: power-domain-cpu6 { 603 #power-domain-cells = <0>; 604 power-domains = <&cluster_pd>; 605 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 606 }; 607 608 cpu_pd7: power-domain-cpu7 { 609 #power-domain-cells = <0>; 610 power-domains = <&cluster_pd>; 611 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 612 }; 613 614 cluster_pd: power-domain-cluster { 615 #power-domain-cells = <0>; 616 domain-idle-states = <&cluster_sleep_0 617 &cluster_sleep_1 618 &cluster_sleep_2>; 619 }; 620 }; 621 622 reserved-memory { 623 #address-cells = <2>; 624 #size-cells = <2>; 625 ranges; 626 627 aop_cmd_db_mem: aop-cmd-db@85f20000 { 628 compatible = "qcom,cmd-db"; 629 reg = <0x0 0x85f20000 0x0 0x20000>; 630 no-map; 631 }; 632 633 smem_region: smem@86000000 { 634 compatible = "qcom,smem"; 635 reg = <0x0 0x86000000 0x0 0x200000>; 636 no-map; 637 hwlocks = <&tcsr_mutex 3>; 638 }; 639 640 pil_video_mem: pil-video@93400000 { 641 reg = <0x0 0x93400000 0x0 0x500000>; 642 no-map; 643 }; 644 645 rproc_cdsp_mem: rproc-cdsp@93b00000 { 646 reg = <0x0 0x93b00000 0x0 0x1e00000>; 647 no-map; 648 }; 649 650 rproc_adsp_mem: rproc-adsp@95900000 { 651 reg = <0x0 0x95900000 0x0 0x1e00000>; 652 no-map; 653 }; 654 }; 655 656 soc: soc@0 { 657 compatible = "simple-bus"; 658 ranges = <0 0 0 0 0x10 0>; 659 dma-ranges = <0 0 0 0 0x10 0>; 660 #address-cells = <2>; 661 #size-cells = <2>; 662 663 gcc: clock-controller@100000 { 664 compatible = "qcom,qcs615-gcc"; 665 reg = <0 0x00100000 0 0x1f0000>; 666 clocks = <&rpmhcc RPMH_CXO_CLK>, 667 <&rpmhcc RPMH_CXO_CLK_A>, 668 <&sleep_clk>; 669 670 #clock-cells = <1>; 671 #reset-cells = <1>; 672 #power-domain-cells = <1>; 673 }; 674 675 qfprom: efuse@780000 { 676 compatible = "qcom,qcs615-qfprom", "qcom,qfprom"; 677 reg = <0x0 0x00780000 0x0 0x7000>; 678 #address-cells = <1>; 679 #size-cells = <1>; 680 681 qusb2_hstx_trim: hstx-trim@1f8 { 682 reg = <0x1fb 0x1>; 683 bits = <1 4>; 684 }; 685 }; 686 687 rng@793000 { 688 compatible = "qcom,qcs615-trng", "qcom,trng"; 689 reg = <0x0 0x00793000 0x0 0x1000>; 690 }; 691 692 sdhc_1: mmc@7c4000 { 693 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; 694 reg = <0x0 0x007c4000 0x0 0x1000>, 695 <0x0 0x007c5000 0x0 0x1000>, 696 <0x0 0x007c8000 0x0 0x8000>; 697 reg-names = "hc", 698 "cqhci", 699 "ice"; 700 701 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>, 702 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 703 interrupt-names = "hc_irq", 704 "pwr_irq"; 705 706 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 707 <&gcc GCC_SDCC1_APPS_CLK>, 708 <&rpmhcc RPMH_CXO_CLK>, 709 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 710 clock-names = "iface", 711 "core", 712 "xo", 713 "ice"; 714 715 resets = <&gcc GCC_SDCC1_BCR>; 716 717 power-domains = <&rpmhpd RPMHPD_CX>; 718 operating-points-v2 = <&sdhc1_opp_table>; 719 iommus = <&apps_smmu 0x02c0 0x0>; 720 interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS 721 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 722 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 723 &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 724 interconnect-names = "sdhc-ddr", 725 "cpu-sdhc"; 726 727 qcom,dll-config = <0x000f642c>; 728 qcom,ddr-config = <0x80040868>; 729 supports-cqe; 730 dma-coherent; 731 732 status = "disabled"; 733 734 sdhc1_opp_table: opp-table { 735 compatible = "operating-points-v2"; 736 737 opp-50000000 { 738 opp-hz = /bits/ 64 <50000000>; 739 required-opps = <&rpmhpd_opp_low_svs>; 740 }; 741 742 opp-100000000 { 743 opp-hz = /bits/ 64 <100000000>; 744 required-opps = <&rpmhpd_opp_svs>; 745 }; 746 747 opp-200000000 { 748 opp-hz = /bits/ 64 <200000000>; 749 required-opps = <&rpmhpd_opp_svs_l1>; 750 }; 751 752 opp-384000000 { 753 opp-hz = /bits/ 64 <384000000>; 754 required-opps = <&rpmhpd_opp_nom>; 755 }; 756 }; 757 }; 758 759 gpi_dma0: dma-controller@800000 { 760 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; 761 reg = <0x0 0x800000 0x0 0x60000>; 762 #dma-cells = <3>; 763 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>, 764 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, 765 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, 766 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, 767 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, 768 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>, 769 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, 770 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; 771 dma-channels = <8>; 772 dma-channel-mask = <0xf>; 773 iommus = <&apps_smmu 0xd6 0x0>; 774 status = "disabled"; 775 }; 776 777 qupv3_id_0: geniqup@8c0000 { 778 compatible = "qcom,geni-se-qup"; 779 reg = <0x0 0x008c0000 0x0 0x6000>; 780 ranges; 781 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 782 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 783 clock-names = "m-ahb", 784 "s-ahb"; 785 iommus = <&apps_smmu 0xc3 0x0>; 786 #address-cells = <2>; 787 #size-cells = <2>; 788 status = "disabled"; 789 790 uart0: serial@880000 { 791 compatible = "qcom,geni-debug-uart"; 792 reg = <0x0 0x00880000 0x0 0x4000>; 793 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 794 clock-names = "se"; 795 pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>; 796 pinctrl-names = "default"; 797 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH 0>; 798 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 799 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 800 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 801 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 802 interconnect-names = "qup-core", 803 "qup-config"; 804 power-domains = <&rpmhpd RPMHPD_CX>; 805 operating-points-v2 = <&qup_opp_table>; 806 status = "disabled"; 807 }; 808 809 i2c1: i2c@884000 { 810 compatible = "qcom,geni-i2c"; 811 reg = <0x0 0x884000 0x0 0x4000>; 812 #address-cells = <1>; 813 #size-cells = <0>; 814 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH 0>; 815 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 816 clock-names = "se"; 817 pinctrl-0 = <&qup_i2c1_data_clk>; 818 pinctrl-names = "default"; 819 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 820 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 821 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 822 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 823 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 824 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 825 interconnect-names = "qup-core", 826 "qup-config", 827 "qup-memory"; 828 power-domains = <&rpmhpd RPMHPD_CX>; 829 required-opps = <&rpmhpd_opp_low_svs>; 830 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 831 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 832 dma-names = "tx", 833 "rx"; 834 status = "disabled"; 835 }; 836 837 i2c2: i2c@888000 { 838 compatible = "qcom,geni-i2c"; 839 reg = <0x0 0x888000 0x0 0x4000>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>; 843 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 844 clock-names = "se"; 845 pinctrl-0 = <&qup_i2c2_data_clk>; 846 pinctrl-names = "default"; 847 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 848 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 849 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 850 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 851 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 852 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 853 interconnect-names = "qup-core", 854 "qup-config", 855 "qup-memory"; 856 power-domains = <&rpmhpd RPMHPD_CX>; 857 required-opps = <&rpmhpd_opp_low_svs>; 858 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 859 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 860 dma-names = "tx", 861 "rx"; 862 status = "disabled"; 863 }; 864 865 spi2: spi@888000 { 866 compatible = "qcom,geni-spi"; 867 reg = <0x0 0x00888000 0x0 0x4000>; 868 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>; 869 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 870 clock-names = "se"; 871 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 872 pinctrl-names = "default"; 873 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 874 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 875 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 876 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 877 interconnect-names = "qup-core", 878 "qup-config"; 879 power-domains = <&rpmhpd RPMHPD_CX>; 880 operating-points-v2 = <&qup_opp_table>; 881 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 882 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 883 dma-names = "tx", 884 "rx"; 885 #address-cells = <1>; 886 #size-cells = <0>; 887 status = "disabled"; 888 }; 889 890 uart2: serial@888000 { 891 compatible = "qcom,geni-uart"; 892 reg = <0x0 0x00888000 0x0 0x4000>; 893 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>; 894 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 895 clock-names = "se"; 896 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, 897 <&qup_uart2_tx>, <&qup_uart2_rx>; 898 pinctrl-names = "default"; 899 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 900 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 901 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 902 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 903 interconnect-names = "qup-core", 904 "qup-config"; 905 power-domains = <&rpmhpd RPMHPD_CX>; 906 operating-points-v2 = <&qup_opp_table>; 907 status = "disabled"; 908 }; 909 910 i2c3: i2c@88c000 { 911 compatible = "qcom,geni-i2c"; 912 reg = <0x0 0x88c000 0x0 0x4000>; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>; 916 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 917 clock-names = "se"; 918 pinctrl-0 = <&qup_i2c3_data_clk>; 919 pinctrl-names = "default"; 920 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 921 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 922 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 923 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 924 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 925 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 926 interconnect-names = "qup-core", 927 "qup-config", 928 "qup-memory"; 929 power-domains = <&rpmhpd RPMHPD_CX>; 930 required-opps = <&rpmhpd_opp_low_svs>; 931 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 932 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 933 dma-names = "tx", 934 "rx"; 935 status = "disabled"; 936 }; 937 }; 938 939 gpi_dma1: dma-controller@a00000 { 940 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; 941 reg = <0x0 0xa00000 0x0 0x60000>; 942 #dma-cells = <3>; 943 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>, 944 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>, 945 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>, 946 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>, 947 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>, 948 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH 0>, 949 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>, 950 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; 951 dma-channels = <8>; 952 dma-channel-mask = <0xf>; 953 iommus = <&apps_smmu 0x376 0x0>; 954 status = "disabled"; 955 }; 956 957 qupv3_id_1: geniqup@ac0000 { 958 compatible = "qcom,geni-se-qup"; 959 reg = <0x0 0xac0000 0x0 0x2000>; 960 ranges; 961 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 962 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 963 clock-names = "m-ahb", 964 "s-ahb"; 965 iommus = <&apps_smmu 0x363 0x0>; 966 #address-cells = <2>; 967 #size-cells = <2>; 968 status = "disabled"; 969 970 i2c4: i2c@a80000 { 971 compatible = "qcom,geni-i2c"; 972 reg = <0x0 0xa80000 0x0 0x4000>; 973 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 974 clock-names = "se"; 975 pinctrl-0 = <&qup_i2c4_data_clk>; 976 pinctrl-names = "default"; 977 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 981 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 982 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 983 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 984 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 985 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 986 interconnect-names = "qup-core", 987 "qup-config", 988 "qup-memory"; 989 power-domains = <&rpmhpd RPMHPD_CX>; 990 required-opps = <&rpmhpd_opp_low_svs>; 991 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 992 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 993 dma-names = "tx", 994 "rx"; 995 status = "disabled"; 996 }; 997 998 spi4: spi@a80000 { 999 compatible = "qcom,geni-spi"; 1000 reg = <0x0 0xa80000 0x0 0x4000>; 1001 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1002 clock-names = "se"; 1003 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1004 pinctrl-names = "default"; 1005 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1009 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1010 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1011 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1012 interconnect-names = "qup-core", 1013 "qup-config"; 1014 power-domains = <&rpmhpd RPMHPD_CX>; 1015 operating-points-v2 = <&qup_opp_table>; 1016 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1017 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1018 dma-names = "tx", 1019 "rx"; 1020 status = "disabled"; 1021 }; 1022 1023 uart4: serial@a80000 { 1024 compatible = "qcom,geni-uart"; 1025 reg = <0x0 0xa80000 0x0 0x4000>; 1026 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1027 clock-names = "se"; 1028 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, 1029 <&qup_uart4_tx>, <&qup_uart4_rx>; 1030 pinctrl-names = "default"; 1031 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 1032 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1033 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1034 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1035 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1036 interconnect-names = "qup-core", 1037 "qup-config"; 1038 power-domains = <&rpmhpd RPMHPD_CX>; 1039 operating-points-v2 = <&qup_opp_table>; 1040 status = "disabled"; 1041 }; 1042 1043 i2c5: i2c@a84000 { 1044 compatible = "qcom,geni-i2c"; 1045 reg = <0x0 0xa84000 0x0 0x4000>; 1046 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1047 clock-names = "se"; 1048 pinctrl-0 = <&qup_i2c5_data_clk>; 1049 pinctrl-names = "default"; 1050 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1054 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1055 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1056 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1057 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1058 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1059 interconnect-names = "qup-core", 1060 "qup-config", 1061 "qup-memory"; 1062 power-domains = <&rpmhpd RPMHPD_CX>; 1063 required-opps = <&rpmhpd_opp_low_svs>; 1064 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1065 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1066 dma-names = "tx", 1067 "rx"; 1068 status = "disabled"; 1069 }; 1070 1071 i2c6: i2c@a88000 { 1072 compatible = "qcom,geni-i2c"; 1073 reg = <0x0 0xa88000 0x0 0x4000>; 1074 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1075 clock-names = "se"; 1076 pinctrl-0 = <&qup_i2c6_data_clk>; 1077 pinctrl-names = "default"; 1078 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1082 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1083 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1084 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1085 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1086 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1087 interconnect-names = "qup-core", 1088 "qup-config", 1089 "qup-memory"; 1090 power-domains = <&rpmhpd RPMHPD_CX>; 1091 required-opps = <&rpmhpd_opp_low_svs>; 1092 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1093 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1094 dma-names = "tx", 1095 "rx"; 1096 status = "disabled"; 1097 }; 1098 1099 spi6: spi@a88000 { 1100 compatible = "qcom,geni-spi"; 1101 reg = <0x0 0xa88000 0x0 0x4000>; 1102 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1103 clock-names = "se"; 1104 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1105 pinctrl-names = "default"; 1106 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1110 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1111 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1112 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1113 interconnect-names = "qup-core", 1114 "qup-config"; 1115 power-domains = <&rpmhpd RPMHPD_CX>; 1116 operating-points-v2 = <&qup_opp_table>; 1117 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1118 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1119 dma-names = "tx", 1120 "rx"; 1121 status = "disabled"; 1122 }; 1123 1124 uart6: serial@a88000 { 1125 compatible = "qcom,geni-uart"; 1126 reg = <0x0 0xa88000 0x0 0x4000>; 1127 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1128 clock-names = "se"; 1129 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, 1130 <&qup_uart6_tx>, <&qup_uart6_rx>; 1131 pinctrl-names = "default"; 1132 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1133 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1134 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1135 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1136 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1137 interconnect-names = "qup-core", 1138 "qup-config"; 1139 power-domains = <&rpmhpd RPMHPD_CX>; 1140 operating-points-v2 = <&qup_opp_table>; 1141 status = "disabled"; 1142 }; 1143 1144 i2c7: i2c@a8c000 { 1145 compatible = "qcom,geni-i2c"; 1146 reg = <0x0 0xa8c000 0x0 0x4000>; 1147 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1148 clock-names = "se"; 1149 pinctrl-0 = <&qup_i2c7_data_clk>; 1150 pinctrl-names = "default"; 1151 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1152 #address-cells = <1>; 1153 #size-cells = <0>; 1154 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1155 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1156 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1157 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1158 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1159 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1160 interconnect-names = "qup-core", 1161 "qup-config", 1162 "qup-memory"; 1163 power-domains = <&rpmhpd RPMHPD_CX>; 1164 required-opps = <&rpmhpd_opp_low_svs>; 1165 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1166 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1167 dma-names = "tx", 1168 "rx"; 1169 status = "disabled"; 1170 }; 1171 1172 spi7: spi@a8c000 { 1173 compatible = "qcom,geni-spi"; 1174 reg = <0x0 0xa8c000 0x0 0x4000>; 1175 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1176 clock-names = "se"; 1177 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1178 pinctrl-names = "default"; 1179 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1183 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1184 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1185 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1186 interconnect-names = "qup-core", 1187 "qup-config"; 1188 power-domains = <&rpmhpd RPMHPD_CX>; 1189 operating-points-v2 = <&qup_opp_table>; 1190 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1191 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1192 dma-names = "tx", 1193 "rx"; 1194 status = "disabled"; 1195 }; 1196 1197 uart7: serial@a8c000 { 1198 compatible = "qcom,geni-uart"; 1199 reg = <0x0 0xa8c000 0x0 0x4000>; 1200 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1201 clock-names = "se"; 1202 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, 1203 <&qup_uart7_tx>, <&qup_uart7_rx>; 1204 pinctrl-names = "default"; 1205 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1206 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1207 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1208 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1209 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1210 interconnect-names = "qup-core", 1211 "qup-config"; 1212 power-domains = <&rpmhpd RPMHPD_CX>; 1213 operating-points-v2 = <&qup_opp_table>; 1214 status = "disabled"; 1215 }; 1216 }; 1217 1218 config_noc: interconnect@1500000 { 1219 reg = <0x0 0x01500000 0x0 0x5080>; 1220 compatible = "qcom,qcs615-config-noc"; 1221 #interconnect-cells = <2>; 1222 qcom,bcm-voters = <&apps_bcm_voter>; 1223 }; 1224 1225 system_noc: interconnect@1620000 { 1226 reg = <0x0 0x01620000 0x0 0x1f300>; 1227 compatible = "qcom,qcs615-system-noc"; 1228 #interconnect-cells = <2>; 1229 qcom,bcm-voters = <&apps_bcm_voter>; 1230 }; 1231 1232 aggre1_noc: interconnect@1700000 { 1233 reg = <0x0 0x01700000 0x0 0x3f200>; 1234 compatible = "qcom,qcs615-aggre1-noc"; 1235 #interconnect-cells = <2>; 1236 qcom,bcm-voters = <&apps_bcm_voter>; 1237 }; 1238 1239 mmss_noc: interconnect@1740000 { 1240 reg = <0x0 0x01740000 0x0 0x1c100>; 1241 compatible = "qcom,qcs615-mmss-noc"; 1242 #interconnect-cells = <2>; 1243 qcom,bcm-voters = <&apps_bcm_voter>; 1244 }; 1245 1246 pcie: pcie@1c08000 { 1247 device_type = "pci"; 1248 compatible = "qcom,pcie-qcs615", "qcom,pcie-sm8150"; 1249 reg = <0x0 0x01c08000 0x0 0x3000>, 1250 <0x0 0x40000000 0x0 0xf1d>, 1251 <0x0 0x40000f20 0x0 0xa8>, 1252 <0x0 0x40001000 0x0 0x1000>, 1253 <0x0 0x40100000 0x0 0x100000>, 1254 <0x0 0x01c0b000 0x0 0x1000>; 1255 reg-names = "parf", 1256 "dbi", 1257 "elbi", 1258 "atu", 1259 "config", 1260 "mhi"; 1261 #address-cells = <3>; 1262 #size-cells = <2>; 1263 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1264 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1265 bus-range = <0x00 0xff>; 1266 1267 dma-coherent; 1268 1269 linux,pci-domain = <0>; 1270 num-lanes = <1>; 1271 1272 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>, 1273 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>, 1274 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>, 1275 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>, 1276 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>, 1277 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>, 1278 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>, 1279 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>, 1280 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>; 1281 interrupt-names = "msi0", 1282 "msi1", 1283 "msi2", 1284 "msi3", 1285 "msi4", 1286 "msi5", 1287 "msi6", 1288 "msi7", 1289 "global"; 1290 1291 #interrupt-cells = <1>; 1292 interrupt-map-mask = <0 0 0 0x7>; 1293 interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>, 1294 <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>, 1295 <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>, 1296 <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1297 1298 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1299 <&gcc GCC_PCIE_0_AUX_CLK>, 1300 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1301 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1302 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1303 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 1304 clock-names = "pipe", 1305 "aux", 1306 "cfg", 1307 "bus_master", 1308 "bus_slave", 1309 "slave_q2a"; 1310 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 1311 assigned-clock-rates = <19200000>; 1312 1313 interconnects = <&aggre1_noc MASTER_PCIE QCOM_ICC_TAG_ALWAYS 1314 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1315 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1316 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1317 interconnect-names = "pcie-mem", "cpu-pcie"; 1318 1319 iommu-map = <0x0 &apps_smmu 0x400 0x1>, 1320 <0x100 &apps_smmu 0x401 0x1>; 1321 1322 resets = <&gcc GCC_PCIE_0_BCR>; 1323 reset-names = "pci"; 1324 1325 power-domains = <&gcc PCIE_0_GDSC>; 1326 1327 phys = <&pcie_phy>; 1328 phy-names = "pciephy"; 1329 1330 max-link-speed = <2>; 1331 1332 operating-points-v2 = <&pcie_opp_table>; 1333 1334 status = "disabled"; 1335 1336 pcie_opp_table: opp-table { 1337 compatible = "operating-points-v2"; 1338 1339 /* GEN 1 x1 */ 1340 opp-2500000 { 1341 opp-hz = /bits/ 64 <2500000>; 1342 required-opps = <&rpmhpd_opp_low_svs>; 1343 opp-peak-kBps = <250000 1>; 1344 }; 1345 1346 /* GEN 2 x1 */ 1347 opp-5000000 { 1348 opp-hz = /bits/ 64 <5000000>; 1349 required-opps = <&rpmhpd_opp_low_svs>; 1350 opp-peak-kBps = <500000 1>; 1351 }; 1352 }; 1353 1354 pcie_port0: pcie@0 { 1355 device_type = "pci"; 1356 reg = <0x0 0x0 0x0 0x0 0x0>; 1357 #address-cells = <3>; 1358 #size-cells = <2>; 1359 ranges; 1360 bus-range = <0x01 0xff>; 1361 }; 1362 }; 1363 1364 pcie_phy: phy@1c0e000 { 1365 compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy"; 1366 reg = <0x0 0x01c0e000 0x0 0x1000>; 1367 1368 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1369 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1370 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1371 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1372 <&gcc GCC_PCIE_0_PIPE_CLK>; 1373 clock-names = "aux", 1374 "cfg_ahb", 1375 "ref", 1376 "refgen", 1377 "pipe"; 1378 1379 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1380 reset-names = "phy"; 1381 1382 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1383 assigned-clock-rates = <100000000>; 1384 1385 #clock-cells = <0>; 1386 clock-output-names = "pcie_0_pipe_clk"; 1387 1388 #phy-cells = <0>; 1389 1390 status = "disabled"; 1391 }; 1392 1393 ufs_mem_hc: ufshc@1d84000 { 1394 compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1395 reg = <0x0 0x01d84000 0x0 0x3000>, 1396 <0x0 0x01d90000 0x0 0x8000>; 1397 reg-names = "std", 1398 "ice"; 1399 1400 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 1401 1402 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1403 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1404 <&gcc GCC_UFS_PHY_AHB_CLK>, 1405 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1406 <&rpmhcc RPMH_CXO_CLK>, 1407 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1408 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1409 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1410 clock-names = "core_clk", 1411 "bus_aggr_clk", 1412 "iface_clk", 1413 "core_clk_unipro", 1414 "ref_clk", 1415 "tx_lane0_sync_clk", 1416 "rx_lane0_sync_clk", 1417 "ice_core_clk"; 1418 1419 resets = <&gcc GCC_UFS_PHY_BCR>; 1420 reset-names = "rst"; 1421 1422 operating-points-v2 = <&ufs_opp_table>; 1423 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1424 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1425 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1426 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 1427 interconnect-names = "ufs-ddr", 1428 "cpu-ufs"; 1429 1430 power-domains = <&gcc UFS_PHY_GDSC>; 1431 1432 iommus = <&apps_smmu 0x300 0x0>; 1433 dma-coherent; 1434 1435 lanes-per-direction = <1>; 1436 1437 phys = <&ufs_mem_phy>; 1438 phy-names = "ufsphy"; 1439 1440 #reset-cells = <1>; 1441 1442 status = "disabled"; 1443 1444 ufs_opp_table: opp-table { 1445 compatible = "operating-points-v2"; 1446 1447 opp-50000000 { 1448 opp-hz = /bits/ 64 <50000000>, 1449 /bits/ 64 <0>, 1450 /bits/ 64 <0>, 1451 /bits/ 64 <37500000>, 1452 /bits/ 64 <0>, 1453 /bits/ 64 <0>, 1454 /bits/ 64 <0>, 1455 /bits/ 64 <75000000>; 1456 required-opps = <&rpmhpd_opp_low_svs>; 1457 }; 1458 1459 opp-100000000 { 1460 opp-hz = /bits/ 64 <100000000>, 1461 /bits/ 64 <0>, 1462 /bits/ 64 <0>, 1463 /bits/ 64 <75000000>, 1464 /bits/ 64 <0>, 1465 /bits/ 64 <0>, 1466 /bits/ 64 <0>, 1467 /bits/ 64 <150000000>; 1468 required-opps = <&rpmhpd_opp_svs>; 1469 }; 1470 1471 opp-200000000 { 1472 opp-hz = /bits/ 64 <200000000>, 1473 /bits/ 64 <0>, 1474 /bits/ 64 <0>, 1475 /bits/ 64 <150000000>, 1476 /bits/ 64 <0>, 1477 /bits/ 64 <0>, 1478 /bits/ 64 <0>, 1479 /bits/ 64 <300000000>; 1480 required-opps = <&rpmhpd_opp_nom>; 1481 }; 1482 }; 1483 }; 1484 1485 ufs_mem_phy: phy@1d87000 { 1486 compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy"; 1487 reg = <0x0 0x01d87000 0x0 0xe00>; 1488 clocks = <&rpmhcc RPMH_CXO_CLK>, 1489 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1490 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 1491 clock-names = "ref", 1492 "ref_aux", 1493 "qref"; 1494 1495 power-domains = <&gcc UFS_PHY_GDSC>; 1496 1497 resets = <&ufs_mem_hc 0>; 1498 reset-names = "ufsphy"; 1499 1500 #clock-cells = <1>; 1501 #phy-cells = <0>; 1502 1503 status = "disabled"; 1504 }; 1505 1506 cryptobam: dma-controller@1dc4000 { 1507 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1508 reg = <0x0 0x01dc4000 0x0 0x24000>; 1509 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>; 1510 #dma-cells = <1>; 1511 qcom,ee = <0>; 1512 qcom,controlled-remotely; 1513 num-channels = <16>; 1514 qcom,num-ees = <4>; 1515 iommus = <&apps_smmu 0x0104 0x0011>; 1516 }; 1517 1518 crypto: crypto@1dfa000 { 1519 compatible = "qcom,qcs615-qce", "qcom,sm8150-qce", "qcom,qce"; 1520 reg = <0x0 0x01dfa000 0x0 0x6000>; 1521 dmas = <&cryptobam 4>, <&cryptobam 5>; 1522 dma-names = "rx", "tx"; 1523 iommus = <&apps_smmu 0x0104 0x0011>; 1524 interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 1525 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1526 interconnect-names = "memory"; 1527 }; 1528 1529 tcsr_mutex: hwlock@1f40000 { 1530 compatible = "qcom,tcsr-mutex"; 1531 reg = <0x0 0x01f40000 0x0 0x20000>; 1532 #hwlock-cells = <1>; 1533 }; 1534 1535 tcsr: syscon@1fc0000 { 1536 compatible = "qcom,qcs615-tcsr", "syscon"; 1537 reg = <0x0 0x01fc0000 0x0 0x30000>; 1538 }; 1539 1540 tlmm: pinctrl@3100000 { 1541 compatible = "qcom,qcs615-tlmm"; 1542 reg = <0x0 0x03100000 0x0 0x300000>, 1543 <0x0 0x03500000 0x0 0x300000>, 1544 <0x0 0x03d00000 0x0 0x300000>; 1545 reg-names = "east", 1546 "west", 1547 "south"; 1548 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>; 1549 gpio-ranges = <&tlmm 0 0 124>; 1550 gpio-controller; 1551 #gpio-cells = <2>; 1552 interrupt-controller; 1553 #interrupt-cells = <2>; 1554 wakeup-parent = <&pdc>; 1555 1556 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 1557 pins = "gpio4", "gpio5"; 1558 function = "qup0"; 1559 1560 }; 1561 1562 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 1563 pins = "gpio0", "gpio1"; 1564 function = "qup0"; 1565 }; 1566 1567 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 1568 pins = "gpio18", "gpio19"; 1569 function = "qup0"; 1570 }; 1571 1572 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 1573 pins = "gpio20", "gpio21"; 1574 function = "qup1"; 1575 }; 1576 1577 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 1578 pins = "gpio14", "gpio15"; 1579 function = "qup1"; 1580 }; 1581 1582 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 1583 pins = "gpio6", "gpio7"; 1584 function = "qup1"; 1585 }; 1586 1587 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 1588 pins = "gpio10", "gpio11"; 1589 function = "qup1"; 1590 }; 1591 1592 qup_spi2_data_clk: qup-spi2-data-clk-state { 1593 pins = "gpio0", "gpio1", "gpio2"; 1594 function = "qup0"; 1595 }; 1596 1597 qup_spi2_cs: qup-spi2-cs-state { 1598 pins = "gpio3"; 1599 function = "qup0"; 1600 }; 1601 1602 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 1603 pins = "gpio3"; 1604 function = "gpio"; 1605 }; 1606 1607 qup_spi4_data_clk: qup-spi4-data-clk-state { 1608 pins = "gpio20", "gpio21", "gpio22"; 1609 function = "qup1"; 1610 }; 1611 1612 qup_spi4_cs: qup-spi4-cs-state { 1613 pins = "gpio23"; 1614 function = "qup1"; 1615 }; 1616 1617 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 1618 pins = "gpio23"; 1619 function = "gpio"; 1620 }; 1621 1622 qup_spi6_data_clk: qup-spi6-data-clk-state { 1623 pins = "gpio6", "gpio7", "gpio8"; 1624 function = "qup1"; 1625 }; 1626 1627 qup_spi6_cs: qup-spi6-cs-state { 1628 pins = "gpio9"; 1629 function = "qup1"; 1630 }; 1631 1632 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 1633 pins = "gpio9"; 1634 function = "gpio"; 1635 }; 1636 1637 qup_spi7_data_clk: qup-spi7-data-clk-state { 1638 pins = "gpio10", "gpio11", "gpio12"; 1639 function = "qup1"; 1640 }; 1641 1642 qup_spi7_cs: qup-spi7-cs-state { 1643 pins = "gpio13"; 1644 function = "qup1"; 1645 }; 1646 1647 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 1648 pins = "gpio13"; 1649 function = "gpio"; 1650 }; 1651 1652 qup_uart0_tx: qup-uart0-tx-state { 1653 pins = "gpio16"; 1654 function = "qup0"; 1655 }; 1656 1657 qup_uart0_rx: qup-uart0-rx-state { 1658 pins = "gpio17"; 1659 function = "qup0"; 1660 }; 1661 1662 qup_uart2_cts: qup-uart2-cts-state { 1663 pins = "gpio0"; 1664 function = "qup0"; 1665 }; 1666 1667 qup_uart2_rts: qup-uart2-rts-state { 1668 pins = "gpio1"; 1669 function = "qup0"; 1670 }; 1671 1672 qup_uart2_tx: qup-uart2-tx-state { 1673 pins = "gpio2"; 1674 function = "qup0"; 1675 }; 1676 1677 qup_uart2_rx: qup-uart2-rx-state { 1678 pins = "gpio3"; 1679 function = "qup0"; 1680 }; 1681 1682 qup_uart4_cts: qup-uart4-cts-state { 1683 pins = "gpio20"; 1684 function = "qup1"; 1685 }; 1686 1687 qup_uart4_rts: qup-uart4-rts-state { 1688 pins = "gpio21"; 1689 function = "qup1"; 1690 }; 1691 1692 qup_uart4_tx: qup-uart4-tx-state { 1693 pins = "gpio22"; 1694 function = "qup1"; 1695 }; 1696 1697 qup_uart4_rx: qup-uart4-rx-state { 1698 pins = "gpio23"; 1699 function = "qup1"; 1700 }; 1701 1702 qup_uart6_cts: qup-uart6-cts-state { 1703 pins = "gpio6"; 1704 function = "qup1"; 1705 }; 1706 1707 qup_uart6_rts: qup-uart6-rts-state { 1708 pins = "gpio7"; 1709 function = "qup1"; 1710 }; 1711 1712 qup_uart6_tx: qup-uart6-tx-state { 1713 pins = "gpio8"; 1714 function = "qup1"; 1715 }; 1716 1717 qup_uart6_rx: qup-uart6-rx-state { 1718 pins = "gpio9"; 1719 function = "qup1"; 1720 }; 1721 1722 qup_uart7_cts: qup-uart7-cts-state { 1723 pins = "gpio10"; 1724 function = "qup1"; 1725 }; 1726 1727 qup_uart7_rts: qup-uart7-rts-state { 1728 pins = "gpio11"; 1729 function = "qup1"; 1730 }; 1731 1732 qup_uart7_tx: qup-uart7-tx-state { 1733 pins = "gpio12"; 1734 function = "qup1"; 1735 }; 1736 1737 qup_uart7_rx: qup-uart7-rx-state { 1738 pins = "gpio13"; 1739 function = "qup1"; 1740 }; 1741 1742 sdc1_state_on: sdc1-on-state { 1743 clk-pins { 1744 pins = "sdc1_clk"; 1745 bias-disable; 1746 drive-strength = <16>; 1747 }; 1748 1749 cmd-pins { 1750 pins = "sdc1_cmd"; 1751 bias-pull-up; 1752 drive-strength = <10>; 1753 }; 1754 1755 data-pins { 1756 pins = "sdc1_data"; 1757 bias-pull-up; 1758 drive-strength = <10>; 1759 }; 1760 1761 rclk-pins { 1762 pins = "sdc1_rclk"; 1763 bias-pull-down; 1764 }; 1765 }; 1766 1767 sdc1_state_off: sdc1-off-state { 1768 clk-pins { 1769 pins = "sdc1_clk"; 1770 bias-disable; 1771 drive-strength = <2>; 1772 }; 1773 1774 cmd-pins { 1775 pins = "sdc1_cmd"; 1776 bias-pull-up; 1777 drive-strength = <2>; 1778 }; 1779 1780 data-pins { 1781 pins = "sdc1_data"; 1782 bias-pull-up; 1783 drive-strength = <2>; 1784 }; 1785 1786 rclk-pins { 1787 pins = "sdc1_rclk"; 1788 bias-pull-down; 1789 }; 1790 }; 1791 1792 sdc2_state_on: sdc2-on-state { 1793 clk-pins { 1794 pins = "sdc2_clk"; 1795 bias-disable; 1796 drive-strength = <16>; 1797 }; 1798 1799 cmd-pins { 1800 pins = "sdc2_cmd"; 1801 bias-pull-up; 1802 drive-strength = <10>; 1803 }; 1804 1805 data-pins { 1806 pins = "sdc2_data"; 1807 bias-pull-up; 1808 drive-strength = <10>; 1809 }; 1810 }; 1811 1812 sdc2_state_off: sdc2-off-state { 1813 clk-pins { 1814 pins = "sdc2_clk"; 1815 bias-disable; 1816 drive-strength = <2>; 1817 }; 1818 1819 cmd-pins { 1820 pins = "sdc2_cmd"; 1821 bias-pull-up; 1822 drive-strength = <2>; 1823 }; 1824 1825 data-pins { 1826 pins = "sdc2_data"; 1827 bias-pull-up; 1828 drive-strength = <2>; 1829 }; 1830 }; 1831 }; 1832 1833 gpucc: clock-controller@5090000 { 1834 compatible = "qcom,qcs615-gpucc"; 1835 reg = <0 0x05090000 0 0x9000>; 1836 1837 clocks = <&rpmhcc RPMH_CXO_CLK>, 1838 <&gcc GPLL0>, 1839 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1840 1841 #clock-cells = <1>; 1842 #reset-cells = <1>; 1843 #power-domain-cells = <1>; 1844 }; 1845 1846 stm@6002000 { 1847 compatible = "arm,coresight-stm", "arm,primecell"; 1848 reg = <0x0 0x06002000 0x0 0x1000>, 1849 <0x0 0x16280000 0x0 0x180000>; 1850 reg-names = "stm-base", 1851 "stm-stimulus-base"; 1852 1853 clocks = <&aoss_qmp>; 1854 clock-names = "apb_pclk"; 1855 1856 out-ports { 1857 port { 1858 stm_out: endpoint { 1859 remote-endpoint = <&funnel_in0_in7>; 1860 }; 1861 }; 1862 }; 1863 }; 1864 1865 tpda@6004000 { 1866 compatible = "qcom,coresight-tpda", "arm,primecell"; 1867 reg = <0x0 0x06004000 0x0 0x1000>; 1868 1869 clocks = <&aoss_qmp>; 1870 clock-names = "apb_pclk"; 1871 1872 in-ports { 1873 #address-cells = <1>; 1874 #size-cells = <0>; 1875 1876 port@0 { 1877 reg = <0>; 1878 1879 tpda_qdss_in0: endpoint { 1880 remote-endpoint = <&tpdm_center_out>; 1881 }; 1882 }; 1883 1884 port@4 { 1885 reg = <4>; 1886 1887 tpda_qdss_in4: endpoint { 1888 remote-endpoint = <&funnel_monaq_out>; 1889 }; 1890 }; 1891 1892 port@5 { 1893 reg = <5>; 1894 1895 tpda_qdss_in5: endpoint { 1896 remote-endpoint = <&funnel_ddr_0_out>; 1897 }; 1898 }; 1899 1900 port@6 { 1901 reg = <6>; 1902 1903 tpda_qdss_in6: endpoint { 1904 remote-endpoint = <&funnel_turing_out>; 1905 }; 1906 }; 1907 1908 port@7 { 1909 reg = <7>; 1910 1911 tpda_qdss_in7: endpoint { 1912 remote-endpoint = <&tpdm_vsense_out>; 1913 }; 1914 }; 1915 1916 port@8 { 1917 reg = <8>; 1918 1919 tpda_qdss_in8: endpoint { 1920 remote-endpoint = <&tpdm_dcc_out>; 1921 }; 1922 }; 1923 1924 port@9 { 1925 reg = <9>; 1926 1927 tpda_qdss_in9: endpoint { 1928 remote-endpoint = <&tpdm_prng_out>; 1929 }; 1930 }; 1931 1932 port@b { 1933 reg = <11>; 1934 1935 tpda_qdss_in11: endpoint { 1936 remote-endpoint = <&tpdm_qm_out>; 1937 }; 1938 }; 1939 1940 port@c { 1941 reg = <12>; 1942 1943 tpda_qdss_in12: endpoint { 1944 remote-endpoint = <&tpdm_west_out>; 1945 }; 1946 }; 1947 1948 port@d { 1949 reg = <13>; 1950 1951 tpda_qdss_in13: endpoint { 1952 remote-endpoint = <&tpdm_pimem_out>; 1953 }; 1954 }; 1955 }; 1956 1957 out-ports { 1958 port { 1959 tpda_qdss_out: endpoint { 1960 remote-endpoint = <&funnel_qatb_in>; 1961 }; 1962 }; 1963 }; 1964 }; 1965 1966 funnel@6005000 { 1967 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1968 reg = <0x0 0x06005000 0x0 0x1000>; 1969 1970 clocks = <&aoss_qmp>; 1971 clock-names = "apb_pclk"; 1972 1973 in-ports { 1974 port { 1975 funnel_qatb_in: endpoint { 1976 remote-endpoint = <&tpda_qdss_out>; 1977 }; 1978 }; 1979 }; 1980 1981 out-ports { 1982 port { 1983 funnel_qatb_out: endpoint { 1984 remote-endpoint = <&funnel_in0_in6>; 1985 }; 1986 }; 1987 }; 1988 }; 1989 1990 cti@6010000 { 1991 compatible = "arm,coresight-cti", "arm,primecell"; 1992 reg = <0x0 0x06010000 0x0 0x1000>; 1993 1994 clocks = <&aoss_qmp>; 1995 clock-names = "apb_pclk"; 1996 }; 1997 1998 cti@6011000 { 1999 compatible = "arm,coresight-cti", "arm,primecell"; 2000 reg = <0x0 0x06011000 0x0 0x1000>; 2001 2002 clocks = <&aoss_qmp>; 2003 clock-names = "apb_pclk"; 2004 }; 2005 2006 cti@6012000 { 2007 compatible = "arm,coresight-cti", "arm,primecell"; 2008 reg = <0x0 0x06012000 0x0 0x1000>; 2009 2010 clocks = <&aoss_qmp>; 2011 clock-names = "apb_pclk"; 2012 }; 2013 2014 cti@6013000 { 2015 compatible = "arm,coresight-cti", "arm,primecell"; 2016 reg = <0x0 0x06013000 0x0 0x1000>; 2017 2018 clocks = <&aoss_qmp>; 2019 clock-names = "apb_pclk"; 2020 }; 2021 2022 cti@6014000 { 2023 compatible = "arm,coresight-cti", "arm,primecell"; 2024 reg = <0x0 0x06014000 0x0 0x1000>; 2025 2026 clocks = <&aoss_qmp>; 2027 clock-names = "apb_pclk"; 2028 }; 2029 2030 cti@6015000 { 2031 compatible = "arm,coresight-cti", "arm,primecell"; 2032 reg = <0x0 0x06015000 0x0 0x1000>; 2033 2034 clocks = <&aoss_qmp>; 2035 clock-names = "apb_pclk"; 2036 }; 2037 2038 cti@6016000 { 2039 compatible = "arm,coresight-cti", "arm,primecell"; 2040 reg = <0x0 0x06016000 0x0 0x1000>; 2041 2042 clocks = <&aoss_qmp>; 2043 clock-names = "apb_pclk"; 2044 }; 2045 2046 cti@6017000 { 2047 compatible = "arm,coresight-cti", "arm,primecell"; 2048 reg = <0x0 0x06017000 0x0 0x1000>; 2049 2050 clocks = <&aoss_qmp>; 2051 clock-names = "apb_pclk"; 2052 }; 2053 2054 cti@6018000 { 2055 compatible = "arm,coresight-cti", "arm,primecell"; 2056 reg = <0x0 0x06018000 0x0 0x1000>; 2057 2058 clocks = <&aoss_qmp>; 2059 clock-names = "apb_pclk"; 2060 }; 2061 2062 cti@6019000 { 2063 compatible = "arm,coresight-cti", "arm,primecell"; 2064 reg = <0x0 0x06019000 0x0 0x1000>; 2065 2066 clocks = <&aoss_qmp>; 2067 clock-names = "apb_pclk"; 2068 }; 2069 2070 cti@601a000 { 2071 compatible = "arm,coresight-cti", "arm,primecell"; 2072 reg = <0x0 0x0601a000 0x0 0x1000>; 2073 2074 clocks = <&aoss_qmp>; 2075 clock-names = "apb_pclk"; 2076 }; 2077 2078 cti@601b000 { 2079 compatible = "arm,coresight-cti", "arm,primecell"; 2080 reg = <0x0 0x0601b000 0x0 0x1000>; 2081 2082 clocks = <&aoss_qmp>; 2083 clock-names = "apb_pclk"; 2084 }; 2085 2086 cti@601c000 { 2087 compatible = "arm,coresight-cti", "arm,primecell"; 2088 reg = <0x0 0x0601c000 0x0 0x1000>; 2089 2090 clocks = <&aoss_qmp>; 2091 clock-names = "apb_pclk"; 2092 }; 2093 2094 cti@601d000 { 2095 compatible = "arm,coresight-cti", "arm,primecell"; 2096 reg = <0x0 0x0601d000 0x0 0x1000>; 2097 2098 clocks = <&aoss_qmp>; 2099 clock-names = "apb_pclk"; 2100 }; 2101 2102 cti@601e000 { 2103 compatible = "arm,coresight-cti", "arm,primecell"; 2104 reg = <0x0 0x0601e000 0x0 0x1000>; 2105 2106 clocks = <&aoss_qmp>; 2107 clock-names = "apb_pclk"; 2108 }; 2109 2110 cti@601f000 { 2111 compatible = "arm,coresight-cti", "arm,primecell"; 2112 reg = <0x0 0x0601f000 0x0 0x1000>; 2113 2114 clocks = <&aoss_qmp>; 2115 clock-names = "apb_pclk"; 2116 }; 2117 2118 funnel@6041000 { 2119 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2120 reg = <0x0 0x06041000 0x0 0x1000>; 2121 2122 clocks = <&aoss_qmp>; 2123 clock-names = "apb_pclk"; 2124 2125 in-ports { 2126 #address-cells = <1>; 2127 #size-cells = <0>; 2128 2129 port@6 { 2130 reg = <6>; 2131 2132 funnel_in0_in6: endpoint { 2133 remote-endpoint = <&funnel_qatb_out>; 2134 }; 2135 }; 2136 2137 port@7 { 2138 reg = <7>; 2139 2140 funnel_in0_in7: endpoint { 2141 remote-endpoint = <&stm_out>; 2142 }; 2143 }; 2144 }; 2145 2146 out-ports { 2147 port { 2148 funnel_in0_out: endpoint { 2149 remote-endpoint = <&funnel_merg_in0>; 2150 }; 2151 }; 2152 }; 2153 }; 2154 2155 funnel@6042000 { 2156 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2157 reg = <0x0 0x06042000 0x0 0x1000>; 2158 2159 clocks = <&aoss_qmp>; 2160 clock-names = "apb_pclk"; 2161 2162 in-ports { 2163 #address-cells = <1>; 2164 #size-cells = <0>; 2165 2166 port@3 { 2167 reg = <3>; 2168 2169 funnel_in1_in3: endpoint { 2170 remote-endpoint = <&replicator_swao_out0>; 2171 }; 2172 }; 2173 2174 port@4 { 2175 reg = <4>; 2176 2177 funnel_in1_in4: endpoint { 2178 remote-endpoint = <&tpdm_wcss_out>; 2179 }; 2180 }; 2181 2182 port@7 { 2183 reg = <7>; 2184 2185 funnel_in1_in7: endpoint { 2186 remote-endpoint = <&funnel_apss_merg_out>; 2187 }; 2188 }; 2189 }; 2190 2191 out-ports { 2192 port { 2193 funnel_in1_out: endpoint { 2194 remote-endpoint = <&funnel_merg_in1>; 2195 }; 2196 }; 2197 }; 2198 }; 2199 2200 funnel@6045000 { 2201 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2202 reg = <0x0 0x06045000 0x0 0x1000>; 2203 2204 clocks = <&aoss_qmp>; 2205 clock-names = "apb_pclk"; 2206 2207 in-ports { 2208 #address-cells = <1>; 2209 #size-cells = <0>; 2210 2211 port@0 { 2212 reg = <0>; 2213 2214 funnel_merg_in0: endpoint { 2215 remote-endpoint = <&funnel_in0_out>; 2216 }; 2217 }; 2218 2219 port@1 { 2220 reg = <1>; 2221 2222 funnel_merg_in1: endpoint { 2223 remote-endpoint = <&funnel_in1_out>; 2224 }; 2225 }; 2226 }; 2227 2228 out-ports { 2229 port { 2230 funnel_merg_out: endpoint { 2231 remote-endpoint = <&tmc_etf_in>; 2232 }; 2233 }; 2234 }; 2235 }; 2236 2237 replicator@6046000 { 2238 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2239 reg = <0x0 0x06046000 0x0 0x1000>; 2240 2241 clocks = <&aoss_qmp>; 2242 clock-names = "apb_pclk"; 2243 2244 in-ports { 2245 port { 2246 replicator0_in: endpoint { 2247 remote-endpoint = <&tmc_etf_out>; 2248 }; 2249 }; 2250 }; 2251 2252 out-ports { 2253 #address-cells = <1>; 2254 #size-cells = <0>; 2255 2256 port@1 { 2257 reg = <1>; 2258 2259 replicator0_out1: endpoint { 2260 remote-endpoint = <&replicator1_in>; 2261 }; 2262 }; 2263 }; 2264 }; 2265 2266 tmc@6047000 { 2267 compatible = "arm,coresight-tmc", "arm,primecell"; 2268 reg = <0x0 0x06047000 0x0 0x1000>; 2269 2270 clocks = <&aoss_qmp>; 2271 clock-names = "apb_pclk"; 2272 2273 in-ports { 2274 port { 2275 tmc_etf_in: endpoint { 2276 remote-endpoint = <&funnel_merg_out>; 2277 }; 2278 }; 2279 }; 2280 2281 out-ports { 2282 port { 2283 tmc_etf_out: endpoint { 2284 remote-endpoint = <&replicator0_in>; 2285 }; 2286 }; 2287 }; 2288 }; 2289 2290 replicator@604a000 { 2291 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2292 reg = <0x0 0x0604a000 0x0 0x1000>; 2293 2294 clocks = <&aoss_qmp>; 2295 clock-names = "apb_pclk"; 2296 status = "disabled"; 2297 2298 in-ports { 2299 port { 2300 replicator1_in: endpoint { 2301 remote-endpoint = <&replicator0_out1>; 2302 }; 2303 }; 2304 }; 2305 2306 out-ports { 2307 port { 2308 replicator1_out: endpoint { 2309 remote-endpoint = <&funnel_swao_in6>; 2310 }; 2311 }; 2312 }; 2313 }; 2314 2315 cti@683b000 { 2316 compatible = "arm,coresight-cti", "arm,primecell"; 2317 reg = <0x0 0x0683b000 0x0 0x1000>; 2318 2319 clocks = <&aoss_qmp>; 2320 clock-names = "apb_pclk"; 2321 }; 2322 2323 tpdm@6840000 { 2324 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2325 reg = <0x0 0x06840000 0x0 0x1000>; 2326 2327 clocks = <&aoss_qmp>; 2328 clock-names = "apb_pclk"; 2329 2330 qcom,cmb-element-bits = <64>; 2331 qcom,cmb-msrs-num = <32>; 2332 status = "disabled"; 2333 2334 out-ports { 2335 port { 2336 tpdm_vsense_out: endpoint { 2337 remote-endpoint = <&tpda_qdss_in7>; 2338 }; 2339 }; 2340 }; 2341 }; 2342 2343 tpdm@684c000 { 2344 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2345 reg = <0x0 0x0684c000 0x0 0x1000>; 2346 2347 clocks = <&aoss_qmp>; 2348 clock-names = "apb_pclk"; 2349 2350 qcom,cmb-element-bits = <32>; 2351 qcom,cmb-msrs-num = <32>; 2352 2353 out-ports { 2354 port { 2355 tpdm_prng_out: endpoint { 2356 remote-endpoint = <&tpda_qdss_in9>; 2357 }; 2358 }; 2359 }; 2360 }; 2361 2362 tpdm@6850000 { 2363 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2364 reg = <0x0 0x06850000 0x0 0x1000>; 2365 2366 clocks = <&aoss_qmp>; 2367 clock-names = "apb_pclk"; 2368 2369 qcom,cmb-element-bits = <64>; 2370 qcom,cmb-msrs-num = <32>; 2371 qcom,dsb-element-bits = <32>; 2372 qcom,dsb-msrs-num = <32>; 2373 2374 out-ports { 2375 port { 2376 tpdm_pimem_out: endpoint { 2377 remote-endpoint = <&tpda_qdss_in13>; 2378 }; 2379 }; 2380 }; 2381 }; 2382 2383 tpdm@6860000 { 2384 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2385 reg = <0x0 0x06860000 0x0 0x1000>; 2386 2387 clocks = <&aoss_qmp>; 2388 clock-names = "apb_pclk"; 2389 2390 qcom,dsb-element-bits = <32>; 2391 qcom,dsb-msrs-num = <32>; 2392 2393 out-ports { 2394 port { 2395 tpdm_turing_out: endpoint { 2396 remote-endpoint = <&funnel_turing_in>; 2397 }; 2398 }; 2399 }; 2400 }; 2401 2402 funnel@6861000 { 2403 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2404 reg = <0x0 0x06861000 0x0 0x1000>; 2405 2406 clocks = <&aoss_qmp>; 2407 clock-names = "apb_pclk"; 2408 2409 in-ports { 2410 port { 2411 funnel_turing_in: endpoint { 2412 remote-endpoint = <&tpdm_turing_out>; 2413 }; 2414 }; 2415 }; 2416 2417 out-ports { 2418 port { 2419 funnel_turing_out: endpoint { 2420 remote-endpoint = <&tpda_qdss_in6>; 2421 }; 2422 }; 2423 }; 2424 }; 2425 2426 cti@6867000 { 2427 compatible = "arm,coresight-cti", "arm,primecell"; 2428 reg = <0x0 0x06867000 0x0 0x1000>; 2429 2430 clocks = <&aoss_qmp>; 2431 clock-names = "apb_pclk"; 2432 }; 2433 2434 tpdm@6870000 { 2435 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2436 reg = <0x0 0x06870000 0x0 0x1000>; 2437 2438 clocks = <&aoss_qmp>; 2439 clock-names = "apb_pclk"; 2440 2441 qcom,cmb-element-bits = <32>; 2442 qcom,cmb-msrs-num = <32>; 2443 status = "disabled"; 2444 2445 out-ports { 2446 port { 2447 tpdm_dcc_out: endpoint { 2448 remote-endpoint = <&tpda_qdss_in8>; 2449 }; 2450 }; 2451 }; 2452 }; 2453 2454 tpdm@699c000 { 2455 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2456 reg = <0x0 0x0699c000 0x0 0x1000>; 2457 2458 clocks = <&aoss_qmp>; 2459 clock-names = "apb_pclk"; 2460 2461 qcom,cmb-element-bits = <32>; 2462 qcom,cmb-msrs-num = <32>; 2463 qcom,dsb-element-bits = <32>; 2464 qcom,dsb-msrs-num = <32>; 2465 status = "disabled"; 2466 2467 out-ports { 2468 port { 2469 tpdm_wcss_out: endpoint { 2470 remote-endpoint = <&funnel_in1_in4>; 2471 }; 2472 }; 2473 }; 2474 }; 2475 2476 tpdm@69c0000 { 2477 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2478 reg = <0x0 0x069c0000 0x0 0x1000>; 2479 2480 clocks = <&aoss_qmp>; 2481 clock-names = "apb_pclk"; 2482 2483 qcom,dsb-element-bits = <32>; 2484 qcom,dsb-msrs-num = <32>; 2485 2486 out-ports { 2487 port { 2488 tpdm_monaq_out: endpoint { 2489 remote-endpoint = <&funnel_monaq_in>; 2490 }; 2491 }; 2492 }; 2493 }; 2494 2495 funnel@69c3000 { 2496 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2497 reg = <0x0 0x069c3000 0x0 0x1000>; 2498 2499 clocks = <&aoss_qmp>; 2500 clock-names = "apb_pclk"; 2501 2502 in-ports { 2503 port { 2504 funnel_monaq_in: endpoint { 2505 remote-endpoint = <&tpdm_monaq_out>; 2506 }; 2507 }; 2508 }; 2509 2510 out-ports { 2511 port { 2512 funnel_monaq_out: endpoint { 2513 remote-endpoint = <&tpda_qdss_in4>; 2514 }; 2515 }; 2516 }; 2517 }; 2518 2519 tpdm@69d0000 { 2520 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2521 reg = <0x0 0x069d0000 0x0 0x1000>; 2522 2523 clocks = <&aoss_qmp>; 2524 clock-names = "apb_pclk"; 2525 2526 qcom,dsb-element-bits = <32>; 2527 qcom,dsb-msrs-num = <32>; 2528 status = "disabled"; 2529 2530 out-ports { 2531 port { 2532 tpdm_qm_out: endpoint { 2533 remote-endpoint = <&tpda_qdss_in11>; 2534 }; 2535 }; 2536 }; 2537 }; 2538 2539 tpdm@6a00000 { 2540 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2541 reg = <0x0 0x06a00000 0x0 0x1000>; 2542 2543 clocks = <&aoss_qmp>; 2544 clock-names = "apb_pclk"; 2545 2546 qcom,dsb-element-bits = <32>; 2547 qcom,dsb-msrs-num = <32>; 2548 status = "disabled"; 2549 2550 out-ports { 2551 port { 2552 tpdm_ddr_out: endpoint { 2553 remote-endpoint = <&funnel_ddr_0_in>; 2554 }; 2555 }; 2556 }; 2557 }; 2558 2559 cti@6a02000 { 2560 compatible = "arm,coresight-cti", "arm,primecell"; 2561 reg = <0x0 0x06a02000 0x0 0x1000>; 2562 2563 clocks = <&aoss_qmp>; 2564 clock-names = "apb_pclk"; 2565 }; 2566 2567 cti@6a03000 { 2568 compatible = "arm,coresight-cti", "arm,primecell"; 2569 reg = <0x0 0x06a03000 0x0 0x1000>; 2570 2571 clocks = <&aoss_qmp>; 2572 clock-names = "apb_pclk"; 2573 }; 2574 2575 cti@6a10000 { 2576 compatible = "arm,coresight-cti", "arm,primecell"; 2577 reg = <0x0 0x06a10000 0x0 0x1000>; 2578 2579 clocks = <&aoss_qmp>; 2580 clock-names = "apb_pclk"; 2581 }; 2582 2583 cti@6a11000 { 2584 compatible = "arm,coresight-cti", "arm,primecell"; 2585 reg = <0x0 0x06a11000 0x0 0x1000>; 2586 2587 clocks = <&aoss_qmp>; 2588 clock-names = "apb_pclk"; 2589 }; 2590 2591 funnel@6a05000 { 2592 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2593 reg = <0x0 0x06a05000 0x0 0x1000>; 2594 2595 clocks = <&aoss_qmp>; 2596 clock-names = "apb_pclk"; 2597 2598 in-ports { 2599 port { 2600 funnel_ddr_0_in: endpoint { 2601 remote-endpoint = <&tpdm_ddr_out>; 2602 }; 2603 }; 2604 }; 2605 2606 out-ports { 2607 port { 2608 funnel_ddr_0_out: endpoint { 2609 remote-endpoint = <&tpda_qdss_in5>; 2610 }; 2611 }; 2612 }; 2613 }; 2614 2615 tpda@6b01000 { 2616 compatible = "qcom,coresight-tpda", "arm,primecell"; 2617 reg = <0x0 0x06b01000 0x0 0x1000>; 2618 2619 clocks = <&aoss_qmp>; 2620 clock-names = "apb_pclk"; 2621 2622 in-ports { 2623 #address-cells = <1>; 2624 #size-cells = <0>; 2625 2626 port@0 { 2627 reg = <0>; 2628 2629 tpda_swao_in0: endpoint { 2630 remote-endpoint = <&tpdm_swao0_out>; 2631 }; 2632 }; 2633 2634 port@1 { 2635 reg = <1>; 2636 2637 tpda_swao_in1: endpoint { 2638 remote-endpoint = <&tpdm_swao1_out>; 2639 }; 2640 2641 }; 2642 }; 2643 2644 out-ports { 2645 port { 2646 tpda_swao_out: endpoint { 2647 remote-endpoint = <&funnel_swao_in7>; 2648 }; 2649 }; 2650 }; 2651 }; 2652 2653 tpdm@6b02000 { 2654 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2655 reg = <0x0 0x06b02000 0x0 0x1000>; 2656 2657 clocks = <&aoss_qmp>; 2658 clock-names = "apb_pclk"; 2659 2660 qcom,cmb-element-bits = <64>; 2661 qcom,cmb-msrs-num = <32>; 2662 status = "disabled"; 2663 2664 out-ports { 2665 port { 2666 tpdm_swao0_out: endpoint { 2667 remote-endpoint = <&tpda_swao_in0>; 2668 }; 2669 }; 2670 }; 2671 }; 2672 2673 tpdm@6b03000 { 2674 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2675 reg = <0x0 0x06b03000 0x0 0x1000>; 2676 2677 clocks = <&aoss_qmp>; 2678 clock-names = "apb_pclk"; 2679 2680 qcom,dsb-element-bits = <32>; 2681 qcom,dsb-msrs-num = <32>; 2682 status = "disabled"; 2683 2684 out-ports { 2685 port { 2686 tpdm_swao1_out: endpoint { 2687 remote-endpoint = <&tpda_swao_in1>; 2688 }; 2689 }; 2690 }; 2691 }; 2692 2693 cti@6b04000 { 2694 compatible = "arm,coresight-cti", "arm,primecell"; 2695 reg = <0x0 0x06b04000 0x0 0x1000>; 2696 2697 clocks = <&aoss_qmp>; 2698 clock-names = "apb_pclk"; 2699 }; 2700 2701 cti@6b05000 { 2702 compatible = "arm,coresight-cti", "arm,primecell"; 2703 reg = <0x0 0x06b05000 0x0 0x1000>; 2704 2705 clocks = <&aoss_qmp>; 2706 clock-names = "apb_pclk"; 2707 }; 2708 2709 cti@6b06000 { 2710 compatible = "arm,coresight-cti", "arm,primecell"; 2711 reg = <0x0 0x06b06000 0x0 0x1000>; 2712 2713 clocks = <&aoss_qmp>; 2714 clock-names = "apb_pclk"; 2715 }; 2716 2717 cti@6b07000 { 2718 compatible = "arm,coresight-cti", "arm,primecell"; 2719 reg = <0x0 0x06b07000 0x0 0x1000>; 2720 2721 clocks = <&aoss_qmp>; 2722 clock-names = "apb_pclk"; 2723 }; 2724 2725 funnel@6b08000 { 2726 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2727 reg = <0x0 0x06b08000 0x0 0x1000>; 2728 2729 clocks = <&aoss_qmp>; 2730 clock-names = "apb_pclk"; 2731 2732 in-ports { 2733 #address-cells = <1>; 2734 #size-cells = <0>; 2735 2736 port@6 { 2737 reg = <6>; 2738 2739 funnel_swao_in6: endpoint { 2740 remote-endpoint = <&replicator1_out>; 2741 }; 2742 }; 2743 2744 port@7 { 2745 reg = <7>; 2746 2747 funnel_swao_in7: endpoint { 2748 remote-endpoint = <&tpda_swao_out>; 2749 }; 2750 }; 2751 }; 2752 2753 out-ports { 2754 port { 2755 funnel_swao_out: endpoint { 2756 remote-endpoint = <&tmc_etf_swao_in>; 2757 }; 2758 }; 2759 }; 2760 }; 2761 2762 tmc@6b09000 { 2763 compatible = "arm,coresight-tmc", "arm,primecell"; 2764 reg = <0x0 0x06b09000 0x0 0x1000>; 2765 2766 clocks = <&aoss_qmp>; 2767 clock-names = "apb_pclk"; 2768 2769 in-ports { 2770 port { 2771 tmc_etf_swao_in: endpoint { 2772 remote-endpoint = <&funnel_swao_out>; 2773 }; 2774 }; 2775 }; 2776 2777 out-ports { 2778 port { 2779 tmc_etf_swao_out: endpoint { 2780 remote-endpoint = <&replicator_swao_in>; 2781 }; 2782 }; 2783 }; 2784 }; 2785 2786 replicator@6b0a000 { 2787 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2788 reg = <0x0 0x06b0a000 0x0 0x1000>; 2789 2790 clocks = <&aoss_qmp>; 2791 clock-names = "apb_pclk"; 2792 2793 in-ports { 2794 port { 2795 replicator_swao_in: endpoint { 2796 remote-endpoint = <&tmc_etf_swao_out>; 2797 }; 2798 }; 2799 }; 2800 2801 out-ports { 2802 #address-cells = <1>; 2803 #size-cells = <0>; 2804 2805 port@0 { 2806 reg = <0>; 2807 2808 replicator_swao_out0: endpoint { 2809 remote-endpoint = <&funnel_in1_in3>; 2810 }; 2811 }; 2812 2813 port@1 { 2814 reg = <1>; 2815 2816 replicator_swao_out1: endpoint { 2817 remote-endpoint = <&eud_in>; 2818 }; 2819 }; 2820 }; 2821 }; 2822 2823 cti@6b21000 { 2824 compatible = "arm,coresight-cti", "arm,primecell"; 2825 reg = <0x0 0x06b21000 0x0 0x1000>; 2826 2827 clocks = <&aoss_qmp>; 2828 clock-names = "apb_pclk"; 2829 }; 2830 2831 tpdm@6b48000 { 2832 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2833 reg = <0x0 0x06b48000 0x0 0x1000>; 2834 2835 clocks = <&aoss_qmp>; 2836 clock-names = "apb_pclk"; 2837 2838 qcom,dsb-element-bits = <32>; 2839 qcom,dsb-msrs-num = <32>; 2840 2841 out-ports { 2842 port { 2843 tpdm_west_out: endpoint { 2844 remote-endpoint = <&tpda_qdss_in12>; 2845 }; 2846 }; 2847 }; 2848 }; 2849 2850 cti@6c13000 { 2851 compatible = "arm,coresight-cti", "arm,primecell"; 2852 reg = <0x0 0x06c13000 0x0 0x1000>; 2853 2854 clocks = <&aoss_qmp>; 2855 clock-names = "apb_pclk"; 2856 2857 /* Not all required clocks can be enabled from the OS */ 2858 status = "fail"; 2859 }; 2860 2861 cti@6c20000 { 2862 compatible = "arm,coresight-cti", "arm,primecell"; 2863 reg = <0x0 0x06c20000 0x0 0x1000>; 2864 2865 clocks = <&aoss_qmp>; 2866 clock-names = "apb_pclk"; 2867 status = "disabled"; 2868 }; 2869 2870 tpdm@6c28000 { 2871 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2872 reg = <0x0 0x06c28000 0x0 0x1000>; 2873 2874 clocks = <&aoss_qmp>; 2875 clock-names = "apb_pclk"; 2876 2877 qcom,dsb-element-bits = <32>; 2878 qcom,dsb-msrs-num = <32>; 2879 2880 out-ports { 2881 port { 2882 tpdm_center_out: endpoint { 2883 remote-endpoint = <&tpda_qdss_in0>; 2884 }; 2885 }; 2886 }; 2887 }; 2888 2889 cti@6c29000 { 2890 compatible = "arm,coresight-cti", "arm,primecell"; 2891 reg = <0x0 0x06c29000 0x0 0x1000>; 2892 2893 clocks = <&aoss_qmp>; 2894 clock-names = "apb_pclk"; 2895 }; 2896 2897 cti@6c2a000 { 2898 compatible = "arm,coresight-cti", "arm,primecell"; 2899 reg = <0x0 0x06c2a000 0x0 0x1000>; 2900 2901 clocks = <&aoss_qmp>; 2902 clock-names = "apb_pclk"; 2903 }; 2904 2905 cti@7020000 { 2906 compatible = "arm,coresight-cti", "arm,primecell"; 2907 reg = <0x0 0x07020000 0x0 0x1000>; 2908 2909 clocks = <&aoss_qmp>; 2910 clock-names = "apb_pclk"; 2911 }; 2912 2913 etm@7040000 { 2914 compatible = "arm,primecell"; 2915 reg = <0x0 0x07040000 0x0 0x1000>; 2916 cpu = <&cpu0>; 2917 2918 clocks = <&aoss_qmp>; 2919 clock-names = "apb_pclk"; 2920 2921 arm,coresight-loses-context-with-cpu; 2922 qcom,skip-power-up; 2923 2924 out-ports { 2925 port { 2926 etm0_out: endpoint { 2927 remote-endpoint = <&funnel_apss_in0>; 2928 }; 2929 }; 2930 }; 2931 }; 2932 2933 cti@7120000 { 2934 compatible = "arm,coresight-cti", "arm,primecell"; 2935 reg = <0x0 0x07120000 0x0 0x1000>; 2936 2937 clocks = <&aoss_qmp>; 2938 clock-names = "apb_pclk"; 2939 }; 2940 2941 etm@7140000 { 2942 compatible = "arm,primecell"; 2943 reg = <0x0 0x07140000 0x0 0x1000>; 2944 cpu = <&cpu1>; 2945 2946 clocks = <&aoss_qmp>; 2947 clock-names = "apb_pclk"; 2948 2949 arm,coresight-loses-context-with-cpu; 2950 qcom,skip-power-up; 2951 2952 out-ports { 2953 port { 2954 etm1_out: endpoint { 2955 remote-endpoint = <&funnel_apss_in1>; 2956 }; 2957 }; 2958 }; 2959 }; 2960 2961 cti@7220000 { 2962 compatible = "arm,coresight-cti", "arm,primecell"; 2963 reg = <0x0 0x07220000 0x0 0x1000>; 2964 2965 clocks = <&aoss_qmp>; 2966 clock-names = "apb_pclk"; 2967 }; 2968 2969 etm@7240000 { 2970 compatible = "arm,primecell"; 2971 reg = <0x0 0x07240000 0x0 0x1000>; 2972 cpu = <&cpu2>; 2973 2974 clocks = <&aoss_qmp>; 2975 clock-names = "apb_pclk"; 2976 2977 arm,coresight-loses-context-with-cpu; 2978 qcom,skip-power-up; 2979 2980 out-ports { 2981 port { 2982 etm2_out: endpoint { 2983 remote-endpoint = <&funnel_apss_in2>; 2984 }; 2985 }; 2986 }; 2987 }; 2988 2989 cti@7320000 { 2990 compatible = "arm,coresight-cti", "arm,primecell"; 2991 reg = <0x0 0x07320000 0x0 0x1000>; 2992 2993 clocks = <&aoss_qmp>; 2994 clock-names = "apb_pclk"; 2995 }; 2996 2997 etm@7340000 { 2998 compatible = "arm,primecell"; 2999 reg = <0x0 0x07340000 0x0 0x1000>; 3000 cpu = <&cpu3>; 3001 3002 clocks = <&aoss_qmp>; 3003 clock-names = "apb_pclk"; 3004 3005 arm,coresight-loses-context-with-cpu; 3006 qcom,skip-power-up; 3007 3008 out-ports { 3009 port { 3010 etm3_out: endpoint { 3011 remote-endpoint = <&funnel_apss_in3>; 3012 }; 3013 }; 3014 }; 3015 }; 3016 3017 cti@7420000 { 3018 compatible = "arm,coresight-cti", "arm,primecell"; 3019 reg = <0x0 0x07420000 0x0 0x1000>; 3020 3021 clocks = <&aoss_qmp>; 3022 clock-names = "apb_pclk"; 3023 }; 3024 3025 etm@7440000 { 3026 compatible = "arm,primecell"; 3027 reg = <0x0 0x07440000 0x0 0x1000>; 3028 cpu = <&cpu4>; 3029 3030 clocks = <&aoss_qmp>; 3031 clock-names = "apb_pclk"; 3032 3033 arm,coresight-loses-context-with-cpu; 3034 qcom,skip-power-up; 3035 3036 out-ports { 3037 port { 3038 etm4_out: endpoint { 3039 remote-endpoint = <&funnel_apss_in4>; 3040 }; 3041 }; 3042 }; 3043 }; 3044 3045 cti@7520000 { 3046 compatible = "arm,coresight-cti", "arm,primecell"; 3047 reg = <0x0 0x07520000 0x0 0x1000>; 3048 3049 clocks = <&aoss_qmp>; 3050 clock-names = "apb_pclk"; 3051 }; 3052 3053 etm@7540000 { 3054 compatible = "arm,primecell"; 3055 reg = <0x0 0x07540000 0x0 0x1000>; 3056 cpu = <&cpu5>; 3057 3058 clocks = <&aoss_qmp>; 3059 clock-names = "apb_pclk"; 3060 3061 arm,coresight-loses-context-with-cpu; 3062 qcom,skip-power-up; 3063 3064 out-ports { 3065 port { 3066 etm5_out: endpoint { 3067 remote-endpoint = <&funnel_apss_in5>; 3068 }; 3069 }; 3070 }; 3071 }; 3072 3073 cti@7620000 { 3074 compatible = "arm,coresight-cti", "arm,primecell"; 3075 reg = <0x0 0x07620000 0x0 0x1000>; 3076 3077 clocks = <&aoss_qmp>; 3078 clock-names = "apb_pclk"; 3079 }; 3080 3081 etm@7640000 { 3082 compatible = "arm,primecell"; 3083 reg = <0x0 0x07640000 0x0 0x1000>; 3084 cpu = <&cpu6>; 3085 3086 clocks = <&aoss_qmp>; 3087 clock-names = "apb_pclk"; 3088 3089 arm,coresight-loses-context-with-cpu; 3090 qcom,skip-power-up; 3091 3092 out-ports { 3093 port { 3094 etm6_out: endpoint { 3095 remote-endpoint = <&funnel_apss_in6>; 3096 }; 3097 }; 3098 }; 3099 }; 3100 3101 cti@7720000 { 3102 compatible = "arm,coresight-cti", "arm,primecell"; 3103 reg = <0x0 0x07720000 0x0 0x1000>; 3104 3105 clocks = <&aoss_qmp>; 3106 clock-names = "apb_pclk"; 3107 }; 3108 3109 etm@7740000 { 3110 compatible = "arm,primecell"; 3111 reg = <0x0 0x07740000 0x0 0x1000>; 3112 cpu = <&cpu7>; 3113 3114 clocks = <&aoss_qmp>; 3115 clock-names = "apb_pclk"; 3116 3117 arm,coresight-loses-context-with-cpu; 3118 qcom,skip-power-up; 3119 3120 out-ports { 3121 port { 3122 etm7_out: endpoint { 3123 remote-endpoint = <&funnel_apss_in7>; 3124 }; 3125 }; 3126 }; 3127 }; 3128 3129 funnel@7800000 { 3130 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3131 reg = <0x0 0x07800000 0x0 0x1000>; 3132 3133 clocks = <&aoss_qmp>; 3134 clock-names = "apb_pclk"; 3135 3136 in-ports { 3137 #address-cells = <1>; 3138 #size-cells = <0>; 3139 3140 port@0 { 3141 reg = <0>; 3142 3143 funnel_apss_in0: endpoint { 3144 remote-endpoint = <&etm0_out>; 3145 }; 3146 }; 3147 3148 port@1 { 3149 reg = <1>; 3150 3151 funnel_apss_in1: endpoint { 3152 remote-endpoint = <&etm1_out>; 3153 }; 3154 }; 3155 3156 port@2 { 3157 reg = <2>; 3158 3159 funnel_apss_in2: endpoint { 3160 remote-endpoint = <&etm2_out>; 3161 }; 3162 }; 3163 3164 port@3 { 3165 reg = <3>; 3166 3167 funnel_apss_in3: endpoint { 3168 remote-endpoint = <&etm3_out>; 3169 }; 3170 }; 3171 3172 port@4 { 3173 reg = <4>; 3174 3175 funnel_apss_in4: endpoint { 3176 remote-endpoint = <&etm4_out>; 3177 }; 3178 }; 3179 3180 port@5 { 3181 reg = <5>; 3182 3183 funnel_apss_in5: endpoint { 3184 remote-endpoint = <&etm5_out>; 3185 }; 3186 }; 3187 3188 port@6 { 3189 reg = <6>; 3190 3191 funnel_apss_in6: endpoint { 3192 remote-endpoint = <&etm6_out>; 3193 }; 3194 }; 3195 3196 port@7 { 3197 reg = <7>; 3198 3199 funnel_apss_in7: endpoint { 3200 remote-endpoint = <&etm7_out>; 3201 }; 3202 }; 3203 }; 3204 3205 out-ports { 3206 port { 3207 funnel_apss_out: endpoint { 3208 remote-endpoint = <&funnel_apss_merg_in0>; 3209 }; 3210 }; 3211 }; 3212 }; 3213 3214 funnel@7810000 { 3215 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3216 reg = <0x0 0x07810000 0x0 0x1000>; 3217 3218 clocks = <&aoss_qmp>; 3219 clock-names = "apb_pclk"; 3220 3221 in-ports { 3222 #address-cells = <1>; 3223 #size-cells = <0>; 3224 3225 port@0 { 3226 reg = <0>; 3227 3228 funnel_apss_merg_in0: endpoint { 3229 remote-endpoint = <&funnel_apss_out>; 3230 }; 3231 }; 3232 3233 port@2 { 3234 reg = <2>; 3235 3236 funnel_apss_merg_in2: endpoint { 3237 remote-endpoint = <&tpda_olc_out>; 3238 }; 3239 }; 3240 3241 port@3 { 3242 reg = <3>; 3243 3244 funnel_apss_merg_in3: endpoint { 3245 remote-endpoint = <&tpda_llm_silver_out>; 3246 }; 3247 }; 3248 3249 port@4 { 3250 reg = <4>; 3251 3252 funnel_apss_merg_in4: endpoint { 3253 remote-endpoint = <&tpda_llm_gold_out>; 3254 }; 3255 }; 3256 3257 port@5 { 3258 reg = <5>; 3259 3260 funnel_apss_merg_in5: endpoint { 3261 remote-endpoint = <&tpda_apss_out>; 3262 }; 3263 }; 3264 }; 3265 3266 out-ports { 3267 port { 3268 funnel_apss_merg_out: endpoint { 3269 remote-endpoint = <&funnel_in1_in7>; 3270 }; 3271 }; 3272 }; 3273 }; 3274 3275 tpdm@7830000 { 3276 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3277 reg = <0x0 0x07830000 0x0 0x1000>; 3278 3279 clocks = <&aoss_qmp>; 3280 clock-names = "apb_pclk"; 3281 3282 qcom,cmb-element-bits = <64>; 3283 qcom,cmb-msrs-num = <32>; 3284 3285 out-ports { 3286 port { 3287 tpdm_olc_out: endpoint { 3288 remote-endpoint = <&tpda_olc_in>; 3289 }; 3290 }; 3291 }; 3292 }; 3293 3294 tpda@7832000 { 3295 compatible = "qcom,coresight-tpda", "arm,primecell"; 3296 reg = <0x0 0x07832000 0x0 0x1000>; 3297 3298 clocks = <&aoss_qmp>; 3299 clock-names = "apb_pclk"; 3300 3301 in-ports { 3302 port { 3303 tpda_olc_in: endpoint { 3304 remote-endpoint = <&tpdm_olc_out>; 3305 }; 3306 }; 3307 }; 3308 3309 out-ports { 3310 port { 3311 tpda_olc_out: endpoint { 3312 remote-endpoint = <&funnel_apss_merg_in2>; 3313 }; 3314 }; 3315 }; 3316 }; 3317 3318 tpdm@7860000 { 3319 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3320 reg = <0x0 0x07860000 0x0 0x1000>; 3321 3322 clocks = <&aoss_qmp>; 3323 clock-names = "apb_pclk"; 3324 3325 qcom,dsb-element-bits = <32>; 3326 qcom,dsb-msrs-num = <32>; 3327 3328 out-ports { 3329 port { 3330 tpdm_apss_out: endpoint { 3331 remote-endpoint = <&tpda_apss_in>; 3332 }; 3333 }; 3334 }; 3335 }; 3336 3337 tpda@7862000 { 3338 compatible = "qcom,coresight-tpda", "arm,primecell"; 3339 reg = <0x0 0x07862000 0x0 0x1000>; 3340 3341 clocks = <&aoss_qmp>; 3342 clock-names = "apb_pclk"; 3343 3344 in-ports { 3345 port { 3346 tpda_apss_in: endpoint { 3347 remote-endpoint = <&tpdm_apss_out>; 3348 }; 3349 }; 3350 }; 3351 3352 out-ports { 3353 port { 3354 tpda_apss_out: endpoint { 3355 remote-endpoint = <&funnel_apss_merg_in5>; 3356 }; 3357 }; 3358 }; 3359 }; 3360 3361 tpdm@78a0000 { 3362 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3363 reg = <0x0 0x078a0000 0x0 0x1000>; 3364 3365 clocks = <&aoss_qmp>; 3366 clock-names = "apb_pclk"; 3367 3368 qcom,cmb-element-bits = <32>; 3369 qcom,cmb-msrs-num = <32>; 3370 3371 out-ports { 3372 port { 3373 tpdm_llm_silver_out: endpoint { 3374 remote-endpoint = <&tpda_llm_silver_in>; 3375 }; 3376 }; 3377 }; 3378 }; 3379 3380 tpdm@78b0000 { 3381 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3382 reg = <0x0 0x078b0000 0x0 0x1000>; 3383 3384 clocks = <&aoss_qmp>; 3385 clock-names = "apb_pclk"; 3386 3387 qcom,cmb-element-bits = <32>; 3388 qcom,cmb-msrs-num = <32>; 3389 3390 out-ports { 3391 port { 3392 tpdm_llm_gold_out: endpoint { 3393 remote-endpoint = <&tpda_llm_gold_in>; 3394 }; 3395 }; 3396 }; 3397 }; 3398 3399 tpda@78c0000 { 3400 compatible = "qcom,coresight-tpda", "arm,primecell"; 3401 reg = <0x0 0x078c0000 0x0 0x1000>; 3402 3403 clocks = <&aoss_qmp>; 3404 clock-names = "apb_pclk"; 3405 3406 in-ports { 3407 port { 3408 tpda_llm_silver_in: endpoint { 3409 remote-endpoint = <&tpdm_llm_silver_out>; 3410 }; 3411 }; 3412 }; 3413 3414 out-ports { 3415 port { 3416 tpda_llm_silver_out: endpoint { 3417 remote-endpoint = <&funnel_apss_merg_in3>; 3418 }; 3419 }; 3420 }; 3421 }; 3422 3423 tpda@78d0000 { 3424 compatible = "qcom,coresight-tpda", "arm,primecell"; 3425 reg = <0x0 0x078d0000 0x0 0x1000>; 3426 3427 clocks = <&aoss_qmp>; 3428 clock-names = "apb_pclk"; 3429 3430 in-ports { 3431 port { 3432 tpda_llm_gold_in: endpoint { 3433 remote-endpoint = <&tpdm_llm_gold_out>; 3434 }; 3435 }; 3436 }; 3437 3438 out-ports { 3439 port { 3440 tpda_llm_gold_out: endpoint { 3441 remote-endpoint = <&funnel_apss_merg_in4>; 3442 }; 3443 }; 3444 }; 3445 }; 3446 3447 cti@78e0000 { 3448 compatible = "arm,coresight-cti", "arm,primecell"; 3449 reg = <0x0 0x078e0000 0x0 0x1000>; 3450 3451 clocks = <&aoss_qmp>; 3452 clock-names = "apb_pclk"; 3453 }; 3454 3455 cti@78f0000 { 3456 compatible = "arm,coresight-cti", "arm,primecell"; 3457 reg = <0x0 0x078f0000 0x0 0x1000>; 3458 3459 clocks = <&aoss_qmp>; 3460 clock-names = "apb_pclk"; 3461 }; 3462 3463 cti@7900000 { 3464 compatible = "arm,coresight-cti", "arm,primecell"; 3465 reg = <0x0 0x07900000 0x0 0x1000>; 3466 3467 clocks = <&aoss_qmp>; 3468 clock-names = "apb_pclk"; 3469 }; 3470 3471 remoteproc_cdsp: remoteproc@8300000 { 3472 compatible = "qcom,qcs615-cdsp-pas", "qcom,sm8150-cdsp-pas"; 3473 reg = <0x0 0x08300000 0x0 0x4040>; 3474 3475 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, 3476 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3477 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3478 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3479 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3480 interrupt-names = "wdog", 3481 "fatal", 3482 "ready", 3483 "handover", 3484 "stop-ack"; 3485 3486 clocks = <&rpmhcc RPMH_CXO_CLK>; 3487 clock-names = "xo"; 3488 3489 power-domains = <&rpmhpd RPMHPD_CX>; 3490 power-domain-names = "cx"; 3491 3492 memory-region = <&rproc_cdsp_mem>; 3493 3494 qcom,qmp = <&aoss_qmp>; 3495 3496 qcom,smem-states = <&cdsp_smp2p_out 0>; 3497 qcom,smem-state-names = "stop"; 3498 3499 status = "disabled"; 3500 3501 glink-edge { 3502 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING 0>; 3503 mboxes = <&apss_shared 4>; 3504 label = "cdsp"; 3505 qcom,remote-pid = <5>; 3506 3507 fastrpc { 3508 compatible = "qcom,fastrpc"; 3509 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3510 label = "cdsp"; 3511 #address-cells = <1>; 3512 #size-cells = <0>; 3513 3514 compute-cb@1 { 3515 compatible = "qcom,fastrpc-compute-cb"; 3516 reg = <1>; 3517 iommus = <&apps_smmu 0x1081 0x0>; 3518 dma-coherent; 3519 }; 3520 3521 compute-cb@2 { 3522 compatible = "qcom,fastrpc-compute-cb"; 3523 reg = <2>; 3524 iommus = <&apps_smmu 0x1082 0x0>; 3525 dma-coherent; 3526 }; 3527 3528 compute-cb@3 { 3529 compatible = "qcom,fastrpc-compute-cb"; 3530 reg = <3>; 3531 iommus = <&apps_smmu 0x1083 0x0>; 3532 dma-coherent; 3533 }; 3534 3535 compute-cb@4 { 3536 compatible = "qcom,fastrpc-compute-cb"; 3537 reg = <4>; 3538 iommus = <&apps_smmu 0x1084 0x0>; 3539 dma-coherent; 3540 }; 3541 3542 compute-cb@5 { 3543 compatible = "qcom,fastrpc-compute-cb"; 3544 reg = <5>; 3545 iommus = <&apps_smmu 0x1085 0x0>; 3546 dma-coherent; 3547 }; 3548 3549 compute-cb@6 { 3550 compatible = "qcom,fastrpc-compute-cb"; 3551 reg = <6>; 3552 iommus = <&apps_smmu 0x1086 0x0>; 3553 dma-coherent; 3554 }; 3555 }; 3556 }; 3557 }; 3558 3559 pmu@90b6300 { 3560 compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon"; 3561 reg = <0x0 0x090b6300 0x0 0x600>; 3562 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>; 3563 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3564 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 3565 3566 operating-points-v2 = <&cpu_bwmon_opp_table>; 3567 3568 cpu_bwmon_opp_table: opp-table { 3569 compatible = "operating-points-v2"; 3570 3571 opp-0 { 3572 opp-peak-kBps = <12896000>; 3573 }; 3574 3575 opp-1 { 3576 opp-peak-kBps = <14928000>; 3577 }; 3578 }; 3579 }; 3580 3581 pmu@90cd000 { 3582 compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3583 reg = <0x0 0x090cd000 0x0 0x1000>; 3584 interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH 0>; 3585 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 3586 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3587 3588 operating-points-v2 = <&llcc_bwmon_opp_table>; 3589 3590 llcc_bwmon_opp_table: opp-table { 3591 compatible = "operating-points-v2"; 3592 3593 opp-0 { 3594 opp-peak-kBps = <800000>; 3595 }; 3596 3597 opp-1 { 3598 opp-peak-kBps = <1200000>; 3599 }; 3600 3601 opp-2 { 3602 opp-peak-kBps = <1804800>; 3603 }; 3604 3605 opp-3 { 3606 opp-peak-kBps = <2188800>; 3607 }; 3608 3609 opp-4 { 3610 opp-peak-kBps = <2726400>; 3611 }; 3612 3613 opp-5 { 3614 opp-peak-kBps = <3072000>; 3615 }; 3616 3617 opp-6 { 3618 opp-peak-kBps = <4070400>; 3619 }; 3620 3621 opp-7 { 3622 opp-peak-kBps = <5414400>; 3623 }; 3624 3625 opp-8 { 3626 opp-peak-kBps = <6220800>; 3627 }; 3628 }; 3629 }; 3630 3631 sdhc_2: mmc@8804000 { 3632 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; 3633 reg = <0x0 0x08804000 0x0 0x1000>; 3634 reg-names = "hc"; 3635 3636 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>, 3637 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; 3638 interrupt-names = "hc_irq", 3639 "pwr_irq"; 3640 3641 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3642 <&gcc GCC_SDCC2_APPS_CLK>, 3643 <&rpmhcc RPMH_CXO_CLK>; 3644 clock-names = "iface", 3645 "core", 3646 "xo"; 3647 3648 power-domains = <&rpmhpd RPMHPD_CX>; 3649 operating-points-v2 = <&sdhc2_opp_table>; 3650 iommus = <&apps_smmu 0x02a0 0x0>; 3651 resets = <&gcc GCC_SDCC2_BCR>; 3652 interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3653 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3654 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3655 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 3656 interconnect-names = "sdhc-ddr", 3657 "cpu-sdhc"; 3658 3659 qcom,dll-config = <0x0007642c>; 3660 qcom,ddr-config = <0x80040868>; 3661 dma-coherent; 3662 3663 status = "disabled"; 3664 3665 sdhc2_opp_table: opp-table { 3666 compatible = "operating-points-v2"; 3667 3668 opp-50000000 { 3669 opp-hz = /bits/ 64 <50000000>; 3670 required-opps = <&rpmhpd_opp_low_svs>; 3671 }; 3672 3673 opp-100000000 { 3674 opp-hz = /bits/ 64 <100000000>; 3675 required-opps = <&rpmhpd_opp_svs>; 3676 }; 3677 3678 opp-202000000 { 3679 opp-hz = /bits/ 64 <202000000>; 3680 required-opps = <&rpmhpd_opp_nom>; 3681 }; 3682 }; 3683 }; 3684 3685 dc_noc: interconnect@9160000 { 3686 reg = <0x0 0x09160000 0x0 0x3200>; 3687 compatible = "qcom,qcs615-dc-noc"; 3688 #interconnect-cells = <2>; 3689 qcom,bcm-voters = <&apps_bcm_voter>; 3690 }; 3691 3692 llcc: system-cache-controller@9200000 { 3693 compatible = "qcom,qcs615-llcc"; 3694 reg = <0x0 0x09200000 0x0 0x50000>, 3695 <0x0 0x09600000 0x0 0x50000>; 3696 reg-names = "llcc0_base", 3697 "llcc_broadcast_base"; 3698 }; 3699 3700 gem_noc: interconnect@9680000 { 3701 reg = <0x0 0x09680000 0x0 0x3e200>; 3702 compatible = "qcom,qcs615-gem-noc"; 3703 #interconnect-cells = <2>; 3704 qcom,bcm-voters = <&apps_bcm_voter>; 3705 }; 3706 3707 venus: video-codec@aa00000 { 3708 compatible = "qcom,qcs615-venus", "qcom,sc7180-venus"; 3709 reg = <0x0 0x0aa00000 0x0 0x100000>; 3710 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>; 3711 3712 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 3713 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3714 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 3715 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 3716 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 3717 clock-names = "core", 3718 "iface", 3719 "bus", 3720 "vcodec0_core", 3721 "vcodec0_bus"; 3722 3723 power-domains = <&videocc VENUS_GDSC>, 3724 <&videocc VCODEC0_GDSC>, 3725 <&rpmhpd RPMHPD_CX>; 3726 power-domain-names = "venus", 3727 "vcodec0", 3728 "cx"; 3729 3730 operating-points-v2 = <&venus_opp_table>; 3731 3732 interconnects = <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 3733 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3734 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3735 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3736 interconnect-names = "video-mem", 3737 "cpu-cfg"; 3738 3739 iommus = <&apps_smmu 0xe60 0x20>; 3740 3741 memory-region = <&pil_video_mem>; 3742 3743 status = "disabled"; 3744 3745 venus_opp_table: opp-table { 3746 compatible = "operating-points-v2"; 3747 3748 opp-133330000 { 3749 opp-hz = /bits/ 64 <133330000>; 3750 required-opps = <&rpmhpd_opp_low_svs>; 3751 }; 3752 3753 opp-240000000 { 3754 opp-hz = /bits/ 64 <240000000>; 3755 required-opps = <&rpmhpd_opp_svs>; 3756 }; 3757 3758 opp-300000000 { 3759 opp-hz = /bits/ 64 <300000000>; 3760 required-opps = <&rpmhpd_opp_svs_l1>; 3761 }; 3762 3763 opp-380000000 { 3764 opp-hz = /bits/ 64 <380000000>; 3765 required-opps = <&rpmhpd_opp_nom>; 3766 }; 3767 3768 opp-410000000 { 3769 opp-hz = /bits/ 64 <410000000>; 3770 required-opps = <&rpmhpd_opp_nom_l1>; 3771 }; 3772 3773 opp-460000000 { 3774 opp-hz = /bits/ 64 <460000000>; 3775 required-opps = <&rpmhpd_opp_turbo>; 3776 }; 3777 }; 3778 }; 3779 3780 videocc: clock-controller@ab00000 { 3781 compatible = "qcom,qcs615-videocc"; 3782 reg = <0 0x0ab00000 0 0x10000>; 3783 3784 clocks = <&rpmhcc RPMH_CXO_CLK>, 3785 <&sleep_clk>; 3786 3787 #clock-cells = <1>; 3788 #reset-cells = <1>; 3789 #power-domain-cells = <1>; 3790 }; 3791 3792 camcc: clock-controller@ad00000 { 3793 compatible = "qcom,qcs615-camcc"; 3794 reg = <0 0x0ad00000 0 0x10000>; 3795 3796 clocks = <&rpmhcc RPMH_CXO_CLK>; 3797 3798 #clock-cells = <1>; 3799 #reset-cells = <1>; 3800 #power-domain-cells = <1>; 3801 }; 3802 3803 mdss: display-subsystem@ae00000 { 3804 compatible = "qcom,sm6150-mdss"; 3805 reg = <0x0 0x0ae00000 0x0 0x1000>; 3806 reg-names = "mdss"; 3807 3808 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 3809 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3810 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3811 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3812 interconnect-names = "mdp0-mem", 3813 "cpu-cfg"; 3814 3815 power-domains = <&dispcc MDSS_CORE_GDSC>; 3816 3817 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3818 <&gcc GCC_DISP_HF_AXI_CLK>, 3819 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3820 3821 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>; 3822 interrupt-controller; 3823 #interrupt-cells = <1>; 3824 3825 iommus = <&apps_smmu 0x800 0x0>; 3826 3827 #address-cells = <2>; 3828 #size-cells = <2>; 3829 ranges; 3830 3831 status = "disabled"; 3832 3833 mdss_mdp: display-controller@ae01000 { 3834 compatible = "qcom,sm6150-dpu"; 3835 reg = <0x0 0x0ae01000 0x0 0x8f000>, 3836 <0x0 0x0aeb0000 0x0 0x2008>; 3837 reg-names = "mdp", 3838 "vbif"; 3839 3840 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3841 <&gcc GCC_DISP_HF_AXI_CLK>, 3842 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3843 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3844 clock-names = "iface", 3845 "bus", 3846 "core", 3847 "vsync"; 3848 3849 operating-points-v2 = <&mdp_opp_table>; 3850 power-domains = <&rpmhpd RPMHPD_CX>; 3851 3852 interrupts-extended = <&mdss 0>; 3853 3854 ports { 3855 #address-cells = <1>; 3856 #size-cells = <0>; 3857 3858 port@0 { 3859 reg = <0>; 3860 3861 dpu_intf0_out: endpoint { 3862 remote-endpoint = <&mdss_dp0_in>; 3863 }; 3864 }; 3865 3866 port@1 { 3867 reg = <1>; 3868 3869 dpu_intf1_out: endpoint { 3870 remote-endpoint = <&mdss_dsi0_in>; 3871 }; 3872 }; 3873 }; 3874 3875 mdp_opp_table: opp-table { 3876 compatible = "operating-points-v2"; 3877 3878 opp-192000000 { 3879 opp-hz = /bits/ 64 <192000000>; 3880 required-opps = <&rpmhpd_opp_low_svs>; 3881 }; 3882 3883 opp-256000000 { 3884 opp-hz = /bits/ 64 <256000000>; 3885 required-opps = <&rpmhpd_opp_svs>; 3886 }; 3887 3888 opp-307200000 { 3889 opp-hz = /bits/ 64 <307200000>; 3890 required-opps = <&rpmhpd_opp_nom>; 3891 }; 3892 }; 3893 }; 3894 3895 mdss_dp0: displayport-controller@ae90000 { 3896 compatible = "qcom,sm6150-dp", "qcom,sm8150-dp", "qcom,sm8350-dp"; 3897 3898 reg = <0x0 0x0ae90000 0x0 0x200>, 3899 <0x0 0x0ae90200 0x0 0x200>, 3900 <0x0 0x0ae90400 0x0 0x600>, 3901 <0x0 0x0ae90a00 0x0 0x600>, 3902 <0x0 0x0ae91000 0x0 0x600>; 3903 3904 interrupt-parent = <&mdss>; 3905 interrupts = <12>; 3906 3907 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3908 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3909 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3910 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3911 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, 3912 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; 3913 clock-names = "core_iface", 3914 "core_aux", 3915 "ctrl_link", 3916 "ctrl_link_iface", 3917 "stream_pixel", 3918 "stream_1_pixel"; 3919 3920 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3921 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, 3922 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; 3923 assigned-clock-parents = <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>, 3924 <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>, 3925 <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>; 3926 3927 phys = <&usb_qmpphy_2 QMP_USB43DP_DP_PHY>; 3928 phy-names = "dp"; 3929 3930 operating-points-v2 = <&dp_opp_table>; 3931 power-domains = <&rpmhpd RPMHPD_CX>; 3932 3933 #sound-dai-cells = <0>; 3934 3935 status = "disabled"; 3936 3937 ports { 3938 #address-cells = <1>; 3939 #size-cells = <0>; 3940 3941 port@0 { 3942 reg = <0>; 3943 3944 mdss_dp0_in: endpoint { 3945 remote-endpoint = <&dpu_intf0_out>; 3946 }; 3947 }; 3948 3949 port@1 { 3950 reg = <1>; 3951 3952 mdss_dp0_out: endpoint { 3953 data-lanes = <3 2 0 1>; 3954 }; 3955 }; 3956 }; 3957 3958 dp_opp_table: opp-table { 3959 compatible = "operating-points-v2"; 3960 3961 opp-160000000 { 3962 opp-hz = /bits/ 64 <160000000>; 3963 required-opps = <&rpmhpd_opp_low_svs>; 3964 }; 3965 3966 opp-270000000 { 3967 opp-hz = /bits/ 64 <270000000>; 3968 required-opps = <&rpmhpd_opp_svs>; 3969 }; 3970 3971 opp-540000000 { 3972 opp-hz = /bits/ 64 <540000000>; 3973 required-opps = <&rpmhpd_opp_svs_l1>; 3974 }; 3975 }; 3976 }; 3977 3978 mdss_dsi0: dsi@ae94000 { 3979 compatible = "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3980 reg = <0x0 0x0ae94000 0x0 0x400>; 3981 reg-names = "dsi_ctrl"; 3982 3983 interrupts-extended = <&mdss 4>; 3984 3985 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3986 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3987 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3988 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3989 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3990 <&gcc GCC_DISP_HF_AXI_CLK>; 3991 clock-names = "byte", 3992 "byte_intf", 3993 "pixel", 3994 "core", 3995 "iface", 3996 "bus"; 3997 3998 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3999 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4000 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4001 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 4002 4003 operating-points-v2 = <&dsi0_opp_table>; 4004 power-domains = <&rpmhpd RPMHPD_CX>; 4005 4006 phys = <&mdss_dsi0_phy>; 4007 4008 #address-cells = <1>; 4009 #size-cells = <0>; 4010 4011 status = "disabled"; 4012 4013 dsi0_opp_table: opp-table { 4014 compatible = "operating-points-v2"; 4015 4016 opp-164000000 { 4017 opp-hz = /bits/ 64 <164000000>; 4018 required-opps = <&rpmhpd_opp_low_svs>; 4019 }; 4020 }; 4021 4022 ports { 4023 #address-cells = <1>; 4024 #size-cells = <0>; 4025 4026 port@0 { 4027 reg = <0>; 4028 4029 mdss_dsi0_in: endpoint { 4030 remote-endpoint = <&dpu_intf1_out>; 4031 }; 4032 }; 4033 4034 port@1 { 4035 reg = <1>; 4036 4037 mdss_dsi0_out: endpoint { 4038 }; 4039 }; 4040 }; 4041 }; 4042 4043 mdss_dsi0_phy: phy@ae94400 { 4044 compatible = "qcom,sm6150-dsi-phy-14nm"; 4045 reg = <0x0 0x0ae94400 0x0 0x100>, 4046 <0x0 0x0ae94500 0x0 0x300>, 4047 <0x0 0x0ae94800 0x0 0x124>; 4048 reg-names = "dsi_phy", 4049 "dsi_phy_lane", 4050 "dsi_pll"; 4051 4052 #clock-cells = <1>; 4053 #phy-cells = <0>; 4054 4055 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4056 <&rpmhcc RPMH_CXO_CLK>; 4057 clock-names = "iface", 4058 "ref"; 4059 4060 status = "disabled"; 4061 }; 4062 }; 4063 4064 dispcc: clock-controller@af00000 { 4065 compatible = "qcom,qcs615-dispcc"; 4066 reg = <0 0x0af00000 0 0x20000>; 4067 4068 clocks = <&rpmhcc RPMH_CXO_CLK>, 4069 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 4070 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4071 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 4072 <0>, 4073 <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>, 4074 <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>; 4075 4076 #clock-cells = <1>; 4077 #reset-cells = <1>; 4078 #power-domain-cells = <1>; 4079 }; 4080 4081 pdc: interrupt-controller@b220000 { 4082 compatible = "qcom,qcs615-pdc", "qcom,pdc"; 4083 reg = <0x0 0x0b220000 0x0 0x30000>, 4084 <0x0 0x17c000f0 0x0 0x64>; 4085 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 4086 interrupt-parent = <&intc>; 4087 #interrupt-cells = <2>; 4088 interrupt-controller; 4089 }; 4090 4091 aoss_qmp: power-management@c300000 { 4092 compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp"; 4093 reg = <0x0 0x0c300000 0x0 0x400>; 4094 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING 0>; 4095 mboxes = <&apss_shared 0>; 4096 4097 #clock-cells = <0>; 4098 }; 4099 4100 sram@c3f0000 { 4101 compatible = "qcom,rpmh-stats"; 4102 reg = <0x0 0x0c3f0000 0x0 0x400>; 4103 }; 4104 4105 sram@14680000 { 4106 compatible = "qcom,qcs615-imem", "syscon", "simple-mfd"; 4107 reg = <0x0 0x14680000 0x0 0x2c000>; 4108 ranges = <0 0 0x14680000 0x2c000>; 4109 4110 #address-cells = <1>; 4111 #size-cells = <1>; 4112 4113 pil-reloc@2a94c { 4114 compatible = "qcom,pil-reloc-info"; 4115 reg = <0x2a94c 0xc8>; 4116 }; 4117 }; 4118 4119 apps_smmu: iommu@15000000 { 4120 compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4121 reg = <0x0 0x15000000 0x0 0x80000>; 4122 #iommu-cells = <2>; 4123 #global-interrupts = <1>; 4124 dma-coherent; 4125 4126 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>, 4127 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>, 4128 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>, 4129 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>, 4130 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, 4131 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>, 4132 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>, 4133 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>, 4134 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, 4135 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>, 4136 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 4137 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 4138 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>, 4139 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>, 4140 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>, 4141 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 4142 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 4143 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, 4144 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>, 4145 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>, 4146 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>, 4147 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 4148 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>, 4149 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>, 4150 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>, 4151 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>, 4152 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>, 4153 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>, 4154 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>, 4155 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>, 4156 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>, 4157 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>, 4158 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>, 4159 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>, 4160 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>, 4161 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>, 4162 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>, 4163 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>, 4164 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>, 4165 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>, 4166 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>, 4167 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>, 4168 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>, 4169 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>, 4170 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>, 4171 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>, 4172 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>, 4173 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>, 4174 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>, 4175 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>, 4176 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>, 4177 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>, 4178 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>, 4179 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>, 4180 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>, 4181 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>, 4182 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>, 4183 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>, 4184 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>, 4185 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>, 4186 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>, 4187 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>, 4188 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>, 4189 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>, 4190 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 4191 }; 4192 4193 spmi_bus: spmi@c440000 { 4194 compatible = "qcom,spmi-pmic-arb"; 4195 reg = <0x0 0x0c440000 0x0 0x1100>, 4196 <0x0 0x0c600000 0x0 0x2000000>, 4197 <0x0 0x0e600000 0x0 0x100000>, 4198 <0x0 0x0e700000 0x0 0xa0000>, 4199 <0x0 0x0c40a000 0x0 0x26000>; 4200 reg-names = "core", 4201 "chnls", 4202 "obsrvr", 4203 "intr", 4204 "cnfg"; 4205 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4206 interrupt-names = "periph_irq"; 4207 interrupt-controller; 4208 #interrupt-cells = <4>; 4209 #address-cells = <2>; 4210 #size-cells = <0>; 4211 qcom,channel = <0>; 4212 qcom,ee = <0>; 4213 }; 4214 4215 intc: interrupt-controller@17a00000 { 4216 compatible = "arm,gic-v3"; 4217 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4218 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4219 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 4220 #address-cells = <0>; 4221 #interrupt-cells = <4>; 4222 interrupt-controller; 4223 #redistributor-regions = <1>; 4224 redistributor-stride = <0x0 0x20000>; 4225 4226 ppi-partitions { 4227 ppi_cluster0: interrupt-partition-0 { 4228 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 4229 }; 4230 4231 ppi_cluster1: interrupt-partition-1 { 4232 affinity = <&cpu6 &cpu7>; 4233 }; 4234 }; 4235 }; 4236 4237 apss_shared: mailbox@17c00000 { 4238 compatible = "qcom,qcs615-apss-shared", 4239 "qcom,sdm845-apss-shared"; 4240 reg = <0x0 0x17c00000 0x0 0x1000>; 4241 #mbox-cells = <1>; 4242 }; 4243 4244 watchdog: watchdog@17c10000 { 4245 compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt"; 4246 reg = <0x0 0x17c10000 0x0 0x1000>; 4247 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>; 4248 clocks = <&sleep_clk>; 4249 }; 4250 4251 timer@17c20000 { 4252 compatible = "arm,armv7-timer-mem"; 4253 reg = <0x0 0x17c20000 0x0 0x1000>; 4254 ranges = <0 0 0 0x20000000>; 4255 #address-cells = <1>; 4256 #size-cells = <1>; 4257 4258 frame@17c21000 { 4259 reg = <0x17c21000 0x1000>, 4260 <0x17c22000 0x1000>; 4261 frame-number = <0>; 4262 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, 4263 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 4264 }; 4265 4266 frame@17c23000 { 4267 reg = <0x17c23000 0x1000>; 4268 frame-number = <1>; 4269 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 4270 status = "disabled"; 4271 }; 4272 4273 frame@17c25000 { 4274 reg = <0x17c25000 0x1000>; 4275 frame-number = <2>; 4276 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 4277 status = "disabled"; 4278 }; 4279 4280 frame@17c27000 { 4281 reg = <0x17c27000 0x1000>; 4282 frame-number = <3>; 4283 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 4284 status = "disabled"; 4285 }; 4286 4287 frame@17c29000 { 4288 reg = <0x17c29000 0x1000>; 4289 frame-number = <4>; 4290 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 4291 status = "disabled"; 4292 }; 4293 4294 frame@17c2b000 { 4295 reg = <0x17c2b000 0x1000>; 4296 frame-number = <5>; 4297 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>; 4298 status = "disabled"; 4299 }; 4300 4301 frame@17c2d000 { 4302 reg = <0x17c2d000 0x1000>; 4303 frame-number = <6>; 4304 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 4305 status = "disabled"; 4306 }; 4307 }; 4308 4309 apps_rsc: rsc@18200000 { 4310 compatible = "qcom,rpmh-rsc"; 4311 reg = <0x0 0x18200000 0x0 0x10000>, 4312 <0x0 0x18210000 0x0 0x10000>, 4313 <0x0 0x18220000 0x0 0x10000>; 4314 reg-names = "drv-0", 4315 "drv-1", 4316 "drv-2"; 4317 4318 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, 4319 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, 4320 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>; 4321 4322 qcom,drv-id = <2>; 4323 qcom,tcs-offset = <0xd00>; 4324 qcom,tcs-config = <ACTIVE_TCS 2>, 4325 <SLEEP_TCS 3>, 4326 <WAKE_TCS 3>, 4327 <CONTROL_TCS 1>; 4328 4329 label = "apps_rsc"; 4330 power-domains = <&cluster_pd>; 4331 4332 apps_bcm_voter: bcm-voter { 4333 compatible = "qcom,bcm-voter"; 4334 }; 4335 4336 rpmhcc: clock-controller { 4337 compatible = "qcom,qcs615-rpmh-clk"; 4338 clocks = <&xo_board_clk>; 4339 clock-names = "xo"; 4340 4341 #clock-cells = <1>; 4342 }; 4343 4344 rpmhpd: power-controller { 4345 compatible = "qcom,qcs615-rpmhpd"; 4346 #power-domain-cells = <1>; 4347 operating-points-v2 = <&rpmhpd_opp_table>; 4348 4349 rpmhpd_opp_table: opp-table { 4350 compatible = "operating-points-v2"; 4351 4352 rpmhpd_opp_ret: opp-0 { 4353 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4354 }; 4355 4356 rpmhpd_opp_min_svs: opp-1 { 4357 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4358 }; 4359 4360 rpmhpd_opp_low_svs: opp-2 { 4361 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4362 }; 4363 4364 rpmhpd_opp_svs: opp-3 { 4365 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4366 }; 4367 4368 rpmhpd_opp_svs_l1: opp-4 { 4369 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4370 }; 4371 4372 rpmhpd_opp_nom: opp-5 { 4373 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4374 }; 4375 4376 rpmhpd_opp_nom_l1: opp-6 { 4377 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4378 }; 4379 4380 rpmhpd_opp_nom_l2: opp-7 { 4381 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4382 }; 4383 4384 rpmhpd_opp_turbo: opp-8 { 4385 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4386 }; 4387 4388 rpmhpd_opp_turbo_l1: opp-9 { 4389 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4390 }; 4391 }; 4392 }; 4393 }; 4394 4395 osm_l3: interconnect@18321000 { 4396 compatible = "qcom,qcs615-osm-l3", "qcom,sm8150-osm-l3", "qcom,osm-l3"; 4397 reg = <0x0 0x18321000 0x0 0x1400>; 4398 4399 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4400 clock-names = "xo", "alternate"; 4401 4402 #interconnect-cells = <1>; 4403 }; 4404 4405 usb_1_hsphy: phy@88e2000 { 4406 compatible = "qcom,qcs615-qusb2-phy"; 4407 reg = <0x0 0x88e2000 0x0 0x180>; 4408 4409 clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, <&rpmhcc RPMH_CXO_CLK>; 4410 clock-names = "cfg_ahb", "ref"; 4411 4412 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 4413 nvmem-cells = <&qusb2_hstx_trim>; 4414 4415 #phy-cells = <0>; 4416 4417 status = "disabled"; 4418 }; 4419 4420 usb_hsphy_2: phy@88e3000 { 4421 compatible = "qcom,qcs615-qusb2-phy"; 4422 reg = <0x0 0x088e3000 0x0 0x180>; 4423 4424 clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, 4425 <&rpmhcc RPMH_CXO_CLK>; 4426 clock-names = "cfg_ahb", 4427 "ref"; 4428 4429 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 4430 4431 #phy-cells = <0>; 4432 4433 status = "disabled"; 4434 }; 4435 4436 usb_qmpphy: phy@88e6000 { 4437 compatible = "qcom,qcs615-qmp-usb3-phy"; 4438 reg = <0x0 0x88e6000 0x0 0x1000>; 4439 4440 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4441 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 4442 <&gcc GCC_AHB2PHY_WEST_CLK>, 4443 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4444 clock-names = "aux", 4445 "ref", 4446 "cfg_ahb", 4447 "pipe"; 4448 4449 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 4450 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 4451 reset-names = "phy", "phy_phy"; 4452 4453 qcom,tcsr-reg = <&tcsr 0xb244>; 4454 4455 clock-output-names = "usb3_phy_pipe_clk_src"; 4456 #clock-cells = <0>; 4457 4458 #phy-cells = <0>; 4459 4460 status = "disabled"; 4461 }; 4462 4463 usb_qmpphy_2: phy@88e8000 { 4464 compatible = "qcom,qcs615-qmp-usb3-dp-phy"; 4465 reg = <0x0 0x088e8000 0x0 0x2000>; 4466 4467 clocks = <&gcc GCC_USB2_SEC_PHY_AUX_CLK>, 4468 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 4469 <&gcc GCC_AHB2PHY_WEST_CLK>, 4470 <&gcc GCC_USB2_SEC_PHY_PIPE_CLK>; 4471 clock-names = "aux", 4472 "ref", 4473 "cfg_ahb", 4474 "pipe"; 4475 4476 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >, 4477 <&gcc GCC_USB3_DP_PHY_SEC_BCR>; 4478 reset-names = "phy_phy", 4479 "dp_phy"; 4480 4481 #clock-cells = <1>; 4482 #phy-cells = <1>; 4483 4484 qcom,tcsr-reg = <&tcsr 0xbff0 0xb24c>; 4485 4486 status = "disabled"; 4487 }; 4488 4489 usb_1: usb@a6f8800 { 4490 compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; 4491 reg = <0x0 0x0a6f8800 0x0 0x400>; 4492 4493 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4494 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4495 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4496 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4497 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4498 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 4499 clock-names = "cfg_noc", 4500 "core", 4501 "iface", 4502 "sleep", 4503 "mock_utmi", 4504 "xo"; 4505 4506 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4507 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4508 assigned-clock-rates = <19200000>, <200000000>; 4509 4510 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, 4511 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, 4512 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 4513 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 4514 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 4515 interrupt-names = "pwr_event", 4516 "hs_phy_irq", 4517 "dp_hs_phy_irq", 4518 "dm_hs_phy_irq", 4519 "ss_phy_irq"; 4520 4521 power-domains = <&gcc USB30_PRIM_GDSC>; 4522 required-opps = <&rpmhpd_opp_nom>; 4523 4524 resets = <&gcc GCC_USB30_PRIM_BCR>; 4525 4526 #address-cells = <2>; 4527 #size-cells = <2>; 4528 ranges; 4529 4530 status = "disabled"; 4531 4532 usb_1_dwc3: usb@a600000 { 4533 compatible = "snps,dwc3"; 4534 reg = <0x0 0x0a600000 0x0 0xcd00>; 4535 4536 iommus = <&apps_smmu 0x140 0x0>; 4537 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>; 4538 4539 phys = <&usb_1_hsphy>, <&usb_qmpphy>; 4540 phy-names = "usb2-phy", "usb3-phy"; 4541 4542 snps,dis-u1-entry-quirk; 4543 snps,dis-u2-entry-quirk; 4544 snps,dis_u2_susphy_quirk; 4545 snps,dis_u3_susphy_quirk; 4546 snps,dis_enblslpm_quirk; 4547 snps,has-lpm-erratum; 4548 snps,hird-threshold = /bits/ 8 <0x10>; 4549 snps,usb3_lpm_capable; 4550 }; 4551 }; 4552 4553 usb_2: usb@a8f8800 { 4554 compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; 4555 reg = <0x0 0x0a8f8800 0x0 0x400>; 4556 4557 clocks = <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>, 4558 <&gcc GCC_USB20_SEC_MASTER_CLK>, 4559 <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, 4560 <&gcc GCC_USB20_SEC_SLEEP_CLK>, 4561 <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, 4562 <&gcc GCC_USB2_PRIM_CLKREF_CLK>; 4563 clock-names = "cfg_noc", 4564 "core", 4565 "iface", 4566 "sleep", 4567 "mock_utmi", 4568 "xo"; 4569 4570 assigned-clocks = <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, 4571 <&gcc GCC_USB20_SEC_MASTER_CLK>; 4572 assigned-clock-rates = <19200000>, <200000000>; 4573 4574 interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>, 4575 <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>, 4576 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 4577 <&pdc 10 IRQ_TYPE_EDGE_BOTH>; 4578 interrupt-names = "pwr_event", 4579 "hs_phy_irq", 4580 "dp_hs_phy_irq", 4581 "dm_hs_phy_irq"; 4582 4583 power-domains = <&gcc USB20_SEC_GDSC>; 4584 required-opps = <&rpmhpd_opp_nom>; 4585 4586 resets = <&gcc GCC_USB20_SEC_BCR>; 4587 4588 qcom,select-utmi-as-pipe-clk; 4589 4590 #address-cells = <2>; 4591 #size-cells = <2>; 4592 ranges; 4593 4594 status = "disabled"; 4595 4596 usb_2_dwc3: usb@a800000 { 4597 compatible = "snps,dwc3"; 4598 reg = <0x0 0x0a800000 0x0 0xcd00>; 4599 4600 iommus = <&apps_smmu 0xe0 0x0>; 4601 interrupts = <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>; 4602 4603 phys = <&usb_hsphy_2>; 4604 phy-names = "usb2-phy"; 4605 4606 snps,dis_u2_susphy_quirk; 4607 snps,dis_u3_susphy_quirk; 4608 snps,dis_enblslpm_quirk; 4609 snps,has-lpm-erratum; 4610 snps,hird-threshold = /bits/ 8 <0x10>; 4611 4612 maximum-speed = "high-speed"; 4613 }; 4614 }; 4615 4616 tsens0: thermal-sensor@c263000 { 4617 compatible = "qcom,qcs615-tsens", "qcom,tsens-v2"; 4618 reg = <0x0 0x0c263000 0x0 0x1000>, 4619 <0x0 0x0c222000 0x0 0x1000>; 4620 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>, 4621 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>; 4622 interrupt-names = "uplow", "critical"; 4623 #qcom,sensors = <16>; 4624 #thermal-sensor-cells = <1>; 4625 }; 4626 4627 remoteproc_adsp: remoteproc@62400000 { 4628 compatible = "qcom,qcs615-adsp-pas", "qcom,sm8150-adsp-pas"; 4629 reg = <0x0 0x62400000 0x0 0x4040>; 4630 4631 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING 0>, 4632 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4633 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4634 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4635 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 4636 interrupt-names = "wdog", 4637 "fatal", 4638 "ready", 4639 "handover", 4640 "stop-ack"; 4641 4642 clocks = <&rpmhcc RPMH_CXO_CLK>; 4643 clock-names = "xo"; 4644 4645 power-domains = <&rpmhpd RPMHPD_CX>; 4646 power-domain-names = "cx"; 4647 4648 memory-region = <&rproc_adsp_mem>; 4649 4650 qcom,qmp = <&aoss_qmp>; 4651 4652 qcom,smem-states = <&adsp_smp2p_out 0>; 4653 qcom,smem-state-names = "stop"; 4654 4655 status = "disabled"; 4656 4657 glink_edge: glink-edge { 4658 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING 0>; 4659 mboxes = <&apss_shared 24>; 4660 label = "lpass"; 4661 qcom,remote-pid = <2>; 4662 4663 fastrpc { 4664 compatible = "qcom,fastrpc"; 4665 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4666 label = "adsp"; 4667 #address-cells = <1>; 4668 #size-cells = <0>; 4669 4670 compute-cb@3 { 4671 compatible = "qcom,fastrpc-compute-cb"; 4672 reg = <3>; 4673 iommus = <&apps_smmu 0x1723 0x0>; 4674 dma-coherent; 4675 }; 4676 4677 compute-cb@4 { 4678 compatible = "qcom,fastrpc-compute-cb"; 4679 reg = <4>; 4680 iommus = <&apps_smmu 0x1724 0x0>; 4681 dma-coherent; 4682 }; 4683 4684 compute-cb@5 { 4685 compatible = "qcom,fastrpc-compute-cb"; 4686 reg = <5>; 4687 iommus = <&apps_smmu 0x1725 0x0>; 4688 dma-coherent; 4689 }; 4690 4691 compute-cb@6 { 4692 compatible = "qcom,fastrpc-compute-cb"; 4693 reg = <6>; 4694 iommus = <&apps_smmu 0x1726 0x0>; 4695 qcom,nsessions = <5>; 4696 dma-coherent; 4697 }; 4698 }; 4699 }; 4700 }; 4701 4702 cpufreq_hw: cpufreq@18323000 { 4703 compatible = "qcom,qcs615-cpufreq-hw", "qcom,cpufreq-hw"; 4704 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 4705 reg-names = "freq-domain0", "freq-domain1"; 4706 4707 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4708 clock-names = "xo", "alternate"; 4709 4710 #freq-domain-cells = <1>; 4711 #clock-cells = <1>; 4712 }; 4713 }; 4714 4715 arch_timer: timer { 4716 compatible = "arm,armv8-timer"; 4717 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 4718 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 4719 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 4720 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>; 4721 }; 4722 4723 thermal-zones { 4724 aoss-thermal { 4725 thermal-sensors = <&tsens0 0>; 4726 4727 trips { 4728 aoss-critical { 4729 temperature = <115000>; 4730 hysteresis = <1000>; 4731 type = "critical"; 4732 }; 4733 }; 4734 }; 4735 4736 cpuss-0-thermal { 4737 thermal-sensors = <&tsens0 1>; 4738 4739 trips { 4740 cpuss0-critical { 4741 temperature = <115000>; 4742 hysteresis = <1000>; 4743 type = "critical"; 4744 }; 4745 }; 4746 }; 4747 4748 cpuss-1-thermal { 4749 thermal-sensors = <&tsens0 2>; 4750 4751 trips { 4752 cpuss1-critical { 4753 temperature = <115000>; 4754 hysteresis = <1000>; 4755 type = "critical"; 4756 }; 4757 }; 4758 }; 4759 4760 cpuss-2-thermal { 4761 thermal-sensors = <&tsens0 3>; 4762 4763 trips { 4764 cpuss2-critical { 4765 temperature = <115000>; 4766 hysteresis = <1000>; 4767 type = "critical"; 4768 }; 4769 }; 4770 }; 4771 4772 cpuss-3-thermal { 4773 thermal-sensors = <&tsens0 4>; 4774 4775 trips { 4776 cpuss3-critical { 4777 temperature = <115000>; 4778 hysteresis = <1000>; 4779 type = "critical"; 4780 }; 4781 }; 4782 }; 4783 4784 cpu-1-0-thermal { 4785 thermal-sensors = <&tsens0 5>; 4786 4787 trips { 4788 cpu-critical { 4789 temperature = <115000>; 4790 hysteresis = <1000>; 4791 type = "critical"; 4792 }; 4793 }; 4794 }; 4795 4796 cpu-1-1-thermal { 4797 thermal-sensors = <&tsens0 6>; 4798 4799 trips { 4800 cpu-critical { 4801 temperature = <115000>; 4802 hysteresis = <1000>; 4803 type = "critical"; 4804 }; 4805 }; 4806 }; 4807 4808 cpu-1-2-thermal { 4809 thermal-sensors = <&tsens0 7>; 4810 4811 trips { 4812 cpu-critical { 4813 temperature = <115000>; 4814 hysteresis = <1000>; 4815 type = "critical"; 4816 }; 4817 }; 4818 }; 4819 4820 cpu-1-3-thermal { 4821 thermal-sensors = <&tsens0 8>; 4822 4823 trips { 4824 cpu-critical { 4825 temperature = <115000>; 4826 hysteresis = <1000>; 4827 type = "critical"; 4828 }; 4829 }; 4830 }; 4831 4832 gpu-thermal { 4833 thermal-sensors = <&tsens0 9>; 4834 4835 trips { 4836 gpu-critical { 4837 temperature = <115000>; 4838 hysteresis = <1000>; 4839 type = "critical"; 4840 }; 4841 }; 4842 }; 4843 4844 q6-hvx-thermal { 4845 thermal-sensors = <&tsens0 10>; 4846 4847 trips { 4848 q6-hvx-critical { 4849 temperature = <115000>; 4850 hysteresis = <1000>; 4851 type = "critical"; 4852 }; 4853 }; 4854 }; 4855 4856 mdm-core-thermal { 4857 thermal-sensors = <&tsens0 11>; 4858 4859 trips { 4860 mdm-core-critical { 4861 temperature = <115000>; 4862 hysteresis = <1000>; 4863 type = "critical"; 4864 }; 4865 }; 4866 }; 4867 4868 camera-thermal { 4869 thermal-sensors = <&tsens0 12>; 4870 4871 trips { 4872 camera-critical { 4873 temperature = <115000>; 4874 hysteresis = <1000>; 4875 type = "critical"; 4876 }; 4877 }; 4878 }; 4879 4880 wlan-thermal { 4881 thermal-sensors = <&tsens0 13>; 4882 4883 trips { 4884 wlan-critical { 4885 temperature = <115000>; 4886 hysteresis = <1000>; 4887 type = "critical"; 4888 }; 4889 }; 4890 }; 4891 4892 display-thermal { 4893 thermal-sensors = <&tsens0 14>; 4894 4895 trips { 4896 display-critical { 4897 temperature = <115000>; 4898 hysteresis = <1000>; 4899 type = "critical"; 4900 }; 4901 }; 4902 }; 4903 4904 video-thermal { 4905 thermal-sensors = <&tsens0 15>; 4906 4907 trips { 4908 video-critical { 4909 temperature = <115000>; 4910 hysteresis = <1000>; 4911 type = "critical"; 4912 }; 4913 }; 4914 }; 4915 }; 4916}; 4917