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/linux/Documentation/hwmon/
H A Dltc4245.rst52 in1_input 12v input voltage (mV)
53 in2_input 5v input voltage (mV)
54 in3_input 3v input voltage (mV)
55 in4_input Vee (-12v) input voltage (mV)
58 in2_min_alarm 5v input undervoltage alarm
63 curr2_input 5v current (mA)
68 curr2_max_alarm 5v overcurrent alarm
72 in5_input 12v output voltage (mV)
73 in6_input 5v output voltage (mV)
74 in7_input 3v output voltage (mV)
[all …]
H A Dxdpe12284.rst41 - VR12.0 mode, 5-mV DAC - 0x01.
42 - VR12.5 mode, 10-mV DAC - 0x02.
43 - IMVP9 mode, 5-mV DAC - 0x03.
44 - AMD mode 6.25mV - 0x10.
/linux/include/dt-bindings/usb/
H A Dpd.h26 #define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */
29 #define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) argument
32 #define PDO_FIXED(mv, ma, flags) \ argument
34 PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma))
36 #define VSAFE5V 5000 /* mv units */
38 #define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */
39 #define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */
42 #define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT) argument
43 #define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT) argument
50 #define PDO_VAR_MAX_VOLT_SHIFT 20 /* 50mV units */
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dmaxim,max8952.yaml42 enum: [0, 1, 2, 3, 4, 5, 6, 7]
46 - 0: 32mV/us
47 - 1: 16mV/us
48 - 2: 8mV/us
49 - 3: 4mV/us
50 - 4: 2mV/us
51 - 5: 1mV/us
52 - 6: 0.5mV/us
53 - 7: 0.25mV/us
54 Defaults to 32mV/us if not specified.
/linux/include/linux/usb/
H A Dpd.h20 PD_CTRL_PING = 5,
45 PD_DATA_BATT_STATUS = 5,
60 PD_EXT_BATT_CAP = 5,
86 #define PD_HEADER_DATA_ROLE BIT(5)
232 #define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */
235 #define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) argument
238 #define PDO_FIXED(mv, ma, flags) \ argument
240 PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma))
242 #define VSAFE5V 5000 /* mv units */
244 #define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_aldebaran.h43 #define FEATURE_DPM_LCLK_BIT 5
116 #define THROTTLER_SPARE_5 5
292 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
293 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
342 int16_t GFX_Guardband_Voltage_Cold[8]; // mV [signed]
343 int16_t GFX_Guardband_Voltage_Mid[8]; // mV [signed]
344 int16_t GFX_Guardband_Voltage_Hot[8]; // mV [signed]
347 int16_t SOC_Guardband_Voltage_Cold[8]; // mV [signed]
348 int16_t SOC_Guardband_Voltage_Mid[8]; // mV [signed]
349 int16_t SOC_Guardband_Voltage_Hot[8]; // mV [signed]
[all …]
H A Dsmu11_driver_if_sienna_cichlid.h81 #define FEATURE_DPM_SOCCLK_BIT 5
200 #define THROTTLER_TEMP_VR_MEM0_BIT 5
224 #define FW_DSTATE_MP1_DS_BIT 5
453 #define NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS 5
633 uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS]; // mV(Q2)
636 uint16_t PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //In mV(Q2)
646 uint16_t UlvVoltageOffsetSoc; // In mV(Q2)
647 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
649 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
650 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode
[all …]
H A Dsmu11_driver_if_navi10.h76 #define FEATURE_DPM_MP0CLK_BIT 5
179 #define THROTTLER_TEMP_VR_MEM0_BIT 5
202 #define FW_DSTATE_MP1_DS_BIT 5
558 uint16_t UlvVoltageOffsetSoc; // In mV(Q2)
559 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
569 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
570 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode
574 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
575 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
576 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
[all …]
H A Dsmu13_driver_if_v13_0_0.h53 #define FEATURE_DPM_SOCCLK_BIT 5
191 #define THROTTLER_TEMP_VR_GFX_BIT 5
216 #define FW_DSTATE_SOC_LIV_MIN_BIT 5
669 #define PP_NUM_RTAVFS_PWL_ZONES 5
846 // PLL 5
863 uint16_t InitGfx; // In mV(Q2) , should be 0?
864 uint16_t InitSoc; // In mV(Q2)
865 uint16_t InitU; // In Mv(Q2)
919 uint16_t DcTol; // mV Q2
920 uint16_t DcBtcGb; // mV Q2
[all …]
H A Dsmu13_driver_if_v13_0_7.h54 #define FEATURE_DPM_SOCCLK_BIT 5
192 #define THROTTLER_TEMP_VR_GFX_BIT 5
217 #define FW_DSTATE_SOC_LIV_MIN_BIT 5
670 #define PP_NUM_RTAVFS_PWL_ZONES 5
855 // PLL 5
872 uint16_t InitGfx; // In mV(Q2) , should be 0?
873 uint16_t InitSoc; // In mV(Q2)
874 uint16_t InitU; // In Mv(Q2) not applicable
928 uint16_t DcTol; // mV Q2
929 uint16_t DcBtcGb; // mV Q2
[all …]
H A Dsmu14_driver_if_v14_0.h51 #define FEATURE_DPM_SOCCLK_BIT 5
200 #define THROTTLER_TEMP_VR_GFX_BIT 5
224 #define FW_DSTATE_SOC_LIV_MIN_BIT 5
590 MEM_VENDOR_NANYA, // 5
680 #define PP_NUM_RTAVFS_PWL_ZONES 5
698 #define PP_OD_FEATURE_FAN_LEGACY_BIT 5
757 uint16_t VddGfxVmax; // in mV
820 uint16_t VddGfxVmax; // in mV
864 uint32_t Spare[5];
947 // PLL 5
[all …]
H A Dsmu11_driver_if_arcturus.h61 #define FEATURE_DPM_MP0CLK_BIT 5
192 #define THROTTLER_TEMP_VR_MEM_BIT 5
217 #define WORKLOAD_PPLIB_COUNT 5
497 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
504 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
505 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
506 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
507 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
526 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2)
583 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dphy-stm32-usbphyc.yaml110 - <1> increases the level by 5 to 7 mV
111 - <2> increases the level by 10 to 14 mV
112 - <3> decreases the level by 5 to 7 mV
134 - <5> = 20.345 mA target current / nominal + 7.8%
166 - <1> = threshold shift by +7 mV
167 - <2> = threshold shift by -5 mV
168 - <3> = threshold shift by +14 mV
182 - <1> = offset of +5 mV
183 - <2> = offset of +10 mV
184 - <3> = offset of -5 mV
[all …]
/linux/drivers/scsi/
H A Dch.c255 cmd[1] = ((ch->device->lun & 0x7) << 5) | in ch_read_element_status()
260 cmd[5] = 1; in ch_read_element_status()
292 cmd[1] = (ch->device->lun & 0x7) << 5; in ch_init_elem()
312 cmd[1] = (ch->device->lun & 0x7) << 5; in ch_readconfig()
362 i+5,i+1,vendor_firsts[i],vendor_counts[i], in ch_readconfig()
437 cmd[1] = (ch->device->lun & 0x7) << 5; in ch_position()
441 cmd[5] = elem & 0xff; in ch_position()
456 cmd[1] = (ch->device->lun & 0x7) << 5; in ch_move()
460 cmd[5] = src & 0xff; in ch_move()
479 cmd[1] = (ch->device->lun & 0x7) << 5; in ch_exchange()
[all …]
/linux/drivers/staging/media/rkvdec/
H A Drkvdec-vp9.c43 u8 comp_mode[5];
44 u8 comp_ref[5];
45 u8 single_ref[5][2];
51 u8 padding1[5];
53 u8 padding2[5];
55 u8 padding3[5];
69 } mv; member
111 u32 comp[5][2];
112 u32 comp_ref[5][2];
113 u32 single_ref[5][2][2];
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_ddi_buf_trans.c53 /* Idx NT mV d T mV d db */
59 { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } }, /* 5: 600 900 3.5 */
126 /* Idx NT mV d T mV df db */
132 { .hsw = { 0x00D7FFFF, 0x00140006, 0x0 } }, /* 5: 600 800 2.5 */
362 /* Idx NT mV diff db */
368 { .bxt = { 116, 0x9A, 0, 85, } }, /* 5: 600 3.5 */
381 /* Idx NT mV diff db */
387 { .bxt = { 48, 0, 0, 104, } }, /* 5: 250 1.5 */
403 /* Idx NT mV diff db */
409 { .bxt = { 77, 0x9A, 0, 85, } }, /* 5: 600 3.5 */
[all …]
/linux/Documentation/devicetree/bindings/input/
H A Dti,drv260x.yaml58 enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
67 vib-rated-mv:
71 If this is not set then the value will be defaulted to 3200 mV.
74 vib-overdrive-mv:
78 If this is not set then the value will be defaulted to 3200 mV.
99 haptics@5a {
106 vib-rated-mv = <3200>;
107 vib-overdrive-mv = <3200>;
/linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_vp9_req_lat_if.c47 u8 single_ref_prob[5][2];
55 u8 padding[5];
60 u8 padding[5];
67 u8 padding[5];
92 u32 band_1_5[5][6];
100 u32 band_1_5[5][6][4];
104 u32 comp_inter[5][2];
106 u32 comp_ref[5][2];
108 u32 single_ref[5][2][2];
340 * @mv: mv working buffer
[all …]
/linux/drivers/media/v4l2-core/
H A Dv4l2-vp9.c145 { 24, 7, 5 }, /* a/l both split */
179 { 5, 52, 13 },
225 { /* Coeff Band 5 */
275 { /* Coeff Band 5 */
327 { /* Coeff Band 5 */
377 { /* Coeff Band 5 */
431 { /* Coeff Band 5 */
453 { 5, 90, 141 },
481 { /* Coeff Band 5 */
528 { 5, 105, 174 },
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dcs35l33.txt22 0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with
23 a value of 1 and will increase at a step size of 100mV until a maximum of
24 8000mV.
62 stage enters LDO operation. Starts as a default value of 50mV for a value
63 of 1 and increases with a step size of 50mV to a maximum of 750mV (value of
72 from 0 to 7 for delays of 5ms, 10ms, 50ms, 100ms, 200ms, 500ms, 1000ms.
80 The reference voltage starts at 3000mV with a value of 0x3 and is increased
81 by 100mV per step to a maximum of 5500mV.
91 1800mV with a step size of 50mV up to a maximum value of 1750mV.
92 Default is 1800mV.
[all …]
H A Dcs35l36.txt14 converter's output voltage in mV. The range is from 2550mV to 12000mV with
15 increments of 50mV.
65 1 = 5ms
69 5 = 200ms
75 weak-FET operation. The range is 50mV to 700mV in 50mV increments.
/linux/include/linux/mfd/
H A Dmenelaus.h21 extern int menelaus_set_vmem(unsigned int mV);
22 extern int menelaus_set_vio(unsigned int mV);
23 extern int menelaus_set_vmmc(unsigned int mV);
24 extern int menelaus_set_vaux(unsigned int mV);
25 extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
32 #define EN_VAUX_SLEEP (1 << 5)
/linux/drivers/mfd/
H A Dmenelaus.c105 #define MENELAUS_HOTDIE_IRQ 5 /* Hot die detect */
118 #define VCORE_CTRL1_BYP_COMP (1 << 5)
122 #define GPIO_CTRL_SLOTSELEN (1 << 5)
136 #define MCT_CTRL2_S2CD_BUFEN (1 << 5)
448 static int menelaus_set_voltage(const struct menelaus_vtg *vtg, int mV, in menelaus_set_voltage() argument
463 "to %d mV (reg 0x%02x, val 0x%02x)\n", in menelaus_set_voltage()
464 vtg->name, mV, vtg->vtg_reg, val); in menelaus_set_voltage()
505 { 1125, 5 },
535 dev_dbg(&c->dev, "Setting VCORE FLOOR to %d mV and ROOF to %d mV\n", in menelaus_set_vcore_hw()
573 int menelaus_set_vmem(unsigned int mV) in menelaus_set_vmem() argument
[all …]
/linux/drivers/hwmon/pmbus/
H A Dstpddc60.c38 * and limit value in steps of 50mv in the range 0 (50mv) to 7 (400mv).
47 v = 250 + (vout - 1) * 5; /* Convert VID to mv */ in stpddc60_get_offset()
48 l = (limit * 1000L) >> 8; /* Convert LINEAR to mv */ in stpddc60_get_offset()
69 m = ((s16)((word & 0x7ff) << 5)) >> 5; in stpddc60_adjust_linear()
106 * is expected. Clear the top 5 bits to set the exponent part to zero to
H A Dxdpe12284.c17 #define XDPE122_PROT_VR12_5MV 0x01 /* VR12.0 mode, 5-mV DAC */
18 #define XDPE122_PROT_VR12_5_10MV 0x02 /* VR12.5 mode, 10-mV DAC */
19 #define XDPE122_PROT_IMVP9_10MV 0x03 /* IMVP9 mode, 10-mV DAC */
20 #define XDPE122_AMD_625MV 0x10 /* AMD mode 6.25mV */
41 mantissa = ((s16)((ret & GENMASK(10, 0)) << 5)) >> 5; in xdpe122_read_word_data()
56 return 1 + DIV_ROUND_CLOSEST(val - 250, 5); in xdpe122_read_word_data()
85 switch (vout_mode >> 5) { in xdpe122_identify()

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