1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright 2025 Cix Technology Group Co., Ltd. 4 * 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/cix,sky1.h> 9#include <dt-bindings/clock/cix,sky1-audss-cru.h> 10#include <dt-bindings/reset/cix,sky1-system-control.h> 11#include <dt-bindings/reset/cix,sky1-s5-system-control.h> 12#include <dt-bindings/reset/cix,sky1-audss-cru.h> 13#include "sky1-power.h" 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <2>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 compatible = "arm,cortex-a520"; 26 enable-method = "psci"; 27 reg = <0x0 0x0>; 28 device_type = "cpu"; 29 power-domains = <&scmi_dvfs SKY1_PERF_CPU_L>; 30 power-domain-names = "perf"; 31 capacity-dmips-mhz = <403>; 32 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 33 }; 34 35 cpu1: cpu@100 { 36 compatible = "arm,cortex-a520"; 37 enable-method = "psci"; 38 reg = <0x0 0x100>; 39 device_type = "cpu"; 40 power-domains = <&scmi_dvfs SKY1_PERF_CPU_L>; 41 power-domain-names = "perf"; 42 capacity-dmips-mhz = <403>; 43 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 44 }; 45 46 cpu2: cpu@200 { 47 compatible = "arm,cortex-a520"; 48 enable-method = "psci"; 49 reg = <0x0 0x200>; 50 device_type = "cpu"; 51 power-domains = <&scmi_dvfs SKY1_PERF_CPU_L>; 52 power-domain-names = "perf"; 53 capacity-dmips-mhz = <403>; 54 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 55 }; 56 57 cpu3: cpu@300 { 58 compatible = "arm,cortex-a520"; 59 enable-method = "psci"; 60 reg = <0x0 0x300>; 61 device_type = "cpu"; 62 power-domains = <&scmi_dvfs SKY1_PERF_CPU_L>; 63 power-domain-names = "perf"; 64 capacity-dmips-mhz = <403>; 65 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 66 }; 67 68 cpu4: cpu@400 { 69 compatible = "arm,cortex-a720"; 70 enable-method = "psci"; 71 reg = <0x0 0x400>; 72 device_type = "cpu"; 73 power-domains = <&scmi_dvfs SKY1_PERF_CPU_M0>; 74 power-domain-names = "perf"; 75 capacity-dmips-mhz = <1024>; 76 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; 77 }; 78 79 cpu5: cpu@500 { 80 compatible = "arm,cortex-a720"; 81 enable-method = "psci"; 82 reg = <0x0 0x500>; 83 device_type = "cpu"; 84 power-domains = <&scmi_dvfs SKY1_PERF_CPU_M0>; 85 power-domain-names = "perf"; 86 capacity-dmips-mhz = <1024>; 87 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; 88 }; 89 90 cpu6: cpu@600 { 91 compatible = "arm,cortex-a720"; 92 enable-method = "psci"; 93 reg = <0x0 0x600>; 94 device_type = "cpu"; 95 power-domains = <&scmi_dvfs SKY1_PERF_CPU_M1>; 96 power-domain-names = "perf"; 97 capacity-dmips-mhz = <1024>; 98 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; 99 }; 100 101 cpu7: cpu@700 { 102 compatible = "arm,cortex-a720"; 103 enable-method = "psci"; 104 reg = <0x0 0x700>; 105 device_type = "cpu"; 106 power-domains = <&scmi_dvfs SKY1_PERF_CPU_M1>; 107 power-domain-names = "perf"; 108 capacity-dmips-mhz = <1024>; 109 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; 110 }; 111 112 cpu8: cpu@800 { 113 compatible = "arm,cortex-a720"; 114 enable-method = "psci"; 115 reg = <0x0 0x800>; 116 device_type = "cpu"; 117 power-domains = <&scmi_dvfs SKY1_PERF_CPU_B0>; 118 power-domain-names = "perf"; 119 capacity-dmips-mhz = <1024>; 120 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; 121 }; 122 123 cpu9: cpu@900 { 124 compatible = "arm,cortex-a720"; 125 enable-method = "psci"; 126 reg = <0x0 0x900>; 127 device_type = "cpu"; 128 power-domains = <&scmi_dvfs SKY1_PERF_CPU_B0>; 129 power-domain-names = "perf"; 130 capacity-dmips-mhz = <1024>; 131 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; 132 }; 133 134 cpu10: cpu@a00 { 135 compatible = "arm,cortex-a720"; 136 enable-method = "psci"; 137 reg = <0x0 0xa00>; 138 device_type = "cpu"; 139 power-domains = <&scmi_dvfs SKY1_PERF_CPU_B1>; 140 power-domain-names = "perf"; 141 capacity-dmips-mhz = <1024>; 142 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; 143 }; 144 145 cpu11: cpu@b00 { 146 compatible = "arm,cortex-a720"; 147 enable-method = "psci"; 148 reg = <0x0 0xb00>; 149 device_type = "cpu"; 150 power-domains = <&scmi_dvfs SKY1_PERF_CPU_B1>; 151 power-domain-names = "perf"; 152 capacity-dmips-mhz = <1024>; 153 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; 154 }; 155 156 cpu-map { 157 cluster0 { 158 core0 { 159 cpu = <&cpu0>; 160 }; 161 core1 { 162 cpu = <&cpu1>; 163 }; 164 core2 { 165 cpu = <&cpu2>; 166 }; 167 core3 { 168 cpu = <&cpu3>; 169 }; 170 core4 { 171 cpu = <&cpu4>; 172 }; 173 core5 { 174 cpu = <&cpu5>; 175 }; 176 core6 { 177 cpu = <&cpu6>; 178 }; 179 core7 { 180 cpu = <&cpu7>; 181 }; 182 core8 { 183 cpu = <&cpu8>; 184 }; 185 core9 { 186 cpu = <&cpu9>; 187 }; 188 core10 { 189 cpu = <&cpu10>; 190 }; 191 core11 { 192 cpu = <&cpu11>; 193 }; 194 }; 195 }; 196 197 idle-states { 198 CPU_SLEEP_0: cpu-sleep-0 { 199 compatible = "arm,idle-state"; 200 arm,psci-suspend-param = <0x0010000>; 201 local-timer-stop; 202 entry-latency-us = <34>; 203 exit-latency-us = <100>; 204 min-residency-us = <3000>; 205 }; 206 207 CPU_SLEEP_1: cpu-sleep-1 { 208 compatible = "arm,idle-state"; 209 arm,psci-suspend-param = <0x0010000>; 210 local-timer-stop; 211 entry-latency-us = <31>; 212 exit-latency-us = <79>; 213 min-residency-us = <3000>; 214 }; 215 216 CLUSTER_SLEEP_0: cluster-sleep-0 { 217 compatible = "arm,idle-state"; 218 arm,psci-suspend-param = <0x1010000>; 219 local-timer-stop; 220 entry-latency-us = <41>; 221 exit-latency-us = <104>; 222 min-residency-us = <4000>; 223 }; 224 }; 225 }; 226 227 firmware { 228 ap_to_pm_scmi: scmi { 229 compatible = "arm,scmi"; 230 mbox-names = "tx", "rx"; 231 mboxes = <&mbox_ap2pm 8>, <&mbox_pm2ap 8>; 232 shmem = <&ap2pm_scmi_mem>, <&pm2ap_scmi_mem>; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 236 scmi_dvfs: protocol@13 { 237 reg = <0x13>; 238 #power-domain-cells = <1>; 239 }; 240 241 scmi_clk: protocol@14 { 242 reg = <0x14>; 243 #clock-cells = <1>; 244 }; 245 }; 246 247 ap_to_tfa_scmi: scmi-1 { 248 compatible = "arm,scmi-smc"; 249 arm,smc-id = <0xc2000001>; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 shmem = <&ap_tfa_scmi_mem>; 253 254 smc_devpd: protocol@11 { 255 reg = <0x11>; 256 #power-domain-cells = <1>; 257 }; 258 }; 259 }; 260 261 pmu-a520 { 262 compatible = "arm,cortex-a520-pmu"; 263 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>; 264 }; 265 266 pmu-a720 { 267 compatible = "arm,cortex-a720-pmu"; 268 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>; 269 }; 270 271 psci { 272 compatible = "arm,psci-1.0"; 273 method = "smc"; 274 }; 275 276 s5_gpio_apb_clk: clock-100000000 { 277 compatible = "fixed-clock"; 278 #clock-cells = <0>; 279 clock-frequency = <100000000>; 280 clock-output-names = "s5_gpio_apb_clk"; 281 }; 282 283 soc@0 { 284 compatible = "simple-bus"; 285 ranges = <0 0 0 0 0x20 0>; 286 dma-ranges; 287 #address-cells = <2>; 288 #size-cells = <2>; 289 290 i2c0: i2c@4010000 { 291 compatible = "cdns,i2c-r1p14"; 292 reg = <0x0 0x04010000 0x0 0x10000>; 293 clock-frequency = <400000>; 294 clocks = <&scmi_clk CLK_TREE_FCH_I2C0_APB>; 295 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH 0>; 296 status = "disabled"; 297 }; 298 299 i2c1: i2c@4020000 { 300 compatible = "cdns,i2c-r1p14"; 301 reg = <0x0 0x04020000 0x0 0x10000>; 302 clock-frequency = <400000>; 303 clocks = <&scmi_clk CLK_TREE_FCH_I2C1_APB>; 304 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH 0>; 305 status = "disabled"; 306 }; 307 308 i2c2: i2c@4030000 { 309 compatible = "cdns,i2c-r1p14"; 310 reg = <0x0 0x04030000 0x0 0x10000>; 311 clock-frequency = <400000>; 312 clocks = <&scmi_clk CLK_TREE_FCH_I2C2_APB>; 313 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH 0>; 314 status = "disabled"; 315 }; 316 317 i2c3: i2c@4040000 { 318 compatible = "cdns,i2c-r1p14"; 319 reg = <0x0 0x04040000 0x0 0x10000>; 320 clock-frequency = <400000>; 321 clocks = <&scmi_clk CLK_TREE_FCH_I2C3_APB>; 322 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; 323 status = "disabled"; 324 }; 325 326 i2c4: i2c@4050000 { 327 compatible = "cdns,i2c-r1p14"; 328 reg = <0x0 0x04050000 0x0 0x10000>; 329 clock-frequency = <400000>; 330 clocks = <&scmi_clk CLK_TREE_FCH_I2C4_APB>; 331 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH 0>; 332 status = "disabled"; 333 }; 334 335 i2c5: i2c@4060000 { 336 compatible = "cdns,i2c-r1p14"; 337 reg = <0x0 0x04060000 0x0 0x10000>; 338 clock-frequency = <400000>; 339 clocks = <&scmi_clk CLK_TREE_FCH_I2C5_APB>; 340 interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH 0>; 341 status = "disabled"; 342 }; 343 344 i2c6: i2c@4070000 { 345 compatible = "cdns,i2c-r1p14"; 346 reg = <0x0 0x04070000 0x0 0x10000>; 347 clock-frequency = <400000>; 348 clocks = <&scmi_clk CLK_TREE_FCH_I2C6_APB>; 349 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH 0>; 350 status = "disabled"; 351 }; 352 353 i2c7: i2c@4080000 { 354 compatible = "cdns,i2c-r1p14"; 355 reg = <0x0 0x04080000 0x0 0x10000>; 356 clock-frequency = <400000>; 357 clocks = <&scmi_clk CLK_TREE_FCH_I2C7_APB>; 358 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 359 status = "disabled"; 360 }; 361 362 spi0: spi@4090000 { 363 compatible = "cix,sky1-spi-r1p6", "cdns,spi-r1p6"; 364 reg = <0x0 0x04090000 0x0 0x10000>; 365 clocks = <&scmi_clk CLK_TREE_FCH_SPI0_APB>, 366 <&scmi_clk CLK_TREE_FCH_SPI0_APB>; 367 clock-names = "ref_clk", "pclk"; 368 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; 369 status = "disabled"; 370 }; 371 372 spi1: spi@40a0000 { 373 compatible = "cix,sky1-spi-r1p6", "cdns,spi-r1p6"; 374 reg = <0x0 0x040a0000 0x0 0x10000>; 375 clocks = <&scmi_clk CLK_TREE_FCH_SPI1_APB>, 376 <&scmi_clk CLK_TREE_FCH_SPI1_APB>; 377 clock-names = "ref_clk", "pclk"; 378 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>; 379 status = "disabled"; 380 }; 381 382 uart0: serial@40b0000 { 383 compatible = "arm,pl011", "arm,primecell"; 384 reg = <0x0 0x040b0000 0x0 0x1000>; 385 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>; 386 clocks = <&scmi_clk CLK_TREE_FCH_UART0_FUNC>, <&scmi_clk CLK_TREE_FCH_UART0_APB>; 387 clock-names = "uartclk", "apb_pclk"; 388 status = "disabled"; 389 }; 390 391 uart1: serial@40c0000 { 392 compatible = "arm,pl011", "arm,primecell"; 393 reg = <0x0 0x040c0000 0x0 0x1000>; 394 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>; 395 clocks = <&scmi_clk CLK_TREE_FCH_UART1_FUNC>, <&scmi_clk CLK_TREE_FCH_UART1_APB>; 396 clock-names = "uartclk", "apb_pclk"; 397 status = "disabled"; 398 }; 399 400 uart2: serial@40d0000 { 401 compatible = "arm,pl011", "arm,primecell"; 402 reg = <0x0 0x040d0000 0x0 0x1000>; 403 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 404 clocks = <&scmi_clk CLK_TREE_FCH_UART2_FUNC>, <&scmi_clk CLK_TREE_FCH_UART2_APB>; 405 clock-names = "uartclk", "apb_pclk"; 406 status = "disabled"; 407 }; 408 409 uart3: serial@40e0000 { 410 compatible = "arm,pl011", "arm,primecell"; 411 reg = <0x0 0x040e0000 0x0 0x1000>; 412 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>; 413 clocks = <&scmi_clk CLK_TREE_FCH_UART3_FUNC>, <&scmi_clk CLK_TREE_FCH_UART3_APB>; 414 clock-names = "uartclk", "apb_pclk"; 415 status = "disabled"; 416 }; 417 418 i3c0: i3c@40f0000 { 419 compatible = "cdns,i3c-master"; 420 reg = <0x0 0x040f0000 0x0 0x10000>; 421 #address-cells = <3>; 422 #size-cells = <0>; 423 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; 424 clocks = <&scmi_clk CLK_TREE_FCH_I3C0_APB>, 425 <&scmi_clk CLK_TREE_FCH_I3C0_FUNC>; 426 clock-names = "pclk", "sysclk"; 427 i3c-scl-hz = <400000>; 428 i2c-scl-hz = <100000>; 429 status = "disabled"; 430 }; 431 432 i3c1: i3c@4100000 { 433 compatible = "cdns,i3c-master"; 434 reg = <0x0 0x04100000 0x0 0x10000>; 435 #address-cells = <3>; 436 #size-cells = <0>; 437 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>; 438 clocks = <&scmi_clk CLK_TREE_FCH_I3C1_APB>, 439 <&scmi_clk CLK_TREE_FCH_I3C1_FUNC>; 440 clock-names = "pclk", "sysclk"; 441 i3c-scl-hz = <400000>; 442 i2c-scl-hz = <100000>; 443 status = "disabled"; 444 }; 445 446 fch_gpio0: gpio-controller@4120000 { 447 compatible = "cdns,gpio-r1p02"; 448 reg = <0x0 0x4120000 0x0 0x1000>; 449 clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>; 450 451 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>; 452 453 gpio-controller; 454 #gpio-cells = <2>; 455 ngpios = <32>; 456 457 interrupt-controller; 458 #interrupt-cells = <2>; 459 status = "disabled"; 460 }; 461 462 fch_gpio1: gpio-controller@4130000 { 463 compatible = "cdns,gpio-r1p02"; 464 reg = <0x0 0x4130000 0x0 0x1000>; 465 clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>; 466 467 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 468 469 gpio-controller; 470 #gpio-cells = <2>; 471 ngpios = <32>; 472 473 interrupt-controller; 474 #interrupt-cells = <2>; 475 status = "disabled"; 476 }; 477 478 fch_gpio2: gpio-controller@4140000 { 479 compatible = "cdns,gpio-r1p02"; 480 reg = <0x0 0x4140000 0x0 0x1000>; 481 clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>; 482 483 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>; 484 485 gpio-controller; 486 #gpio-cells = <2>; 487 ngpios = <32>; 488 489 interrupt-controller; 490 #interrupt-cells = <2>; 491 status = "disabled"; 492 }; 493 494 fch_gpio3: gpio-controller@4150000 { 495 compatible = "cdns,gpio-r1p02"; 496 reg = <0x0 0x4150000 0x0 0x1000>; 497 clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>; 498 499 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>; 500 501 gpio-controller; 502 #gpio-cells = <2>; 503 ngpios = <17>; 504 505 interrupt-controller; 506 #interrupt-cells = <2>; 507 status = "disabled"; 508 }; 509 510 syscon: syscon@4160000 { 511 compatible = "cix,sky1-system-control", "syscon"; 512 reg = <0x0 0x4160000 0x0 0x100>; 513 #reset-cells = <1>; 514 }; 515 516 iomuxc: pinctrl@4170000 { 517 compatible = "cix,sky1-pinctrl"; 518 reg = <0x0 0x04170000 0x0 0x1000>; 519 }; 520 521 fch_dmac: dma-controller@4190000 { 522 compatible = "arm,dma-350"; 523 reg = <0x0 0x4190000 0x0 0x10000>; 524 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>, 525 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>, 526 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>, 527 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>, 528 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>, 529 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>, 530 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>, 531 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>; 532 #dma-cells = <1>; 533 }; 534 535 mbox_ap2se: mailbox@5060000 { 536 compatible = "cix,sky1-mbox"; 537 reg = <0x0 0x05060000 0x0 0x10000>; 538 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH 0>; 539 #mbox-cells = <1>; 540 cix,mbox-dir = "tx"; 541 }; 542 543 mbox_se2ap: mailbox@5070000 { 544 compatible = "cix,sky1-mbox"; 545 reg = <0x0 0x05070000 0x0 0x10000>; 546 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>; 547 #mbox-cells = <1>; 548 cix,mbox-dir = "rx"; 549 }; 550 551 ap2pm_scmi_mem: shmem@6590000 { 552 compatible = "arm,scmi-shmem"; 553 reg = <0x0 0x06590000 0x0 0x80>; 554 reg-io-width = <4>; 555 }; 556 557 mbox_ap2pm: mailbox@6590080 { 558 compatible = "cix,sky1-mbox"; 559 reg = <0x0 0x06590080 0x0 0xff80>; 560 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 561 #mbox-cells = <1>; 562 cix,mbox-dir = "tx"; 563 }; 564 565 pm2ap_scmi_mem: shmem@65a0000 { 566 compatible = "arm,scmi-shmem"; 567 reg = <0x0 0x065a0000 0x0 0x80>; 568 reg-io-width = <4>; 569 }; 570 571 mbox_pm2ap: mailbox@65a0080 { 572 compatible = "cix,sky1-mbox"; 573 reg = <0x0 0x065a0080 0x0 0xff80>; 574 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>; 575 #mbox-cells = <1>; 576 cix,mbox-dir = "rx"; 577 }; 578 579 audss_cru: clock-controller@7110000 { 580 compatible = "cix,sky1-audss-cru"; 581 reg = <0x0 0x07110000 0x0 0x10000>; 582 #clock-cells = <1>; 583 #reset-cells = <1>; 584 clocks = <&scmi_clk CLK_TREE_AUDIO_CLK0>, 585 <&scmi_clk CLK_TREE_AUDIO_CLK2>, 586 <&scmi_clk CLK_TREE_AUDIO_CLK4>, 587 <&scmi_clk CLK_TREE_AUDIO_CLK5>; 588 clock-names = "x8k", "x11k", "sys", "48m"; 589 power-domains = <&smc_devpd SKY1_PD_AUDIO>; 590 resets = <&s5_syscon SKY1_AUDIO_HIFI5_NOC_RESET_N>; 591 }; 592 593 mbox_sfh2ap: mailbox@8090000 { 594 compatible = "cix,sky1-mbox"; 595 reg = <0x0 0x08090000 0x0 0x10000>; 596 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; 597 #mbox-cells = <1>; 598 cix,mbox-dir = "rx"; 599 }; 600 601 mbox_ap2sfh: mailbox@80a0000 { 602 compatible = "cix,sky1-mbox"; 603 reg = <0x0 0x080a0000 0x0 0x10000>; 604 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; 605 #mbox-cells = <1>; 606 cix,mbox-dir = "tx"; 607 }; 608 609 pcie_x8_rc: pcie@a010000 { 610 compatible = "cix,sky1-pcie-host"; 611 reg = <0x00 0x0a010000 0x00 0x10000>, 612 <0x00 0x2c000000 0x00 0x4000000>, 613 <0x00 0x0a000300 0x00 0x100>, 614 <0x00 0x0a000400 0x00 0x100>, 615 <0x00 0x60000000 0x00 0x00100000>; 616 reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; 617 ranges = <0x01000000 0x0 0x60100000 0x0 0x60100000 0x0 0x00100000>, 618 <0x02000000 0x0 0x60200000 0x0 0x60200000 0x0 0x1fe00000>, 619 <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>; 620 #address-cells = <3>; 621 #size-cells = <2>; 622 bus-range = <0xc0 0xff>; 623 device_type = "pci"; 624 power-domains = <&smc_devpd SKY1_PD_PCIE_CTRL0>; 625 #interrupt-cells = <1>; 626 interrupt-map-mask = <0 0 0 0x7>; 627 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, 628 <0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, 629 <0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, 630 <0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>; 631 msi-map = <0xc000 &gic_its 0xc000 0x4000>; 632 status = "disabled"; 633 }; 634 635 pcie_x4_rc: pcie@a070000 { 636 compatible = "cix,sky1-pcie-host"; 637 reg = <0x00 0x0a070000 0x00 0x10000>, 638 <0x00 0x29000000 0x00 0x3000000>, 639 <0x00 0x0a060300 0x00 0x40>, 640 <0x00 0x0a060400 0x00 0x40>, 641 <0x00 0x50000000 0x00 0x00100000>; 642 reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; 643 ranges = <0x01000000 0x00 0x50100000 0x00 0x50100000 0x00 0x00100000>, 644 <0x02000000 0x00 0x50200000 0x00 0x50200000 0x00 0x0fe00000>, 645 <0x43000000 0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>; 646 #address-cells = <3>; 647 #size-cells = <2>; 648 bus-range = <0x90 0xbf>; 649 device_type = "pci"; 650 #interrupt-cells = <1>; 651 interrupt-map-mask = <0 0 0 0x7>; 652 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 0>, 653 <0 0 0 2 &gic 0 0 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, 654 <0 0 0 3 &gic 0 0 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, 655 <0 0 0 4 &gic 0 0 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 0>; 656 msi-map = <0x9000 &gic_its 0x9000 0x3000>; 657 status = "disabled"; 658 }; 659 660 pcie_x2_rc: pcie@a0c0000 { 661 compatible = "cix,sky1-pcie-host"; 662 reg = <0x00 0x0a0c0000 0x00 0x10000>, 663 <0x00 0x26000000 0x00 0x3000000>, 664 <0x00 0x0a0600340 0x00 0x20>, 665 <0x00 0x0a0600440 0x00 0x20>, 666 <0x00 0x40000000 0x00 0x00100000>; 667 reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; 668 ranges = <0x01000000 0x0 0x40100000 0x0 0x40100000 0x0 0x00100000>, 669 <0x02000000 0x0 0x40200000 0x0 0x40200000 0x0 0x0fe00000>, 670 <0x43000000 0x10 0x00000000 0x10 0x00000000 0x04 0x00000000>; 671 #address-cells = <3>; 672 #size-cells = <2>; 673 bus-range = <0x60 0x8f>; 674 device_type = "pci"; 675 #interrupt-cells = <1>; 676 interrupt-map-mask = <0 0 0 0x7>; 677 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 0>, 678 <0 0 0 2 &gic 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 0>, 679 <0 0 0 3 &gic 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 0>, 680 <0 0 0 4 &gic 0 0 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 0>; 681 msi-map = <0x6000 &gic_its 0x6000 0x3000>; 682 status = "disabled"; 683 }; 684 685 pcie_x1_0_rc: pcie@a0d0000 { 686 compatible = "cix,sky1-pcie-host"; 687 reg = <0x00 0x0a0d0000 0x00 0x10000>, 688 <0x00 0x20000000 0x00 0x3000000>, 689 <0x00 0x0a060360 0x00 0x20>, 690 <0x00 0x0a060460 0x00 0x20>, 691 <0x00 0x30000000 0x00 0x00100000>; 692 reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; 693 ranges = <0x01000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000>, 694 <0x02000000 0x0 0x30200000 0x0 0x30200000 0x0 0x07e00000>, 695 <0x43000000 0x08 0x00000000 0x08 0x00000000 0x04 0x00000000>; 696 #address-cells = <3>; 697 #size-cells = <2>; 698 bus-range = <0x00 0x2f>; 699 device_type = "pci"; 700 #interrupt-cells = <1>; 701 interrupt-map-mask = <0 0 0 0x7>; 702 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>, 703 <0 0 0 2 &gic 0 0 GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>, 704 <0 0 0 3 &gic 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, 705 <0 0 0 4 &gic 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; 706 msi-map = <0x0000 &gic_its 0x0000 0x3000>; 707 status = "disabled"; 708 }; 709 710 pcie_x1_1_rc: pcie@a0e0000 { 711 compatible = "cix,sky1-pcie-host"; 712 reg = <0x00 0x0a0e0000 0x00 0x10000>, 713 <0x00 0x23000000 0x00 0x3000000>, 714 <0x00 0x0a060380 0x00 0x20>, 715 <0x00 0x0a060480 0x00 0x20>, 716 <0x00 0x38000000 0x00 0x00100000>; 717 reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; 718 ranges = <0x01000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, 719 <0x02000000 0x0 0x38200000 0x0 0x38200000 0x0 0x07e00000>, 720 <0x43000000 0x0c 0x00000000 0x0c 0x00000000 0x04 0x00000000>; 721 #address-cells = <3>; 722 #size-cells = <2>; 723 bus-range = <0x30 0x5f>; 724 device_type = "pci"; 725 726 #interrupt-cells = <1>; 727 interrupt-map-mask = <0 0 0 0x7>; 728 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH 0>, 729 <0 0 0 2 &gic 0 0 GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH 0>, 730 <0 0 0 3 &gic 0 0 GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH 0>, 731 <0 0 0 4 &gic 0 0 GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH 0>; 732 msi-map = <0x3000 &gic_its 0x3000 0x3000>; 733 status = "disabled"; 734 }; 735 736 gic: interrupt-controller@e010000 { 737 compatible = "arm,gic-v3"; 738 reg = <0x0 0x0e010000 0 0x10000>, /* GICD */ 739 <0x0 0x0e090000 0 0x300000>; /* GICR * 12 */ 740 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>; 741 #interrupt-cells = <4>; 742 interrupt-controller; 743 #address-cells = <2>; 744 #size-cells = <2>; 745 ranges; 746 747 gic_its: msi-controller@e050000 { 748 compatible = "arm,gic-v3-its"; 749 reg = <0x0 0x0e050000 0x0 0x30000>; 750 msi-controller; 751 #msi-cells = <1>; 752 }; 753 754 ppi-partitions { 755 ppi_partition0: interrupt-partition-0 { 756 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 757 }; 758 759 ppi_partition1: interrupt-partition-1 { 760 affinity = <&cpu4 &cpu5 &cpu6 &cpu7 &cpu8 &cpu9 &cpu10 &cpu11>; 761 }; 762 }; 763 }; 764 765 s5_syscon: syscon@16000000 { 766 compatible = "cix,sky1-s5-system-control", "syscon"; 767 reg = <0x0 0x16000000 0x0 0x1000>; 768 #reset-cells = <1>; 769 }; 770 771 s5_gpio0: gpio-controller@16004000 { 772 compatible = "cdns,gpio-r1p02"; 773 reg = <0x0 0x16004000 0x0 0x1000>; 774 clocks = <&s5_gpio_apb_clk>; 775 776 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH 0>; 777 778 gpio-controller; 779 #gpio-cells = <2>; 780 ngpios = <32>; 781 782 interrupt-controller; 783 #interrupt-cells = <2>; 784 status = "disabled"; 785 }; 786 787 s5_gpio1: gpio-controller@16005000 { 788 compatible = "cdns,gpio-r1p02"; 789 reg = <0x0 0x16005000 0x0 0x1000>; 790 clocks = <&s5_gpio_apb_clk>; 791 792 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; 793 794 gpio-controller; 795 #gpio-cells = <2>; 796 ngpios = <10>; 797 798 interrupt-controller; 799 #interrupt-cells = <2>; 800 status = "disabled"; 801 }; 802 803 s5_gpio2: gpio-controller@16006000 { 804 compatible = "cdns,gpio-r1p02"; 805 reg = <0x0 0x16006000 0x0 0x1000>; 806 clocks = <&s5_gpio_apb_clk>; 807 808 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>; 809 810 gpio-controller; 811 #gpio-cells = <2>; 812 ngpios = <10>; 813 814 interrupt-controller; 815 #interrupt-cells = <2>; 816 status = "disabled"; 817 }; 818 819 iomuxc_s5: pinctrl@16007000 { 820 compatible = "cix,sky1-pinctrl-s5"; 821 reg = <0x0 0x16007000 0x0 0x1000>; 822 }; 823 824 ap_tfa_scmi_mem: shmem@84380000 { 825 compatible = "arm,scmi-shmem"; 826 reg = <0x0 0x84380000 0x0 0x80>; 827 reg-io-width = <4>; 828 }; 829 }; 830 831 timer { 832 compatible = "arm,armv8-timer"; 833 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 834 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 835 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 836 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 837 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>, 838 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>; 839 }; 840}; 841