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/linux/tools/perf/pmu-events/arch/x86/arrowlake/
H A D	virtual-memory.json	3 …"BriefDescription": "Counts the number of page walks initiated by a demand load that missed the fi… 4 "Counter": "0,1,2,3,4,5,6,7", 13 "Counter": "0,1,2,3,4,5,6,7", 21 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page… 22 "Counter": "0,1,2,3,4,5,6,7", 31 "Counter": "0,1,2,3,4,5,6,7,8,9", 40 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page… 41 "Counter": "0,1,2,3,4,5,6,7", 49 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", 50 "Counter": "0,1,2,3,4,5,6,7,8,9", [all …]
H A D	frontend.json	4 "Counter": "0,1,2,3,4,5,6,7", 7 "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", 14 "Counter": "0,1,2,3,4,5,6,7,8,9", 17 "PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", 24 "Counter": "0,1,2,3,4,5,6,7", 27 "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", 33 "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.", 34 "Counter": "0,1,2,3,4, 41 { global() object [all...]
H A D	other.json	3 …re not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and… 4 "Counter": "0,1,2,3,4,5,6,7,8,9", 7 …re not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and… 14 "Counter": "0,1,2,3,4,5,6,7,8,9", 22 …"BriefDescription": "Counts the number of unhalted cycles a Core is blocked due to a lock In Progr… 23 "Counter": "0,1,2,3,4,5,6,7", 26 …Counts the number of unhalted cycles a Core is blocked due to a lock In Progress issued by another… 32 …"BriefDescription": "Counts the number of unhalted cycles a Core is blocked due to an Accepted loc… 33 "Counter": "0,1,2,3,4,5,6,7", 36 …r of unhalted cycles a Core is blocked due to an Accepted lock it issued, includes both split and … [all …]
/linux/tools/perf/pmu-events/arch/x86/lunarlake/
H A D	virtual-memory.json	3 …"BriefDescription": "Counts the number of page walks initiated by a demand load that missed the fi… 4 "Counter": "0,1,2,3,4,5,6,7", 13 "Counter": "0,1,2,3,4,5,6,7", 21 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page… 22 "Counter": "0,1,2,3,4,5,6,7", 31 "Counter": "0,1,2,3,4,5,6,7,8,9", 40 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", 41 "Counter": "0,1,2,3,4,5,6,7,8,9", 45 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.… 52 "Counter": "0,1,2,3,4,5,6,7", [all …]
H A D	frontend.json	4 "Counter": "0,1,2,3,4,5,6,7", 7 "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", 14 "Counter": "0,1,2,3,4,5,6,7,8,9", 17 "PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", 23 "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.", 24 "Counter": "0,1,2,3,4,5,6,7", 33 "Counter": "0,1,2,3,4,5,6,7", 41 "BriefDescription": "Counts the number of BACLEARS due to a retur 40 { global() object [all...]
/linux/drivers/ata/pata_parport/
H A D	kbic.c	5 * This is a low-level driver for the KBIC-951A and KBIC-971A 9 * required for the 971A interferes with the correct operation of 10 * the 951A, so this driver registers itself twice, once for 25 #define j44(a, b) ((((a >> 4) & 0x0f) \| (b & 0xf0)) ^ 0x88) argument 26 #define j53(w) (((w >> 3) & 0x1f) \| ((w >> 4) & 0xe0)) 37 int a, b, s; in kbic_read_regr() local 43 w0(regr \| 0x18 \| s); w2(4); w2(6); w2(4); w2(1); w0(8); in kbic_read_regr() 44 a = r1(); w0(0x28); b = r1(); w2(4); in kbic_read_regr() 45 return j44(a, b); in kbic_read_regr() 47 w0(regr\|0x38 \| s); w2(4); w2(6); w2(4); w2(5); w0(8); in kbic_read_regr() [all …]
H A D	epat.c	20 #define j44(a, b) (((a >> 4) & 0x0f) + (b & 0xf0)) argument 21 #define j53(a, b) (((a >> 3) & 0x1f) + ((b << 4) & 0xe0)) argument 45 w0(0x60+r); w2(1); w0(val); w2(4); in epat_write_regr() 48 case 4: in epat_write_regr() 57 int a, b, r; in epat_read_regr() local 65 a = r1(); w2(4); b = r1(); in epat_read_regr() 66 return j44(a, b); in epat_read_regr() 68 w0(0x40+r); w2(1); w2(4); in epat_read_regr() 69 a = r1(); b = r2(); w0(0xff); in epat_read_regr() 70 return j53(a, b); in epat_read_regr() [all …]
/linux/tools/perf/pmu-events/arch/x86/pantherlake/
H A D	virtual-memory.json	3 "BriefDescription": "Counts the number of page walks initiated by a demand load that missed the first and second level TLBs.", 4 "Counter": "0,1,2,3,4,5,6,7", 12 "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.", 13 "Counter": "0,1,2,3,4,5,6,7", 22 "Counter": "0,1,2,3,4,5,6,7,8,9", 31 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", 32 "Counter": "0,1,2,3,4, 41 { global() object [all...]
H A D	frontend.json	4 "Counter": "0,1,2,3,4,5,6,7", 7 "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", 14 "Counter": "0,1,2,3,4,5,6,7,8,9", 17 "PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", 23 "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.", 24 "Counter": "0,1,2,3,4,5,6,7", 33 "Counter": "0,1,2,3,4,5,6,7", 41 "BriefDescription": "Counts the number of BACLEARS due to a retur 40 { global() object [all...]
/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A D	virtual-memory.json	3 "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.", 4 "Counter": "0,1,2,3,4,5,6,7", 22 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", 27 "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.", 34 "Counter": "0,1,2,3,4,5,6,7", 42 "BriefDescription": "Load miss in all TLB levels causes a pag 41 { global() object [all...]
H A D	frontend.json	4 "Counter": "0,1,2,3,4,5,6,7", 7 "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", 17 "PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", 27 "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", 46 "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transitio 41 { global() object [all...]
/linux/Documentation/userspace-api/media/v4l/
H A D	pixfmt-rgb.rst	10 These formats encode each pixel as a triplet of RGB values. They are packed 13 bits required to store a pixel is not aligned to a byte boundary, the data is 21 or a permutation thereof, collectively referred to as alpha formats) depend on 25 a meaningful value. Otherwise, when the device doesn't capture an alpha channel 26 but can set the alpha bit to a user-configurable value, the 29 the value specified by that control. Otherwise a corresponding format without 35 filled with meaningful values by applications. Otherwise a corresponding format 39 Formats that contain padding bits are named XRGB (or a permutation thereof). 45 - In all the tables that follow, bit 7 is the most significant bit in a byte. 47 respectively. 'a' denotes bits of the alpha component (if supported by the [all …]
/linux/arch/x86/crypto/
H A D	twofish-i586-asm_32.S	`17 #define ctx 4 /* Twofish context structure / 20 #define b_offset 4 33 / define a few register aliases to allow macro substitution / 61 a input register containing a (rotated 16) 65 * operations on a and b are interleaved to increase performance 67 #define encrypt_round(a,b,c,d,round)\ argument 70 mov s1(%ebp,%edi,4),d ## D;\ 71 movzx a ## B, %edi;\ 72 mov s2(%ebp,%edi,4),%esi;\ 75 xor s2(%ebp,%edi,4),d ## D;\ [all …]`
/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A D	virtual-memory.json	3 "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.", 4 "Counter": "0,1,2,3,4,5,6,7", 12 "Counter": "0,1,2,3,4,5,6,7", 19 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.", 20 "Counter": "0,1,2,3,4,5,6,7", 23 "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.", 28 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 36 { global() object [all...]
H A D	cache.json	4 "Counter": "0,1,2,3,4,5,6,7", 7 "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.) Counts on a per core basis.", 12 "Counter": "0,1,2,3,4,5,6,7", 15 "PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches. Does not count evictions or dirty writebacks caused by snoops. Does not count a replacement unless a (dirty) line was written back.", 21 "Counter": "0,1,2,3,4, 38 { global() object [all...]
/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A D	virtual-memory.json	3 "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.", 4 "Counter": "0,1,2,3,4,5,6,7", 12 "Counter": "0,1,2,3,4,5,6,7", 19 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.", 20 "Counter": "0,1,2,3,4,5,6,7", 23 "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.", 28 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 36 { global() object [all...]
/linux/drivers/net/ethernet/sfc/
H A D	mcdi_pcol.h	19 #define MC_FW_STATE_BOOTING (4) 24 * Unlike a warm boot, assume DMEM has been reloaded, so that 51 /* Check whether an mcfw version (in host order) belongs to a bootloader / 65 Each MCDI request starts with an MCDI_HEADER, which is a 32bit 87 * The protocol requires one response to be delivered for every request; a 102 #define MCDI_HEADER_SEQ_WIDTH 4 126 * - To advance a shared memory request if XFLAGS_EVREQ was set 127 * - As a notification (link state, i2c event), controlled 130 * Both events share a common structure: 148 * Events can be squirted out of the UART (using LOG_CTRL) without a [all …]
/linux/lib/crypto/x86/
H A D	sha256-avx2-asm.S	`11 # This software is available to you under a choice of one of two 32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 48 # This code schedules 2 blocks at a time, with 4 lanes per block 102 a = %eax define 115 _XFER_SIZE = 2644 # 2 blocks, 64 rounds, 4 bytes/round 139 # Rotate values of symbols a...h 149 b = a 150 a = TMP_ define 156 mov a, y3 # y3 = a # MAJA 161 or c, y3 # y3 = a\|c # MAJA [all …]`
/linux/tools/perf/pmu-events/arch/x86/skylake/
H A D	virtual-memory.json	7 …PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1… 21 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa… 26 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.", 31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 35 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 40 "BriefDescription": "Page walk completed due to a demand data load to a 1G page", 44 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 49 "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page", 53 …4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and fu… 58 "BriefDescription": "Page walk completed due to a demand data load to a 4K page", [all …]
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A D	virtual-memory.json	7 …PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1… 21 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa… 26 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.", 31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 35 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 40 "BriefDescription": "Page walk completed due to a demand data load to a 1G page", 44 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 49 "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page", 53 …4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and fu… 58 "BriefDescription": "Page walk completed due to a demand data load to a 4K page", [all …]
/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A D	virtual-memory.json	7 …PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1… 21 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa… 26 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.", 31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 35 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 40 "BriefDescription": "Page walk completed due to a demand data load to a 1G page", 44 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 49 "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page", 53 …4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and fu… 58 "BriefDescription": "Page walk completed due to a demand data load to a 4K page", [all …]
/linux/tools/perf/pmu-events/arch/x86/alderlake/
H A D	virtual-memory.json	13 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", 18 "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.", 25 "Counter": "0,1,2,3,4,5", 34 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", 38 "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 44 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.", 48 "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a faul 43 { global() object [all...]
/linux/drivers/net/ethernet/sfc/siena/
H A D	mcdi_pcol.h	19 #define MC_FW_STATE_BOOTING (4) 24 * Unlike a warm boot, assume DMEM has been reloaded, so that 51 /* Check whether an mcfw version (in host order) belongs to a bootloader / 65 Each MCDI request starts with an MCDI_HEADER, which is a 32bit 87 * The protocol requires one response to be delivered for every request, a 102 #define MCDI_HEADER_SEQ_WIDTH 4 126 * - To advance a shared memory request if XFLAGS_EVREQ was set 127 * - As a notification (link state, i2c event), controlled 130 * Both events share a common structure: 148 * Events can be squirted out of the UART (using LOG_CTRL) without a [all …]
/linux/tools/perf/pmu-events/arch/x86/alderlaken/
H A D	cache.json	3 "BriefDescription": "Counts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a full condition.", 4 "Counter": "0,1,2,3,4,5", 7 "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the External Queue (XQ), but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event). Counts on a per core basis.", 11 "BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition.", 12 "Counter": "0,1,2,3,4,5", 15 "PublicDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a ful 37 { global() object [all...]
/linux/include/drm/
H A D	drm_fourcc.h	30 * DRM_FORMAT_MAX_PLANES - maximum number of planes a DRM format can have 32 #define DRM_FORMAT_MAX_PLANES 4u 59 * struct drm_format_info - information about a DRM format 62 /** @format: 4CC format identifier (DRM_FORMAT_) / 69 * valid for a subset of RGB formats only. This is a legacy field, do 92 * defined as a rectangle of pixels which are stored next to 93 * each other in a byte aligned memory region. Together with 96 * formats for which the memory needed for a single pixel is not 100 * a lot of places in drivers where it's used. In drm core for 139 /** @is_yuv: Is it a YUV format? */ [all …]

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