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/linux/drivers/gpu/drm/i915/display/
H A Dvlv_dpio_phy_regs.h1 /* SPDX-License-Identifier: MIT */
11 #define _VLV_CMN(dw) (0x8100 + (dw) * 4)
12 #define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4)
13 #define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */ argument
14 #define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4) argument
15 #define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */
16 #define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + (dw) * 4) argument
17 #define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4) argument
18 #define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4)
19 #define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4) argument
[all …]
/linux/sound/soc/codecs/
H A Drk3308_codec.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Rockchip RK3308 internal audio codec driver -- register definitions
6 * Copyright (c) 2022, Vivax-Metrotech Ltd
24 #define RK3308_ADC_DIG_OFFSET(ch) (((ch) & 0x3) * 0xc0 + 0x0) argument
26 #define RK3308_ADC_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x04) argument
27 #define RK3308_ADC_DIG_CON02(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x08) argument
28 #define RK3308_ADC_DIG_CON03(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x0c) argument
29 #define RK3308_ADC_DIG_CON04(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x10) argument
30 #define RK3308_ADC_DIG_CON05(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x14) // ver.C only argument
31 #define RK3308_ADC_DIG_CON06(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x18) // ver.C only argument
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/linux/drivers/gpu/drm/imx/dcss/
H A Ddcss-dpr.c1 // SPDX-License-Identifier: GPL-2.0
9 #include "dcss-dev.h"
16 #define SW_SHADOW_LOAD_SEL BIT(4)
25 #define DPR2RTR_YRGB_FIFO_OVFL BIT(4)
33 #define TILE_TYPE_MASK GENMASK(4, 2)
53 #define ROT_FLIP_ORDER_EN BIT(4)
73 #define THRES_LOW_POS 4
74 #define THRES_LOW_MASK GENMASK(6, 4)
118 struct dcss_dpr_ch ch[3]; member
121 static void dcss_dpr_write(struct dcss_dpr_ch *ch, u32 val, u32 ofs) in dcss_dpr_write() argument
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/linux/drivers/clk/berlin/
H A Dberlin2-avpll.c1 // SPDX-License-Identifier: GPL-2.0
6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 #include <linux/clk-provider.h>
15 #include "berlin2-avpll.h"
19 * VCO with 8 channels each, channel 8 is the odd-one-out and does
34 /* BG2/BG2CDs VCO_B has an additional shift of 4 for its VCO_CTRL0 reg */
67 #define VCO_SPEED_1G86_2G00 VCO_SPEED(4)
118 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled()
119 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_is_enabled()
120 reg >>= 4; in berlin2_avpll_vco_is_enabled()
[all …]
/linux/drivers/clocksource/
H A Dsh_mtu2.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - MTU2
55 #define TSTR -1 /* shared register */
60 #define TSR 4 /* channel register */
75 /* Values 4 to 7 are channel-dependent */
80 #define TCR_TPSC_CH0_TCLKA (4 << 0)
84 #define TCR_TPSC_CH1_TCLKA (4 << 0)
88 #define TCR_TPSC_CH2_TCLKA (4 << 0)
92 #define TCR_TPSC_CH34_P256 (4 << 0)
100 #define TMDR_BFA (1 << 4)
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H A Dsh_tmu.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - TMU
70 #define TSTR -1 /* shared register */
81 #define TCR_TPSC_CLK1024 (4 << 0)
84 static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr) in sh_tmu_read() argument
89 switch (ch->tmu->model) { in sh_tmu_read()
91 return ioread8(ch->tmu->mapbase + 2); in sh_tmu_read()
93 return ioread8(ch->tmu->mapbase + 4); in sh_tmu_read()
100 return ioread16(ch->base + offs); in sh_tmu_read()
102 return ioread32(ch->base + offs); in sh_tmu_read()
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H A Dsh_cmt.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - CMT
39 * 16B 32B 32B-F 48B R-Car Gen2
40 * -----------------------------------------------------------------------------
41 * Channels 2 1/4 1 6 2/8
46 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
50 * Channels are indexed from 0 to N-1 in the documentation. The channel index
55 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
59 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
60 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
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/linux/drivers/staging/most/dim2/
H A Dhal.c1 // SPDX-License-Identifier: GPL-2.0
3 * hal.c - DIM2 HAL implementation
6 * Copyright (C) 2015-2016, Microchip Technology Germany II GmbH & Co. KG
25 * Number of 32-bit units for DBR map.
29 * 4: block size is 128, max allocation is 4K
37 /* -------------------------------------------------------------------------- */
50 /* -------------------------------------------------------------------------- */
64 /* -------------------------------------------------------------------------- */
86 /* -------------------------------------------------------------------------- */
99 * alloc_dbr() - Allocates DBR memory.
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/linux/drivers/gpu/ipu-v3/
H A Dipu-prv.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
17 #include <video/imx-ipu-v3.h>
53 #define IPU_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0150 + 4 * ((ch) / 32)) argument
54 #define IPU_ALT_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0168 + 4 * ((ch) / 32)) argument
55 #define IPU_CHA_CUR_BUF(ch) IPU_CM_REG(0x023C + 4 * ((ch) / 32)) argument
61 #define IPU_CHA_BUF0_RDY(ch) IPU_CM_REG(0x0268 + 4 * ((ch) / 32)) argument
62 #define IPU_CHA_BUF1_RDY(ch) IPU_CM_REG(0x0270 + 4 * ((ch) / 32)) argument
63 #define IPU_CHA_BUF2_RDY(ch) IPU_CM_REG(0x0288 + 4 * ((ch) / 32)) argument
64 #define IPU_ALT_CHA_BUF0_RDY(ch) IPU_CM_REG(0x0278 + 4 * ((ch) / 32)) argument
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H A Dipu-cpmem.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
11 #include "ipu-prv.h"
34 #define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4)
74 #define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4)
93 ipu_get_cpmem(struct ipuv3_channel *ch) in ipu_get_cpmem() argument
95 struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv; in ipu_get_cpmem()
97 return cpmem->base + ch->num; in ipu_get_cpmem()
100 static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v) in ipu_ch_param_write_field() argument
102 struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch); in ipu_ch_param_write_field()
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/linux/lib/
H A Dhexdump.c1 // SPDX-License-Identifier: GPL-2.0-only
20 * hex_to_bin - convert a hex digit to its real value
21 * @ch: ascii character represents hex digit
23 * hex_to_bin() converts one hex digit to its actual value or -1 in case of bad
30 * (ch - '9' - 1) is negative if ch <= '9'
31 * ('0' - 1 - ch) is negative if ch >= '0'
32 * we "and" these two values, so the result is negative if ch is in the range
35 * shift of a negative value is implementation-defined, so we cast the
36 * value to (unsigned) before the shift --- we have 0xffffff if ch is in
38 * we "and" this value with (ch - '0' + 1) --- we have a value 1 ... 10 if ch is
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/linux/arch/x86/crypto/
H A Dsha256-avx2-asm.S2 # Implement fast SHA-256 with AVX2 instructions. (x86_64)
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
41 # This code is described in an Intel White-Paper:
42 # "Fast SHA-256 Implementations on Intel Architecture Processors"
48 # This code schedules 2 blocks at a time, with 4 lanes per block
60 # Add reg to mem using reg-mem add and store
87 SHUF_00BA = %ymm10 # shuffle xBxA -> 00BA
88 SHUF_DC00 = %ymm12 # shuffle xDxC -> DC00
116 _XFER_SIZE = 2*64*4 # 2 blocks, 64 rounds, 4 bytes/round
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H A Dsha256-avx-asm.S2 # Implement fast SHA-256 with AVX1 instructions. (x86_64)
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
40 # This code is described in an Intel White-Paper:
41 # "Fast SHA-256 Implementations on Intel Architecture Processors"
47 # This code schedules 1 block at a time, with 4 lanes per block
59 # Add reg to mem using reg-mem add and store
67 shld $(32-(\p1)), \p2, \p2
94 SHUF_00BA = %xmm10 # shuffle xBxA -> 00BA
95 SHUF_DC00 = %xmm12 # shuffle xDxC -> DC00
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H A Dsha256-ssse3-asm.S2 # Implement fast SHA-256 with SSSE3 instructions. (x86_64)
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
41 # This code is described in an Intel White-Paper:
42 # "Fast SHA-256 Implementations on Intel Architecture Processors"
58 # Add reg to mem using reg-mem add and store
87 SHUF_00BA = %xmm10 # shuffle xBxA -> 00BA
88 SHUF_DC00 = %xmm11 # shuffle xDxC -> DC00
150 ## compute W[-16] + W[-7] 4 at a time
153 ror $(25-11), y0 # y0 = e >> (25-11)
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/linux/drivers/media/pci/cx25821/
H A Dcx25821-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include "cx25821-sram.h"
16 #include "cx25821-video.h"
19 MODULE_AUTHOR("Shu Lin - Hiep Huynh");
26 static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET };
320 [RISC_WRITECR >> 28] = 4, in cx25821_risc_decode()
332 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) { in cx25821_risc_decode()
356 /* PLL-A setting for the Audio Master Clock */ in cx25821_registers_init()
366 /* PLL-B setting for Mobilygen Host Bus Interface */ in cx25821_registers_init()
376 /* PLL-C setting for video upstream channel */ in cx25821_registers_init()
[all …]
/linux/include/linux/mfd/
H A Drz-mtu3.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 /* 8-bit shared register offsets macros */
16 /* 16-bit shared register offset macros */
31 /* 8-bit register offset macros of MTU3 channels except MTU5 */
36 #define RZ_MTU3_TCR2 4 /* Timer control register 2 */
47 /* Only MTU3/4/6/7 have TBTM registers */
50 /* 8-bit MTU5 register offset macros */
53 #define RZ_MTU3_TCRU 4 /* Timer control register U */
63 /* 16-bit register offset macros of MTU3 channels except MTU5 */
68 #define RZ_MTU3_TGRD 4 /* Timer general register D */
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/linux/drivers/scsi/
H A Dch.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * (c) 1996-2003 Gerd Knorr <kraxel@bytesex.org>
71 static int dt_id[CH_DT_MAX] = { [ 0 ... (CH_DT_MAX-1) ] = -1 };
76 /* tell the driver about vendor-specific slots */
77 static int vendor_firsts[CH_TYPES-4];
78 static int vendor_counts[CH_TYPES-4];
82 static const char * vendor_labels[CH_TYPES-4] = {
87 #define ch_printk(prefix, ch, fmt, a...) \ argument
88 sdev_prefix_printk(prefix, (ch)->device, (ch)->name, fmt, ##a)
93 ch_printk(KERN_DEBUG, ch, fmt, ##arg); \
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/linux/drivers/clk/uniphier/
H A Dclk-uniphier-peri.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include "clk-uniphier.h"
9 #define UNIPHIER_PERI_CLK_UART(idx, ch) \ argument
10 UNIPHIER_CLK_GATE("uart" #ch, (idx), "uart", 0x24, 19 + (ch))
13 UNIPHIER_CLK_GATE("i2c-common", -1, "i2c", 0x20, 1)
15 #define UNIPHIER_PERI_CLK_I2C(idx, ch) \ argument
16 UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c-common", 0x24, 5 + (ch))
18 #define UNIPHIER_PERI_CLK_FI2C(idx, ch) \ argument
19 UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c", 0x24, 24 + (ch))
21 #define UNIPHIER_PERI_CLK_SCSSI(idx, ch) \ argument
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/linux/drivers/media/pci/solo6x10/
H A Dsolo6x10-regs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2010-2013 Bluecherry, LLC <https://www.bluecherrydvr.com>
17 #include "solo6x10-offsets.h"
38 #define SOLO_DMA_CTRL_STROBE_SELECT BIT(4)
48 /* 0=sys_clk/4, 1=sys_clk/2, 2=clk_in/2 of system input */
55 #define SOLO_VCLK_VIN0405_DELAY(n) ((n)<<4)
73 #define SOLO_IRQ_UART(n) BIT((n) + 4)
107 #define SOLO_P2M_CSC_BYTE_REORDER BIT(5) /* BGR -> RGB */
108 /* 0:r=[14:10] g=[9:5] b=[4:0], 1:r=[15:11] g=[10:5] b=[4:0] */
109 #define SOLO_P2M_CSC_16BIT_565 BIT(4)
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H A Dsolo6x10-tw28.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010-2013 Bluecherry, LLC <https://www.bluecherrydvr.com>
16 #include "solo6x10-tw28.h"
18 #define DEFAULT_HDELAY_NTSC (32 - 8)
20 #define DEFAULT_VDELAY_NTSC (7 - 2)
21 #define DEFAULT_VACTIVE_NTSC (240 + 4)
23 #define DEFAULT_HDELAY_PAL (32 + 4)
24 #define DEFAULT_HACTIVE_PAL (864-DEFAULT_HDELAY_PAL)
26 #define DEFAULT_VACTIVE_PAL (312-DEFAULT_VDELAY_PAL)
169 #define is_tw286x(__solo, __id) (!(__solo->tw2815 & (1 << __id)))
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/linux/arch/mips/lantiq/xway/
H A Ddma.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
45 #define DMA_PCTRL_4W_BURST 0x2 /* 4 word burst length */
47 #define DMA_TX_BURST_SHIFT 4 /* tx burst shift */
61 ltq_dma_enable_irq(struct ltq_dma_channel *ch) in ltq_dma_enable_irq() argument
66 ltq_dma_w32(ch->nr, LTQ_DMA_CS); in ltq_dma_enable_irq()
67 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); in ltq_dma_enable_irq()
73 ltq_dma_disable_irq(struct ltq_dma_channel *ch) in ltq_dma_disable_irq() argument
78 ltq_dma_w32(ch->nr, LTQ_DMA_CS); in ltq_dma_disable_irq()
79 ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN); in ltq_dma_disable_irq()
[all …]
/linux/drivers/gpu/drm/tidss/
H A Dtidss_irq.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
18 * bit group |dev|wb |mrg0|mrg1|mrg2|mrg3|plane0-3| <unused> |
20 * bit number|0 |1-3|4-7 |8-11| 12-19 | 20-23 | 24-31 |
34 #define DSS_IRQ_VP_BIT_N(ch, bit) (4 + 4 * (ch) + (bit)) argument
38 #define DSS_IRQ_VP_BIT(ch, bit) BIT(DSS_IRQ_VP_BIT_N((ch), (bit))) argument
42 static inline dispc_irq_t DSS_IRQ_VP_MASK(u32 ch) in DSS_IRQ_VP_MASK() argument
44 return GENMASK(DSS_IRQ_VP_BIT_N((ch), 3), DSS_IRQ_VP_BIT_N((ch), 0)); in DSS_IRQ_VP_MASK()
53 #define DSS_IRQ_VP_FRAME_DONE(ch) DSS_IRQ_VP_BIT((ch), 0) argument
54 #define DSS_IRQ_VP_VSYNC_EVEN(ch) DSS_IRQ_VP_BIT((ch), 1) argument
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/linux/arch/arm64/boot/dts/renesas/
H A Dulcb-kf-audio-graph-card2-mix+split.dtsi1 // SPDX-License-Identifier: GPL-2.0
12 * (A) CPU0 (2ch) <----> (2ch) (X) ak4613 (MIX-0)
13 * (B) CPU1 (2ch) --/ (MIX-1)
14 * (C) CPU3 (2ch) ----> (8ch) (Y) PCM3168A-p (TDM-0 : 0,1ch)
15 * (D) CPU2 (2ch) --/ (TDM-1 : 2,3ch)
16 * (E) CPU4 (2ch) --/ (TDM-2 : 4,5ch)
17 * (F) CPU5 (2ch) --/ (TDM-3 : 6,7ch)
18 * (G) CPU6 (6ch) <---- (6ch) (Z) PCM3168A-c
20 * (A) aplay -D plughw:0,0 xxx.wav (MIX-0)
21 * (B) aplay -D plughw:0,1 xxx.wav (MIX-1)
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/linux/sound/soc/fsl/
H A Dfsl_micfil.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
38 /* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
53 #define MICFIL_CTRL1_CHEN(ch) BIT(ch) argument
55 /* MICFIL Control Register 2 -
72 MICFIL_STAT_CHXF(ch) global() argument
78 MICFIL_FIFO_STAT_FIFOX_OVER(ch) global() argument
79 MICFIL_FIFO_STAT_FIFOX_UNDER(ch) global() argument
83 MICFIL_DC_CHX_SHIFT(ch) global() argument
84 MICFIL_DC_CHX(ch) global() argument
[all...]
/linux/drivers/gpio/
H A Dgpio-ml-ioh.c1 // SPDX-License-Identifier: GPL-2.0-only
40 u32 ioh_sel_reg[4];
46 * struct ioh_gpio_reg_data - The register store data.
66 * struct ioh_gpio - GPIO private data structure.
73 * @gpio_use_sel: Save GPIO_USE_SEL1~4 register for PM
74 * @ch: Indicate GPIO channel
85 int ch; member
98 spin_lock_irqsave(&chip->spinlock, flags); in ioh_gpio_set()
99 reg_val = ioread32(&chip->reg->regs[chip->ch].po); in ioh_gpio_set()
105 iowrite32(reg_val, &chip->reg->regs[chip->ch].po); in ioh_gpio_set()
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