Home
last modified time | relevance | path

Searched +full:24 +full:khz (Results 1 – 25 of 450) sorted by relevance

12345678910>>...18

/linux/Documentation/fb/
H A Dviafb.modes14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
39 # Scan Frequency 37.500 kHz 75.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
60 # Scan Frequency 43.269 kHz 85.00 Hz
70 # 24 chars 29 lines
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
81 # Scan Frequency 50.900 kHz 100.00 Hz
[all …]
/linux/Documentation/sound/cards/
H A Daudiophile-usb.rst47 * sample depth of 16 or 24 bits
48 * sample rate from 8kHz to 96kHz
57 * 16-bit/48kHz ==> 4 channels in + 4 channels out
61 * 24-bit/48kHz ==> 4 channels in + 2 channels out,
66 * 24-bit/96kHz ==> 2 channels in _or_ 2 channels out (half duplex only)
113 24bit-depth-mode and immediately after wants to switch to a 16bit-depth mode,
133 24-bits depth mode.
197 - 16bits 48kHz mode with Di disabled
204 - 16bits 48kHz mode with Di enabled
227 24-bit modes
[all …]
/linux/sound/pci/ca0106/
H A Dca0106.h4 * Driver CA0106 chips. e.g. Sound Blaster Audigy LS and Live 24bit
48 * Added GPIO info for SB Live 24bit.
50 * Implement support for Line-in capture on SB Live 24bit.
52 * Add support for mute control on SB Live 24bit (cards w/ SPI DAC)
139 /* SB Live 24bit:
144 * bit 12 0 = 48 Khz / 1 = 96 Khz Analog out on SB Live 24bit.
148 * Both bit 9 and bit 14 have to be set for analog sound to work on the SB Live 24bit.
203 * Playback rate [23:16] (2 bits per channel) (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
204 * Playback mixer in enable [27:24] (one bit per channel)
232 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
[all …]
/linux/Documentation/arch/arm/sunxi/
H A Dclocks.rst8 Q: Why is the main 24MHz oscillator gateable? Wouldn't that break the
11 A: The 24MHz oscillator allows gating to save power. Indeed, if gated
18 24MHz 32kHz
26 When you are about to suspend, you switch the CPU Mux to the 32kHz
29 24Mhz 32kHz
39 32kHz
/linux/sound/firewire/dice/
H A Ddice-weiss.c13 // Weiss DAC202: 192kHz 2-channel DAC
19 // Weiss MAN301: 192kHz 2-channel music archive network player
25 // Weiss INT202: 192kHz unidirectional 2-channel digital Firewire nterface
31 // Weiss INT203: 192kHz bidirectional 2-channel digital Firewire nterface
37 // Weiss ADC2: 192kHz A/D converter with microphone preamps and line nputs
43 // Weiss DAC2/Minerva: 192kHz 2-channel DAC
49 // Weiss Vesta: 192kHz 2-channel Firewire to AES/EBU interface
55 // Weiss AFI1: 192kHz 24-channel Firewire to ADAT or AES/EBU interface
57 .tx_pcm_chs = {{24, 16, 8}, {0, 0, 0} },
58 .rx_pcm_chs = {{24, 16, 8}, {0, 0, 0} },
H A Ddice.c280 /* TC Electronic Konnekt 24D. */
395 // Weiss DAC202: 192kHz 2-channel DAC
402 // Weiss DAC202: 192kHz 2-channel DAC (Maya edition)
409 // Weiss MAN301: 192kHz 2-channel music archive network player
416 // Weiss INT202: 192kHz unidirectional 2-channel digital Firewire face
423 // Weiss INT203: 192kHz bidirectional 2-channel digital Firewire face
430 // Weiss ADC2: 192kHz A/D converter with microphone preamps and inputs
437 // Weiss DAC2/Minerva: 192kHz 2-channel DAC
444 // Weiss Vesta: 192kHz 2-channel Firewire to AES/EBU interface
451 // Weiss AFI1: 192kHz 2
[all...]
/linux/sound/ppc/
H A Dawacs.h45 #define MASK_NEWECMD (0x1 << 24) /* Lock: don't write to reg when 1 */
112 #define SAMPLERATE_48000 (0x0 << 3) /* 48 or 44.1 kHz */
113 #define SAMPLERATE_32000 (0x1 << 3) /* 32 or 29.4 kHz */
114 #define SAMPLERATE_24000 (0x2 << 3) /* 24 or 22.05 kHz */
115 #define SAMPLERATE_19200 (0x3 << 3) /* 19.2 or 17.64 kHz */
116 #define SAMPLERATE_16000 (0x4 << 3) /* 16 or 14.7 kHz */
117 #define SAMPLERATE_12000 (0x5 << 3) /* 12 or 11.025 kHz */
118 #define SAMPLERATE_9600 (0x6 << 3) /* 9.6 or 8.82 kHz */
119 #define SAMPLERATE_8000 (0x7 << 3) /* 8 or 7.35 kHz */
172 #define RATE_48000 (0x0 << 8) /* 48 kHz */
[all …]
/linux/drivers/media/dvb-frontends/
H A Dmxl5xx_defs.h80 MXL_HYDRA_DEMOD_SCRAMBLE_CODE_CMD = 24,
396 MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, /* 102.05 KHz for 24 MHz XTAL */
397 MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, /* 204.10 KHz for 24 MHz XTAL */
398 MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, /* 306.15 KHz for 24 MHz XTAL */
399 MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, /* 408.20 KHz for 24 MHz XTAL */
401 MXL_HYDRA_STEP_SIZE_27_XTAL_102_05KHZ, /* 102.05 KHz for 27 MHz XTAL */
402 MXL_HYDRA_STEP_SIZE_27_XTAL_204_35KHZ, /* 204.35 KHz for 27 MHz XTAL */
403 MXL_HYDRA_STEP_SIZE_27_XTAL_306_52KHZ, /* 306.52 KHz for 27 MHz XTAL */
404 MXL_HYDRA_STEP_SIZE_27_XTAL_408_69KHZ, /* 408.69 KHz for 27 MHz XTAL */
700 MXL_HYDRA_DISEQC_CARRIER_FREQ_22KHZ = 0, /* DiSEqC signal frequency of 22 KHz */
[all …]
/linux/sound/soc/codecs/
H A Dwm8974.c39 { 24, 0x0032 }, { 25, 0x0000 }, { 26, 0x0000 }, { 27, 0x0000 },
56 static const char *wm8974_deemp[] = {"None", "32kHz", "44.1kHz", "48kHz" };
61 static const char *wm8974_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz" };
62 static const char *wm8974_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz" };
[all...]
H A Dcs48l32.c251 "12kHz",
252 "24kHz",
253 "48kHz",
254 "96kHz",
255 "192kHz",
256 "384kHz",
257 "768kHz",
258 "11.025kHz",
259 "22.05kHz",
[all...]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dnv40.c47 u32 ref = 27000, khz = 0; in read_pll_1() local
50 khz = ref * N / M; in read_pll_1()
52 return khz >> P; in read_pll_1()
61 int N2 = (coef & 0xff000000) >> 24; in read_pll_2()
66 u32 ref = 27000, khz = 0; in read_pll_2() local
69 khz = ref * N1 / M1; in read_pll_2()
72 khz = khz * N2 / M2; in read_pll_2()
74 khz = 0; in read_pll_2()
78 return khz >> P; in read_pll_2()
124 nv40_clk_calc_pll(struct nv40_clk *clk, u32 reg, u32 khz, in nv40_clk_calc_pll() argument
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun55i-a523-ccu.yaml55 - description: High Frequency Oscillator (usually at 24MHz)
56 - description: Low Frequency Oscillator (usually at 32kHz)
77 - description: High Frequency Oscillator (usually at 24MHz)
78 - description: Low Frequency Oscillator (usually at 32kHz)
109 - description: High Frequency Oscillator (usually at 24MHz)
110 - description: Low Frequency Oscillator (usually at 32kHz)
H A Dstarfive,jh7110-aoncrg.yaml22 - description: Main Oscillator (24 MHz)
29 - description: Main Oscillator (24 MHz)
34 - description: RTC Oscillator (32.768 kHz) or GMAC0 GTX
37 - description: Main Oscillator (24 MHz)
43 - description: RTC Oscillator (32.768 kHz)
/linux/sound/pci/emu10k1/
H A Dp16v.h75 * [26:24] FX engine channel capture 0 = 0x60-0x67.
93 * [18:16] Channel 0 Detected sample rate. 0 - 44.1khz
94 * 1 - 48 khz
95 * 2 - 96 khz
96 * 3 - 192 khz
101 * [26:24] Channel 2 Detected sample rate.
116 * Record source select for channel 2 [26:24]
147 /* SRC48 converts samples rates 44.1, 48, 96, 192 to 48 khz. */
148 /* SRCMulti converts 48khz samples rates to 44.1, 48, 96, 192 to 48. */
174 /* SRC48 converts samples rates 44.1, 48, 96, 192 to 48 khz. */
[all …]
/linux/drivers/media/tuners/
H A Dqt1010_priv.h24 09 10 ? changes every 8/24 MHz; values 1d/1c
41 1a d0 set frequency: 125 kHz scale, n*125 kHz
51 24 d0 ?
65 #define QT1010_STEP (125 * kHz) /*
/linux/include/sound/
H A Ddesignware_i2s.h15 * @data_width: number of bits per sample (8/16/24/32 bit)
16 * @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz)
H A Dak4114.h67 #define AK4114_DIF_24R (AK4114_DIF1|AK4114_DIF0) /* STDO: 24-bit, right justified */
68 #define AK4114_DIF_24L (AK4114_DIF2) /* STDO: 24-bit, left justified */
70 #define AK4114_DIF_I24L (AK4114_DIF2|AK4114_DIF1) /* STDO: 24-bit, left justified; LRCLK, BICK = I…
73 #define AK4114_DEM1 (1<<2) /* 32kHz-48kHz Deemphasis Control */
74 #define AK4114_DEM0 (1<<1) /* 32kHz-48kHz Deemphasis Control */
79 #define AK4114_DFS (1<<0) /* 96kHz Deemphasis Control */
/linux/Documentation/hwmon/
H A Dlm85.rst153 driven by a 22.5 kHz clock. This is a global mode, not per-PWM output,
154 which means that setting any PWM frequency above 11.3 kHz will switch
155 all 3 PWM outputs to a 22.5 kHz frequency. Conversely, setting any PWM
156 frequency below 11.3 kHz will switch all 3 PWM outputs to a frequency
167 fans in a PC or embedded system. The EMC6D101, available in a 24-pin SSOP
179 The LM96000 supports additional high frequency PWM modes (22.5 kHz, 24 kHz,
180 25.7 kHz, 27.7 kHz and 30 kHz), which can be configured on a per-PWM basis.
/linux/sound/firewire/bebob/
H A Dbebob_yamaha_terratec.c18 * Both of them have a capability to change its sampling rate up to 192.0kHz.
19 * At 192.0kHz, the device reports 4 PCM-in, 1 MIDI-in, 6 PCM-out, 1 MIDI-out.
27 * recommend users to close ffado-mixer at 192.0kHz if mixer is needless.
29 * Terratec PHASE 24 FW and PHASE X24 FW are internally the same as
/linux/arch/arm/mach-omap2/
H A Dtimer.c18 * Some parts based off of TI's 24xx code:
83 * Errata i856 says the 32.768KHz crystal does not start at in realtime_counter_init()
84 * power on, so the CPU falls back to an emulated 32KHz clock in realtime_counter_init()
90 * Of course any board built without a populated 32.768KHz in realtime_counter_init()
95 * If they are not 0, then the 32.768KHz clock driving the in realtime_counter_init()
97 * ticks is actually rate/610 rather than 32.768KHz and we in realtime_counter_init()
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q-cm-fx6.dts81 gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
213 /* kHz uV */
220 /* ARM kHz SOC-PU uV */
235 /* kHz uV */
242 /* ARM kHz SOC-PU uV */
257 /* kHz uV */
264 /* ARM kHz SOC-PU uV */
279 /* kHz uV */
286 /* ARM kHz SOC-PU uV */
329 compatible = "atmel,24c02";
/linux/drivers/clk/qcom/
H A Dipq-cmn-pll.c16 * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS
121 CLK_PLL_OUTPUT(IPQ5018_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
122 CLK_PLL_OUTPUT(IPQ5018_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
140 CLK_PLL_OUTPUT(IPQ5332_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
141 CLK_PLL_OUTPUT(IPQ5332_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
150 CLK_PLL_OUTPUT(IPQ5424_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
151 CLK_PLL_OUTPUT(IPQ5424_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
163 CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
164 CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
/linux/arch/arm/mach-rockchip/
H A Dpm.c75 * function of usb wakeup, so do not switch to 32khz, since the usb phy in rk3288_slp_disable_osc()
76 * clk does not connect to 32khz osc in rk3288_slp_disable_osc()
142 * switch its main clock supply to the alternative 32kHz in rk3288_slp_mode_set()
143 * source. Therefore set 30ms on a 32kHz clock for pmic in rk3288_slp_mode_set()
144 * stabilization. Similar 30ms on 24MHz for the other in rk3288_slp_mode_set()
163 /* 30ms on a 24MHz clock for pmic stabilization */ in rk3288_slp_mode_set()
/linux/sound/soc/intel/keembay/
H A Dkmb_platform.h72 #define COMP1_TX_WORDSIZE_2(r) FIELD_GET(GENMASK(24, 22), (r))
117 * @data_width: number of bits per sample (8/16/24/32 bit)
118 * @sample_rate: sampling frequency (8Khz, 16Khz, 48Khz)
/linux/drivers/gpu/drm/amd/include/
H A Datombios.h96 #define ATOM_COMBOPHY_PLL4 24
429 ULONG ulClockFreq:24;
431 ULONG ulClockFreq:24;
479 ULONG ulClockFreq:24; // in unit of 10kHz
481 ULONG ulClockFreq:24; // in unit of 10kHz
518 ULONG ulClock:24; //Input= target clock, output = actual clock
520 ULONG ulClock:24; //Input= target clock, output = actual clock
687 ULONG ulTargetEngineClock; //In 10Khz unit
692 ULONG ulTargetEngineClock; //In 10Khz unit
698 ULONG ulTargetEngineClock; //In 10Khz unit
[all …]

12345678910>>...18