1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx93.dtsi" 10 11/ { 12 model = "NXP i.MX93 9x9 Quick Start Board"; 13 compatible = "fsl,imx93-9x9-qsb", "fsl,imx93"; 14 15 bt_sco_codec: bt-sco-codec { 16 #sound-dai-cells = <1>; 17 compatible = "linux,bt-sco"; 18 }; 19 20 aliases { 21 ethernet0 = &fec; 22 ethernet1 = &eqos; 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 i2c0 = &lpi2c1; 27 i2c1 = &lpi2c2; 28 mmc0 = &usdhc1; 29 mmc1 = &usdhc2; 30 rtc0 = &bbnsm_rtc; 31 serial0 = &lpuart1; 32 serial1 = &lpuart2; 33 serial2 = &lpuart3; 34 serial3 = &lpuart4; 35 serial4 = &lpuart5; 36 }; 37 38 chosen { 39 stdout-path = &lpuart1; 40 }; 41 42 reserved-memory { 43 #address-cells = <2>; 44 #size-cells = <2>; 45 ranges; 46 47 linux,cma { 48 compatible = "shared-dma-pool"; 49 reusable; 50 size = <0 0x10000000>; 51 linux,cma-default; 52 }; 53 54 vdev0vring0: vdev0vring0@a4000000 { 55 reg = <0 0xa4000000 0 0x8000>; 56 no-map; 57 }; 58 59 vdev0vring1: vdev0vring1@a4008000 { 60 reg = <0 0xa4008000 0 0x8000>; 61 no-map; 62 }; 63 64 vdev1vring0: vdev1vring0@a4010000 { 65 reg = <0 0xa4010000 0 0x8000>; 66 no-map; 67 }; 68 69 vdev1vring1: vdev1vring1@a4018000 { 70 reg = <0 0xa4018000 0 0x8000>; 71 no-map; 72 }; 73 74 rsc_table: rsc-table@2021e000 { 75 reg = <0 0x2021e000 0 0x1000>; 76 no-map; 77 }; 78 79 vdevbuffer: vdevbuffer@a4020000 { 80 compatible = "shared-dma-pool"; 81 reg = <0 0xa4020000 0 0x100000>; 82 no-map; 83 }; 84 85 }; 86 87 reg_vref_1v8: regulator-adc-vref { 88 compatible = "regulator-fixed"; 89 regulator-name = "VREF_1V8"; 90 regulator-min-microvolt = <1800000>; 91 regulator-max-microvolt = <1800000>; 92 }; 93 94 reg_audio_pwr: regulator-audio-pwr { 95 compatible = "regulator-fixed"; 96 regulator-name = "audio-pwr"; 97 regulator-min-microvolt = <3300000>; 98 regulator-max-microvolt = <3300000>; 99 gpio = <&pcal6524 16 GPIO_ACTIVE_HIGH>; 100 enable-active-high; 101 }; 102 103 reg_m2_pwr: regulator-m2-pwr { 104 compatible = "regulator-fixed"; 105 regulator-name = "M.2-power"; 106 regulator-min-microvolt = <3300000>; 107 regulator-max-microvolt = <3300000>; 108 gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; 109 enable-active-high; 110 }; 111 112 reg_rpi_3v3: regulator-rpi { 113 compatible = "regulator-fixed"; 114 regulator-name = "VDD_RPI_3V3"; 115 regulator-min-microvolt = <3300000>; 116 regulator-max-microvolt = <3300000>; 117 gpio = <&pcal6524 21 GPIO_ACTIVE_HIGH>; 118 enable-active-high; 119 }; 120 121 reg_usdhc2_vmmc: regulator-usdhc2 { 122 compatible = "regulator-fixed"; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 125 regulator-name = "VSD_3V3"; 126 regulator-min-microvolt = <3300000>; 127 regulator-max-microvolt = <3300000>; 128 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 129 enable-active-high; 130 off-on-delay-us = <12000>; 131 }; 132 133 reg_usdhc3_vmmc: regulator-usdhc3 { 134 compatible = "regulator-fixed"; 135 regulator-name = "WLAN_EN"; 136 regulator-min-microvolt = <3300000>; 137 regulator-max-microvolt = <3300000>; 138 vin-supply = <®_m2_pwr>; 139 gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; 140 /* 141 * IW612 wifi chip needs more delay than other wifi chips to complete 142 * the host interface initialization after power up, otherwise the 143 * internal state of IW612 may be unstable, resulting in the failure of 144 * the SDIO3.0 switch voltage. 145 */ 146 startup-delay-us = <20000>; 147 enable-active-high; 148 }; 149 150 sound-bt-sco { 151 compatible = "simple-audio-card"; 152 simple-audio-card,name = "bt-sco-audio"; 153 simple-audio-card,format = "dsp_a"; 154 simple-audio-card,bitclock-inversion; 155 simple-audio-card,frame-master = <&btcpu>; 156 simple-audio-card,bitclock-master = <&btcpu>; 157 158 btcpu: simple-audio-card,cpu { 159 sound-dai = <&sai1>; 160 dai-tdm-slot-num = <2>; 161 dai-tdm-slot-width = <16>; 162 }; 163 164 simple-audio-card,codec { 165 sound-dai = <&bt_sco_codec 1>; 166 }; 167 }; 168 169 sound-micfil { 170 compatible = "fsl,imx-audio-card"; 171 model = "micfil-audio"; 172 173 pri-dai-link { 174 link-name = "micfil hifi"; 175 format = "i2s"; 176 177 cpu { 178 sound-dai = <&micfil>; 179 }; 180 }; 181 }; 182 183 sound-wm8962 { 184 compatible = "fsl,imx-audio-wm8962"; 185 model = "wm8962-audio"; 186 audio-cpu = <&sai3>; 187 audio-codec = <&wm8962>; 188 hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; 189 audio-routing = 190 "Headphone Jack", "HPOUTL", 191 "Headphone Jack", "HPOUTR", 192 "Ext Spk", "SPKOUTL", 193 "Ext Spk", "SPKOUTR", 194 "AMIC", "MICBIAS", 195 "IN3R", "AMIC", 196 "IN1R", "AMIC"; 197 }; 198 199 usdhc3_pwrseq: usdhc3_pwrseq { 200 compatible = "mmc-pwrseq-simple"; 201 reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; 202 }; 203}; 204 205&adc1 { 206 vref-supply = <®_vref_1v8>; 207 status = "okay"; 208}; 209 210&cm33 { 211 mbox-names = "tx", "rx", "rxdb"; 212 mboxes = <&mu1 0 1>, 213 <&mu1 1 1>, 214 <&mu1 3 1>; 215 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 216 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 217 status = "okay"; 218}; 219 220&eqos { 221 pinctrl-names = "default"; 222 pinctrl-0 = <&pinctrl_eqos>; 223 phy-mode = "rgmii-id"; 224 phy-handle = <ðphy1>; 225 status = "okay"; 226 227 mdio { 228 compatible = "snps,dwmac-mdio"; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 clock-frequency = <5000000>; 232 233 ethphy1: ethernet-phy@1 { 234 compatible = "ethernet-phy-ieee802.3-c22"; 235 reg = <1>; 236 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; 237 reset-assert-us = <10000>; 238 reset-deassert-us = <80000>; 239 realtek,clkout-disable; 240 }; 241 }; 242}; 243 244&lpi2c1 { 245 clock-frequency = <400000>; 246 pinctrl-names = "default"; 247 pinctrl-0 = <&pinctrl_lpi2c1>; 248 status = "okay"; 249 250 wm8962: audio-codec@1a { 251 compatible = "wlf,wm8962"; 252 reg = <0x1a>; 253 clocks = <&clk IMX93_CLK_SAI3_GATE>; 254 DCVDD-supply = <®_audio_pwr>; 255 DBVDD-supply = <®_audio_pwr>; 256 AVDD-supply = <®_audio_pwr>; 257 CPVDD-supply = <®_audio_pwr>; 258 MICVDD-supply = <®_audio_pwr>; 259 PLLVDD-supply = <®_audio_pwr>; 260 SPKVDD1-supply = <®_audio_pwr>; 261 SPKVDD2-supply = <®_audio_pwr>; 262 gpio-cfg = < 263 0x0000 /* 0:Default */ 264 0x0000 /* 1:Default */ 265 0x0000 /* 2:FN_DMICCLK */ 266 0x0000 /* 3:Default */ 267 0x0000 /* 4:FN_DMICCDAT */ 268 0x0000 /* 5:Default */ 269 >; 270 }; 271 272 p3t1085: temperature-sensor@48 { 273 compatible = "nxp,p3t1085"; 274 reg = <0x48>; 275 }; 276 277 ptn5110: tcpc@50 { 278 compatible = "nxp,ptn5110", "tcpci"; 279 reg = <0x50>; 280 interrupt-parent = <&gpio3>; 281 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 282 283 typec1_con: connector { 284 compatible = "usb-c-connector"; 285 label = "USB-C"; 286 power-role = "dual"; 287 data-role = "dual"; 288 try-power-role = "sink"; 289 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 290 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 291 PDO_VAR(5000, 20000, 3000)>; 292 op-sink-microwatt = <15000000>; 293 self-powered; 294 295 ports { 296 #address-cells = <1>; 297 #size-cells = <0>; 298 299 port@0 { 300 reg = <0>; 301 302 typec1_dr_sw: endpoint { 303 remote-endpoint = <&usb1_drd_sw>; 304 }; 305 }; 306 }; 307 }; 308 }; 309 310 rtc@53 { 311 compatible = "nxp,pcf2131"; 312 reg = <0x53>; 313 interrupt-parent = <&pcal6524>; 314 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 315 }; 316 317 inertial-meter@6a { 318 compatible = "st,lsm6dso"; 319 reg = <0x6a>; 320 }; 321}; 322 323&lpi2c2 { 324 clock-frequency = <400000>; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&pinctrl_lpi2c2>; 327 status = "okay"; 328 329 pcal6524: gpio@22 { 330 compatible = "nxp,pcal6524"; 331 reg = <0x22>; 332 gpio-controller; 333 #gpio-cells = <2>; 334 interrupt-controller; 335 #interrupt-cells = <2>; 336 interrupt-parent = <&gpio3>; 337 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 338 pinctrl-names = "default"; 339 pinctrl-0 = <&pinctrl_pcal6524>; 340 341 exp-sel-hog { 342 gpio-hog; 343 gpios = <22 GPIO_ACTIVE_HIGH>; 344 output-low; 345 }; 346 347 mic-can-sel-hog { 348 gpio-hog; 349 gpios = <17 GPIO_ACTIVE_HIGH>; 350 output-low; 351 }; 352 353 m2-pcm-level-shifter-hog { 354 gpio-hog; 355 gpios = <19 GPIO_ACTIVE_HIGH>; 356 output-high; 357 }; 358 }; 359 360 pmic@25 { 361 compatible = "nxp,pca9451a"; 362 reg = <0x25>; 363 interrupt-parent = <&pcal6524>; 364 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 365 366 regulators { 367 buck1: BUCK1 { 368 regulator-name = "BUCK1"; 369 regulator-min-microvolt = <650000>; 370 regulator-max-microvolt = <2237500>; 371 regulator-boot-on; 372 regulator-always-on; 373 regulator-ramp-delay = <3125>; 374 }; 375 376 buck2: BUCK2 { 377 regulator-name = "BUCK2"; 378 regulator-min-microvolt = <600000>; 379 regulator-max-microvolt = <2187500>; 380 regulator-boot-on; 381 regulator-always-on; 382 regulator-ramp-delay = <3125>; 383 }; 384 385 buck4: BUCK4 { 386 regulator-name = "BUCK4"; 387 regulator-min-microvolt = <600000>; 388 regulator-max-microvolt = <3400000>; 389 regulator-boot-on; 390 regulator-always-on; 391 }; 392 393 buck5: BUCK5 { 394 regulator-name = "BUCK5"; 395 regulator-min-microvolt = <600000>; 396 regulator-max-microvolt = <3400000>; 397 regulator-boot-on; 398 regulator-always-on; 399 }; 400 401 buck6: BUCK6 { 402 regulator-name = "BUCK6"; 403 regulator-min-microvolt = <600000>; 404 regulator-max-microvolt = <3400000>; 405 regulator-boot-on; 406 regulator-always-on; 407 }; 408 409 ldo1: LDO1 { 410 regulator-name = "LDO1"; 411 regulator-min-microvolt = <1600000>; 412 regulator-max-microvolt = <3300000>; 413 regulator-boot-on; 414 regulator-always-on; 415 }; 416 417 ldo4: LDO4 { 418 regulator-name = "LDO4"; 419 regulator-min-microvolt = <800000>; 420 regulator-max-microvolt = <3300000>; 421 regulator-boot-on; 422 regulator-always-on; 423 }; 424 425 ldo5: LDO5 { 426 regulator-name = "LDO5"; 427 regulator-min-microvolt = <1800000>; 428 regulator-max-microvolt = <3300000>; 429 regulator-boot-on; 430 regulator-always-on; 431 }; 432 }; 433 }; 434}; 435 436&lpuart1 { /* console */ 437 pinctrl-names = "default"; 438 pinctrl-0 = <&pinctrl_uart1>; 439 status = "okay"; 440}; 441 442&lpuart5 { 443 /* BT */ 444 pinctrl-names = "default"; 445 pinctrl-0 = <&pinctrl_uart5>; 446 status = "okay"; 447 448 bluetooth { 449 compatible = "nxp,88w8987-bt"; 450 }; 451}; 452 453&micfil { 454 pinctrl-names = "default"; 455 pinctrl-0 = <&pinctrl_pdm>; 456 assigned-clocks = <&clk IMX93_CLK_PDM>; 457 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 458 assigned-clock-rates = <49152000>; 459 status = "okay"; 460}; 461 462&mu1 { 463 status = "okay"; 464}; 465 466&mu2 { 467 status = "okay"; 468}; 469 470&sai1 { 471 pinctrl-names = "default"; 472 pinctrl-0 = <&pinctrl_sai1>; 473 assigned-clocks = <&clk IMX93_CLK_SAI1>; 474 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 475 assigned-clock-rates = <12288000>; 476 fsl,sai-mclk-direction-output; 477 status = "okay"; 478}; 479 480&sai3 { 481 pinctrl-names = "default"; 482 pinctrl-0 = <&pinctrl_sai3>; 483 assigned-clocks = <&clk IMX93_CLK_SAI3>; 484 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 485 assigned-clock-rates = <12288000>; 486 fsl,sai-mclk-direction-output; 487 fsl,sai-synchronous-rx; 488 status = "okay"; 489}; 490 491&usbotg1 { 492 dr_mode = "otg"; 493 hnp-disable; 494 srp-disable; 495 adp-disable; 496 usb-role-switch; 497 disable-over-current; 498 samsung,picophy-pre-emp-curr-control = <3>; 499 samsung,picophy-dc-vol-level-adjust = <7>; 500 status = "okay"; 501 502 port { 503 usb1_drd_sw: endpoint { 504 remote-endpoint = <&typec1_dr_sw>; 505 }; 506 }; 507}; 508 509&usdhc1 { 510 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 511 pinctrl-0 = <&pinctrl_usdhc1>; 512 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 513 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 514 bus-width = <8>; 515 non-removable; 516 fsl,tuning-step = <1>; 517 status = "okay"; 518}; 519 520&usdhc2 { 521 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 522 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 523 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 524 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 525 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 526 vmmc-supply = <®_usdhc2_vmmc>; 527 bus-width = <4>; 528 no-mmc; 529 fsl,tuning-step = <1>; 530 status = "okay"; 531}; 532 533&usdhc3 { 534 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 535 pinctrl-0 = <&pinctrl_usdhc3>; 536 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 537 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 538 mmc-pwrseq = <&usdhc3_pwrseq>; 539 vmmc-supply = <®_usdhc3_vmmc>; 540 bus-width = <4>; 541 keep-power-in-suspend; 542 non-removable; 543 wakeup-source; 544 status = "okay"; 545}; 546 547&wdog3 { 548 pinctrl-names = "default"; 549 pinctrl-0 = <&pinctrl_wdog>; 550 fsl,ext-reset-output; 551 status = "okay"; 552}; 553 554&iomuxc { 555 pinctrl_eqos: eqosgrp { 556 fsl,pins = < 557 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e 558 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 559 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 560 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 561 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 562 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 563 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e 564 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 565 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 566 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e 567 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 568 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 569 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e 570 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 571 >; 572 }; 573 574 pinctrl_lpi2c1: lpi2c1grp { 575 fsl,pins = < 576 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 577 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 578 >; 579 }; 580 581 pinctrl_lpi2c2: lpi2c2grp { 582 fsl,pins = < 583 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 584 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 585 >; 586 }; 587 588 pinctrl_pcal6524: pcal6524grp { 589 fsl,pins = < 590 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e 591 >; 592 }; 593 594 pinctrl_pdm: pdmgrp { 595 fsl,pins = < 596 MX93_PAD_PDM_CLK__PDM_CLK 0x31e 597 MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e 598 MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e 599 >; 600 }; 601 602 pinctrl_uart1: uart1grp { 603 fsl,pins = < 604 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 605 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 606 >; 607 }; 608 609 pinctrl_uart5: uart5grp { 610 fsl,pins = < 611 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 612 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e 613 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 614 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 615 >; 616 }; 617 618 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 619 pinctrl_usdhc1: usdhc1grp { 620 fsl,pins = < 621 MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 622 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 623 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 624 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 625 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 626 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 627 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 628 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 629 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 630 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 631 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 632 >; 633 }; 634 635 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 636 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 637 fsl,pins = < 638 MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e 639 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e 640 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 641 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e 642 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e 643 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e 644 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e 645 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e 646 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e 647 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e 648 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 649 >; 650 }; 651 652 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 653 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 654 fsl,pins = < 655 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 656 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe 657 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe 658 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe 659 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe 660 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe 661 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe 662 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe 663 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe 664 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe 665 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 666 >; 667 }; 668 669 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 670 fsl,pins = < 671 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 672 >; 673 }; 674 675 pinctrl_sai1: sai1grp { 676 fsl,pins = < 677 MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e 678 MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e 679 MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e 680 MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e 681 >; 682 }; 683 684 pinctrl_sai3: sai3grp { 685 fsl,pins = < 686 MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x31e 687 MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x31e 688 MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e 689 MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e 690 MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e 691 >; 692 }; 693 694 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 695 fsl,pins = < 696 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 697 >; 698 }; 699 700 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 701 pinctrl_usdhc2: usdhc2grp { 702 fsl,pins = < 703 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 704 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 705 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 706 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 707 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 708 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 709 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 710 >; 711 }; 712 713 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 714 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 715 fsl,pins = < 716 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e 717 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e 718 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 719 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 720 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e 721 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e 722 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 723 >; 724 }; 725 726 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 727 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 728 fsl,pins = < 729 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 730 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe 731 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe 732 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe 733 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe 734 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe 735 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 736 >; 737 }; 738 739 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 740 pinctrl_usdhc3: usdhc3grp { 741 fsl,pins = < 742 MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 743 MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 744 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 745 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 746 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 747 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 748 >; 749 }; 750 751 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 752 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 753 fsl,pins = < 754 MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e 755 MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e 756 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e 757 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e 758 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e 759 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e 760 >; 761 }; 762 763 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 764 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 765 fsl,pins = < 766 MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe 767 MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe 768 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe 769 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe 770 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe 771 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe 772 >; 773 }; 774 775 pinctrl_wdog: wdoggrp { 776 fsl,pins = < 777 MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e 778 >; 779 }; 780}; 781