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/linux/drivers/w1/masters/
H A DKconfig3 # 1-wire bus master configuration
6 menu "1-wire Bus Masters"
9 tristate "AMD AXI 1-wire bus host"
11 Say Y here is you want to support the AMD AXI 1-wire IP core.
13 correctly timed 1 wire transactions without relying on GPIO timing
20 tristate "Matrox G400 transport layer for 1-wire"
23 Say Y here if you want to communicate with your 1-wire devices
30 tristate "DS2490 USB <-> W1 transport layer for 1-wire"
40 tristate "Maxim DS2482 I2C to 1-Wire bridge"
44 I2C to 1-Wire bridge.
[all …]
H A Damd_axi_w1.c3 * amd_axi_w1 - AMD 1Wire programmable logic bus host driver
23 /* 1-wire AMD IP definition */
100 * amd_axi_w1_touch_bit() - Performs the touch-bit function - write a 0 or 1 and reads the level.
113 /* Wait for READY signal to be 1 to ensure 1-wire IP is ready */ in amd_axi_w1_touch_bit()
118 return 1; /* Callee doesn't test for error. Return inactive bus state */ in amd_axi_w1_touch_bit()
132 /* Wait for done signal to be 1 */ in amd_axi_w1_touch_bit()
133 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) { in amd_axi_w1_touch_bit()
136 return 1; /* Callee doesn't test for error. Return inactive bus state */ in amd_axi_w1_touch_bit()
143 /* Clear Go signal in register 1 */ in amd_axi_w1_touch_bit()
161 /* Wait for READY signal to be 1 to ensure 1-wire IP is ready */ in amd_axi_w1_read_byte()
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H A Dsgi_w1.c3 * sgi_w1.c - w1 master driver for one wire support in SGI ASICs
18 #define MCR_DONE BIT(1)
36 return (mcr_val & MCR_RD_DATA) ? 1 : 0; in sgi_w1_wait()
41 * reset the device on the One Wire interface
56 * this is the low level routine to read/write a bit on the One Wire
58 * to 0, otherwise a write 1/read.
126 MODULE_DESCRIPTION("Driver for One-Wire IP in SGI ASICs");
/linux/drivers/w1/slaves/
H A DKconfig3 # 1-wire slaves configuration
6 menu "1-wire Slaves"
11 Say Y here if you want to connect 1-wire thermal sensors to your
12 wire.
17 Say Y here if you want to connect 1-wire
18 simple 64bit memory rom(ds2401/ds2411/ds1990*) to your wire.
23 Say Y or M here if you want to use a DS2405 1-wire
31 Say Y here if you want to use a 1-wire
47 Say Y here if you want to use a 1-wire
54 Say Y or M here if you want to use a 1-wire
[all …]
/linux/Documentation/w1/masters/
H A Dw1-uart.rst13 UART 1-Wire bus driver. The driver utilizes the UART interface via the
14 Serial Device Bus to create the 1-Wire timing patterns as described in
15 the document `"Using a UART to Implement a 1-Wire Bus Master"`_.
17 …sing a UART to Implement a 1-Wire Bus Master": https://www.analog.com/en/technical-articles/using-…
22 1-Wire read bit, write bit or reset pulse.
24 For instance the timing pattern for a 1-Wire reset and presence detect uses
27 for 1-Wire to 521 us. A present 1-Wire device changes the received byte by
29 the 1-Wire operation.
31 Similar for a 1-Wire read bit or write bit, which uses the baud-rate
33 Write-0 operation (low time 69.6us) and the byte 0xff for Read-0, Read-1
[all …]
H A Domap-hdq.rst2 Kernel driver for omap HDQ/1-wire module
7 HDQ/1-wire controller on the TI OMAP 2430/3430 platforms.
15 The HDQ/1-Wire module of TI OMAP2430/3430 platforms implement the hardware
17 Semiconductor 1-Wire protocols. These protocols use a single wire for
18 communication between the master (HDQ/1-Wire controller) and the slave
19 (HDQ/1-Wire external compliant device).
21 A typical application of the HDQ/1-Wire module is the communication with battery
24 The controller supports operation in both HDQ and 1-wire mode. The essential
25 difference between the HDQ and 1-wire mode is how the slave device responds to
29 does not respond with a presence pulse as it does in the 1-Wire protocol.
[all …]
/linux/Documentation/devicetree/bindings/w1/
H A Dw1-uart.yaml7 title: UART 1-Wire Bus
13 UART 1-wire bus. Utilizes the UART interface via the Serial Device Bus
14 to create the 1-Wire timing patterns.
18 baud-rate and transmitted byte, which corresponds to a 1-Wire read bit,
22 a 1-Wire read or write operation 115200. In case the actual baud-rate
24 to generate the 1-Wire timing patterns.
26 https://www.analog.com/en/technical-articles/using-a-uart-to-implement-a-1wire-bus-master.html
35 The baud rate for the 1-Wire reset and presence detect.
40 The baud rate for the 1-Wire write-0 cycle.
42 write-1-bps:
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H A Damd,axi-1wire-host.yaml4 $id: http://devicetree.org/schemas/w1/amd,axi-1wire-host.yaml#
7 title: AMD AXI 1-wire bus host for programmable logic
14 const: amd,axi-1wire-host
17 maxItems: 1
20 maxItems: 1
23 maxItems: 1
38 compatible = "amd,axi-1wire-host";
/linux/include/linux/mfd/
H A Dmotorola-cpcap.h18 #define CPCAP_VENDOR_TI 1
20 #define CPCAP_REVISION_MAJOR(r) (((r) >> 4) + 1)
29 #define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */
33 #define CPCAP_REG_INTM1 0x0010 /* Interrupt Mask 1 */
37 #define CPCAP_REG_INTS1 0x0020 /* Interrupt Sense 1 */
41 #define CPCAP_REG_ASSIGN1 0x0030 /* Resource Assignment 1 */
47 #define CPCAP_REG_VERSC1 0x0048 /* Version Control 1 */
50 #define CPCAP_REG_MI1 0x0200 /* Macro Interrupt 1 */
51 #define CPCAP_REG_MIM1 0x0204 /* Macro Interrupt Mask 1 */
54 #define CPCAP_REG_UCC1 0x0210 /* UC Control 1 */
[all …]
/linux/Documentation/peci/
H A Dpeci.rst24 PECI Wire
27 PECI Wire interface uses a single wire for self-clocking and data
29 physical layer is a self-clocked one-wire bus signal that begins each
32 value is logic '0' or logic '1'. PECI Wire also includes variable data
35 For PECI Wire, each processor package will utilize unique, fixed
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dintel,ce4100-lapic.yaml20 See [1] Chapter 8 for more details.
28 [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
35 maxItems: 1
42 intel,virtual-wire-mode:
47 Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode.
52 mode is configured to virtual wire compatibility mode.
70 intel,virtual-wire-mode;
H A Darm,gic-v5-iwb.yaml7 title: ARM Generic Interrupt Controller, version 5 Interrupt Wire Bridge (IWB)
20 GICv5 has zero or more Interrupt Wire Bridges (IWB) that are responsible
21 for translating wire signals into interrupt messages to the GICv5 ITS.
39 The 1st cell corresponds to the IWB wire.
44 1 = low-to-high edge triggered
54 maxItems: 1
/linux/Documentation/devicetree/bindings/display/panel/
H A Dtpo,tpg110.yaml17 and other properties, and has a control interface over 3WIRE
39 protocol is not I2C but 3WIRE SPI.
55 maxItems: 1
58 maxItems: 1
61 spi-3wire: true
72 - spi-3wire
81 #address-cells = <1>;
87 spi-3wire;
93 grestb-gpios = <&foo_gpio 5 1>;
/linux/arch/sh/mm/
H A Dtlb-urb.c18 * Load the entry for 'addr' into the TLB and wire the entry.
32 * Make sure we're not trying to wire the last TLB entry slot. in tlb_wire_entry()
49 /* ... and wire it up. */ in tlb_wire_entry()
64 * It should also be noted that it is not possible to wire and unwire
65 * TLB entries in an arbitrary order. If you wire TLB entry N, followed
66 * by entry N+1, you must unwire entry N+1 first, then entry N. In this
/linux/drivers/w1/
H A DKconfig3 tristate "Dallas's 1-wire support"
6 Dallas' 1-wire bus is useful to connect slow 1-pin devices
12 will be called wire.
24 1. Events. They are generated each time new master or slave device found
H A DMakefile3 # Makefile for the Dallas's 1-wire bus.
6 obj-$(CONFIG_W1) += wire.o
7 wire-objs := w1.o w1_int.o w1_family.o w1_netlink.o w1_io.o
/linux/arch/sh/include/mach-common/mach/
H A Dhighlander.h11 #define PA_SDPOW (-1)
15 #define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */
62 #define PA_SMCR (PA_BCR+0x0600) /* 2-wire Serial control */
63 #define PA_SMSMADR (PA_BCR+0x0602) /* 2-wire Serial Slave control */
64 #define PA_SMMR (PA_BCR+0x0604) /* 2-wire Serial Mode control */
65 #define PA_SMSADR1 (PA_BCR+0x0606) /* 2-wire Serial Address1 control */
66 #define PA_SMTRDR1 (PA_BCR+0x0646) /* 2-wire Serial Data1 control */
75 #define PA_POFF (-1)
84 #define PA_ZIGIO1 (PA_BCR+0x000c) /* Zigbee IO control 1 */
114 #define PA_SMCR (PA_BCR+0x0500) /* 2-wire Serial control */
[all …]
/linux/Documentation/devicetree/bindings/input/touchscreen/
H A Dti,am3359-tsc.yaml17 description: Wires refer to application modes i.e. 4/5/8 wire touchscreen
33 minimum: 1
36 ti,wire-config:
41 input lines and terminals respectively are as follows, AIN0 = 0, AIN1 = 1
42 and so on until AIN7 = 7. XP = 0, XN = 1, YP = 2, YN = 3.
63 - ti,wire-config
74 ti,wire-config = <0x00 0x11 0x22 0x33>;
/linux/Documentation/iio/
H A Dad4000.rst41 * `AD7988-1 <https://www.analog.com/AD7988-1>`_
50 CS mode, 3-wire turbo mode
53 Datasheet "3-wire" mode is what most resembles standard SPI connection which,
56 "CS Mode, 3-Wire Turbo Mode" connection in datasheets.
57 NOTE: The datasheet definition of 3-wire mode for the AD4000 series is NOT the
58 same of standard spi-3wire mode.
80 CS mode, 3-wire, without busy indicator
83 Another wiring configuration supported as "3-wire" mode has the SDI pin
86 is not possible. This connection mode saves one wire and works with any SPI
122 CS mode, 4-wire without busy indicator
[all …]
/linux/include/linux/platform_data/
H A Dusb-omap1.h22 unsigned register_host:1;
23 unsigned register_dev:1;
24 u8 otg; /* port number, 1-based: usb1 == 2 */
36 * 3 == 3 wire bidirectional
37 * 4 == 4 wire bidirectional
38 * 6 == 6 wire unidirectional (or TLL)
/linux/tools/testing/selftests/drivers/net/hw/
H A Dtso.py84 ksft_ge(qstat_new['tx-hw-gso-wire-packets'] -
85 qstat_old['tx-hw-gso-wire-packets'],
87 comment="Number of LSO wire-packets with LSO enabled")
94 ksft_lt(qstat_new['tx-hw-gso-wire-packets'] -
95 qstat_old['tx-hw-gso-wire-packets'],
96 500, comment="Number of LSO wire-packets with LSO disabled")
100 local_v4 = NetDrvEpEnv.nsim_v4_pfx + "1"
101 local_v6 = NetDrvEpEnv.nsim_v6_pfx + "1"
109 tun_arg = tun_info[1]
221 if 'tx-hw-gso-wire
[all...]
/linux/Documentation/devicetree/bindings/sound/
H A Dawinic,aw8738.yaml14 (set using one-wire pulse control). The mode configures the speaker-guard
26 GPIO used for one-wire pulse control. The pin is typically called SHDN
29 maxItems: 1
32 description: Operation mode (number of pulses for one-wire pulse control)
34 minimum: 1
/linux/Documentation/devicetree/bindings/spi/
H A Dicpdas-lp8841-spi-rtc.txt13 - #address-cells: should be 1
28 - spi-3wire: The master itself has only 3 wire. It cannor work in
41 #address-cells = <1>;
50 spi-3wire;
/linux/Documentation/devicetree/bindings/rtc/
H A Dnxp,pcf85063.yaml23 maxItems: 1
29 maxItems: 1
32 maxItems: 1
50 spi-3wire: true
75 spi-3wire: false
86 #address-cells = <1>;
104 #address-cells = <1>;
111 spi-3wire;
/linux/sound/ppc/
H A Dsnd_ps3_reg.h39 * three wire serial
49 * n:0..1
66 can be cleared by writing a '1' to the corresponding bit. A new interrupt
77 #define PS3_AUDIO_INTR_0_CHAN(n) (1 << ((n) * 2))
86 #define PS3_AUDIO_INTR_0_CHAN1 PS3_AUDIO_INTR_0_CHAN(1)
119 #define PS3_AUDIO_CONFIG_CLEAR (1 << 8) /* RWIVF */
130 /* 3 Wire Audio Serial Output Channel Mutes (0..3) */
131 #define PS3_AUDIO_AX_MCTRL_ASOMT(n) (1 << (3 - (n))) /* RWIVF */
132 #define PS3_AUDIO_AX_MCTRL_ASO3MT (1 << 0) /* RWIVF */
133 #define PS3_AUDIO_AX_MCTRL_ASO2MT (1 << 1) /* RWIVF */
[all …]

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