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/freebsd/share/man/man4/
H A Dpms.430 .Nd "PMC-Sierra PM8001/8081/8088/8089/8074/8076/8077 SAS/SATA HBA Controller driver"
35 .Bd -ragged -offset indent
42 .Bd -literal -offset indent
48 driver provides support for the PMC-Sierra PM8001/8081/8088/8089/8074/8076/8077
55 .Bl -bullet -compact
57 Tachyon TS Fibre Channel Card
59 Tachyon TL Fibre Channel Card
61 Tachyon XL2 Fibre Channel Card
63 Tachyon DX2 Fibre Channel Card
65 Tachyon DX2+ Fibre Channel Card
[all …]
/freebsd/usr.sbin/virtual_oss/virtual_oss/
H A Dvirtual_oss.82 .\" Copyright (c) 2017-2022 Hans Petter Selasky <hselasky@freebsd.org>
52 All channel numbers start at zero.
53 Left channel is zero and right channel is one.
56 .Bl -tag -width indent
67 Valid values are 8, 16, 24 and 32.
69 Set default sample-rate for the subsequent commands.
75 The buffer size specified is per channel.
78 Set real-time priority to
87 Valid values range from -63 to 63 inclusivly.
96 Valid values range from -63 to 63 inclusivly.
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/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dqcom,spmi-vadc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
15 voltage. The VADC is a 15-bit sigma-delta ADC.
17 voltage. The VADC is a 16-bit sigma-delta ADC.
22 - items:
23 - const: qcom,pms405-adc
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H A Dqcom,spmi-vadc.txt3 - SPMI PMIC voltage ADC (VADC) provides interface to clients to read
4 voltage. The VADC is a 15-bit sigma-delta ADC.
5 - SPMI PMIC5 voltage ADC (ADC) provides interface to clients to read
6 voltage. The VADC is a 16-bit sigma-delta ADC.
10 - compatible:
13 Definition: Should contain "qcom,spmi-vadc".
14 Should contain "qcom,spmi-adc5" for PMIC5 ADC driver.
15 Should contain "qcom,spmi-adc-rev2" for PMIC rev2 ADC driver.
16 Should contain "qcom,pms405-adc" for PMS405 PMIC
18 - reg:
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H A Dti,am3359-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/ti,am3359-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
15 - enum:
16 - ti,am3359-adc
17 - ti,am4372-adc
18 - items:
19 - enum:
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Deeprom.h1 /* SPDX-License-Identifier: ISC */
48 #define MT_EE_CAL_GROUP_SIZE_7915 (49 * MT_EE_CAL_UNIT + 16)
49 #define MT_EE_CAL_GROUP_SIZE_7916 (54 * MT_EE_CAL_UNIT + 16)
50 #define MT_EE_CAL_GROUP_SIZE_7975 (54 * MT_EE_CAL_UNIT + 16)
51 #define MT_EE_CAL_GROUP_SIZE_7976 (94 * MT_EE_CAL_UNIT + 16)
52 #define MT_EE_CAL_GROUP_SIZE_7916_6G (94 * MT_EE_CAL_UNIT + 16)
114 mt7915_get_channel_group_5g(int channel, bool is_7976) in mt7915_get_channel_group_5g() argument
117 if (channel <= 64) in mt7915_get_channel_group_5g()
119 if (channel <= 96) in mt7915_get_channel_group_5g()
121 if (channel <= 128) in mt7915_get_channel_group_5g()
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/freebsd/sys/dts/powerpc/
H A Dp3041si.dtsi4 * Copyright 2010-2011 Freescale Semiconductor Inc.
35 /dts-v1/;
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
102 #address-cells = <1>;
103 #size-cells = <0>;
108 bus-frequency = <749999996>;
109 next-level-cache = <&L2_0>;
110 L2_0: l2-cache {
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H A Dp5020si.dtsi4 * Copyright 2010-2011 Freescale Semiconductor Inc.
35 /dts-v1/;
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
108 #address-cells = <1>;
109 #size-cells = <0>;
114 bus-frequency = <799999998>;
115 next-level-cache = <&L2_0>;
116 L2_0: l2-cache {
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H A Dp2041si.dtsi35 /dts-v1/;
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
101 #address-cells = <1>;
102 #size-cells = <0>;
107 bus-frequency = <749999996>;
108 next-level-cache = <&L2_0>;
109 L2_0: l2-cache {
110 next-level-cache = <&cpc>;
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/freebsd/sys/contrib/device-tree/Bindings/input/
H A Diqs626a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS626A is a 14-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
19 - $ref: touchscreen/touchscreen.yaml#
31 "#address-cells":
34 "#size-cells":
37 azoteq,suspend-mode:
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H A Dazoteq,iqs7222.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
21 - azoteq,iqs7222a
22 - azoteq,iqs7222b
23 - azoteq,iqs7222c
24 - azoteq,iqs7222d
29 irq-gpios:
32 Specifies the GPIO connected to the device's active-low RDY output.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/xilinx/
H A Dxilinx_dma.txt2 It can be configured to have one channel or two channels. If configured
7 target devices. It can be configured to have one channel or two channels.
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
15 target devices. It can be configured to have up to 16 independent transmit
19 - compatible: Should be one of-
20 "xlnx,axi-vdma-1.00.a"
21 "xlnx,axi-dm
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/freebsd/sys/contrib/device-tree/Bindings/pwm/
H A Dmicrochip,corepwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Conor Dooley <conor.dooley@microchip.com>
14 corePWM is an 16 channel pulse width modulator FPGA IP
16 https://www.microsemi.com/existing-parts/parts/152118
19 - $ref: pwm.yaml#
24 - const: microchip,corepwm-rtl-v4
32 "#pwm-cells":
37 microchip,sync-update-mask:
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/freebsd/contrib/file/magic/Magdir/
H A Dplaydate2 #------------------------------------------------------------------------------
8 # https://github.com/jaames/playdate-reverse-engineering
20 >>16 leshort x %d x
41 >15 byte 0 unsigned, 8-bit PCM, 1 channel
42 >15 byte 1 unsigned, 8-bit PCM, 2 channel
43 >15 byte 2 signed, 16-bit little-endian PCM, 1 channel
44 >15 byte 3 signed, 16-bit little-endian PCM, 1 channel
45 >15 byte 4 4-bit ADPCM, 1 channel
46 >15 byte 5 4-bit ADPCM, 2 channel
52 >16 leshort x %d frames,
/freebsd/crypto/openssh/
H A Dchannels.h41 /* Definitions for channel types. */
45 #define SSH_CHANNEL_OPEN 4 /* normal open two-way channel */
50 #define SSH_CHANNEL_RPORT_LISTENER 11 /* Listening to a R-style port */
55 #define SSH_CHANNEL_MUX_CLIENT 16 /* Conn. to mux client */
58 #define SSH_CHANNEL_RUNIX_LISTENER 19 /* Listening to a R-style domain socket. */
59 #define SSH_CHANNEL_MUX_PROXY 20 /* proxy channel for mux-client */
64 #define CHANNEL_CANCEL_PORT_STATIC -1
67 #define CHANNEL_NONBLOCK_LEAVE 0 /* don't modify non-blocking state */
68 #define CHANNEL_NONBLOCK_SET 1 /* set non-blocking state */
69 #define CHANNEL_NONBLOCK_STDIO 2 /* set non-blocking and restore on close */
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/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dsnps,dma-spear1340.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
21 - enum:
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/freebsd/sys/contrib/device-tree/Bindings/iio/dac/
H A Dad5755.txt1 * Analog Devices AD5755 IIO Multi-Channel DAC Linux Driver
4 - compatible: Has to contain one of the following:
6 adi,ad5755-1
11 - reg: spi chip select number for the device
12 - spi-cpha or spi-cpol: is the only modes that is supported
15 - spi-max-frequency: Definition as per
16 Documentation/devicetree/bindings/spi/spi-bus.txt
19 See include/dt-bindings/iio/ad5755.h
20 - adi,ext-dc-dc-compenstation-resistor: boolean set if the hardware have an
23 - adi,dc-dc-phase:
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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dfsl,qmc-audio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/fsl,qmc-audio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
16 if only one QMC channel is used by the DAI or it is working in non-interleaved
20 - $ref: dai-common.yaml#
24 const: fsl,qmc-audio
26 '#address-cells':
28 '#size-cells':
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H A Dsamsung-i2s.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/samsung-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylweste
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/freebsd/sys/contrib/dev/iwlwifi/
H A Diwl-fh.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014, 2018-2021, 2023-2025 Intel Corporation
4 * Copyright (C) 2015-2017 Intel Deutschland GmbH
12 #include "iwl-trans.h"
28 * Keep-Warm (KW) buffer base address.
31 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
33 * from going into a power-savings mode that would cause higher DRAM latency,
34 * and possible data over/under-runs, before all Tx/Rx is complete.
38 * automatically invokes keep-warm accesses when normal accesses might not
42 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-venice-gw702x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/net/ti-dp83867.h>
23 gpio-keys {
24 compatible = "gpio-keys";
26 key-user-pb {
32 key-user-pb1x {
35 interrupt-parent = <&gsc>;
[all …]
H A Dimx8mm-venice-gw700x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/net/ti-dp83867.h>
22 gpio-keys {
23 compatible = "gpio-keys";
25 key-user-pb {
31 key-user-pb1x {
34 interrupt-parent = <&gsc>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/ti/
H A Dkeystone-navigator-qmss.txt5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
9 management of the packet queues. Packets are queued/de-queued by writing or
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
29 - qmgrs : child node describing the individual queue managers on the
32 -- managed-queues : the actual queues managed by each queue manager
[all …]
/freebsd/sys/dev/hptmv/
H A Dentry.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2004-2005 HighPoint Technologies, Inc.
122 static void init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel);
149 #define MAX_DPC 16
157 char DRIVER_VERSION[] = "v1.16";
162 * Description: free allocated queues for the given channel
164 * Parameters: pMvSataAdapter - pointer to the RR18xx controller this
165 * channel connected to.
166 * channelNum - channel number.
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/freebsd/sys/net80211/
H A D_ieee80211.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
53 * PHY mode; this is not really a mode as multi-mode devices
57 * channels were identified as IEEE channel numbers.
100 IEEE80211_PROT_RTSCTS = 2, /* RTS-CTS */
113 IEEE80211_AUTH_SHARED = 2, /* shared-key */
115 IEEE80211_AUTH_AUTO = 4, /* auto-select/accept */
141 uint8_t ic_ieee; /* IEEE channel number */
146 uint8_t ic_extieee; /* HT40 extension channel number */
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