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/linux/Documentation/devicetree/bindings/phy/
H A Dapm,xgene-phy.yaml7 title: APM X-Gene 15Gbps Multi-purpose PHY
13 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
146 0 = 1-2Gbps
147 1 = 2-4Gbps (1st tuple default)
148 2 = 4-8Gbps
149 3 = 8-15Gbps (2nd tuple default)
150 4 = 2.5-4Gbps
151 5 = 4-5Gbps
152 6 = 5-6Gbps
153 7 = 6-16Gbps (3rd tuple default).
/linux/drivers/net/ethernet/ezchip/
H A Dnps_enet.h41 #define TX_CTL_CT_SHIFT 15
51 #define RX_CTL_CR_SHIFT 15
59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
135 #define CFG_3_TX_CBFC_EN_SHIFT 15
/linux/drivers/scsi/mvsas/
H A Dmv_94xx.h156 MVS_IRQ_PCIF_DRBL3 = (1 << 15),
180 * bit 2: 6Gbps support
181 * bit 1: 3Gbps support
182 * bit 0: 1.5Gbps support
188 * bit 5: G1 (1.5Gbps) Without SSC
189 * bit 4: G1 (1.5Gbps) with SSC
190 * bit 3: G2 (3.0Gbps) Without SSC
191 * bit 2: G2 (3.0Gbps) with SSC
192 * bit 1: G3 (6.0Gbps) without SSC
193 * bit 0: G3 (6.0Gbps) with SSC
[all …]
H A Dmv_94xx.c43 * R0Ch -> R118h[15:0] (Adapted DFE F3 - F5 coefficient) in set_phy_tuning()
45 * R0Eh -> R11Ch[15:0] (Generation 1 Setting 1) in set_phy_tuning()
47 * R10h -> R120h[15:0] (Generation 2 Setting 1) in set_phy_tuning()
49 * R12h -> R124h[15:0] (Generation 3 Setting 1) in set_phy_tuning()
177 /* support 1.5 Gbps */ in set_phy_rate()
185 /* support 1.5, 3.0 Gbps */ in set_phy_rate()
192 /* support 1.5, 3.0, 6.0 Gbps */ in set_phy_rate()
233 /*set default phy_rate = 6Gbps*/ in mvs_94xx_config_reg_from_hba()
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_arcturus.h72 #define FEATURE_WAFL_CG_BIT 15
202 #define THROTTLER_APCC_BIT 15
429 XGMI_LINK_RATE_2 = 2, // 2Gbps
430 XGMI_LINK_RATE_4 = 4, // 4Gbps
431 XGMI_LINK_RATE_8 = 8, // 8Gbps
432 XGMI_LINK_RATE_12 = 12, // 12Gbps
433 XGMI_LINK_RATE_16 = 16, // 16Gbps
434 XGMI_LINK_RATE_17 = 17, // 17Gbps
435 XGMI_LINK_RATE_18 = 18, // 18Gbps
436 XGMI_LINK_RATE_19 = 19, // 19Gbps
[all …]
H A Dsmu11_driver_if_sienna_cichlid.h93 #define FEATURE_DS_LCLK_BIT 15
210 #define THROTTLER_PPT2_BIT 15
524 XGMI_LINK_RATE_2 = 2, // 2Gbps
525 XGMI_LINK_RATE_4 = 4, // 4Gbps
526 XGMI_LINK_RATE_8 = 8, // 8Gbps
527 XGMI_LINK_RATE_12 = 12, // 12Gbps
528 XGMI_LINK_RATE_16 = 16, // 16Gbps
529 XGMI_LINK_RATE_17 = 17, // 17Gbps
530 XGMI_LINK_RATE_18 = 18, // 18Gbps
531 XGMI_LINK_RATE_19 = 19, // 19Gbps
[all …]
H A Dsmu13_driver_if_aldebaran.h53 #define FEATURE_WAFL_CG_BIT 15
126 #define THORTTLER_SPARE_15 15
358 uint8_t XgmiLinkSpeed[NUM_XGMI_DPM_LEVELS]; //Gbps [EX: 32 = 32Gbps]
/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_main.h247 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
248 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
249 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
250 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
251 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */
252 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */
253 HCLGE_MAC_SPEED_200G = 200000 /* 200000 Mbps = 200 Gbps */
645 #define HCLGE_FD_USER_DEF_DATA GENMASK(15, 0)
646 #define HCLGE_FD_USER_DEF_OFFSET GENMASK(15, 0)
647 #define HCLGE_FD_USER_DEF_OFFSET_UNMASK GENMASK(15, 0)
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dp_types.h50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane
52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane
53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane
55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane
56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane
57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane
58 LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane
62 LINK_RATE_UHBR10 = 1000, // UHBR10 - 10.0 Gbps/Lane
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-puzzle-m801.dts49 gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
108 /* SFP+ port 2: 10 Gbps indicator */
115 /* SFP+ port 2: 1 Gbps indicator */
122 /* SFP+ port 1: 10 Gbps indicator */
129 /* SFP+ port 1: 1 Gbps indicator */
/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c47 #define PU_IVREF_BIT BIT(15)
88 #define PHY_ISOLATE_MODE BIT(15)
91 #define GS2_TX_SSC_AMP_MASK GENMASK(15, 9)
120 #define SEL_BITS_PCIE_FORCE BIT(15)
134 #define PRD_TXDEEMPH1_MASK BIT(15)
164 #define CFG_SEL_20B BIT(15)
167 #define CFG_PM_OSCCLK_WAIT_MASK GENMASK(15, 12)
608 * All PHY register values are defined in full for 3.125Gbps in comphy_gbe_phy_init()
609 * SERDES speed. The values required for 1.25 Gbps are almost in comphy_gbe_phy_init()
611 * comparison to 3.125 Gbps values. These register values are in comphy_gbe_phy_init()
[all …]
/linux/drivers/net/ethernet/ibm/ehea/
H A Dehea_phyp.h135 u32 max_num_sgel_rq1wqe; /* 15 */
190 #define H_SPEED_1G_F 6 /* 1 Gbps, Full Duplex */
191 #define H_SPEED_10G_F 8 /* 10 Gbps, Full Duplex */
274 u64 rcu; /* 15 */
304 u64 rxrf; /* 15 */
/linux/drivers/gpu/drm/kmb/
H A Dkmb_dsi.c358 data_type_param.size_constraint_bytes = 15; in mipi_get_datatype_params()
395 /* Word count bits [15:0] */ in mipi_tx_fg_section_cfg_regs()
424 * REG_UNPACKED_BYTES0: [15:0]-BYTES0, [31:16]-BYTES1 in mipi_tx_fg_section_cfg_regs()
425 * REG_UNPACKED_BYTES1: [15:0]-BYTES2, [31:16]-BYTES3 in mipi_tx_fg_section_cfg_regs()
529 * REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1 in mipi_tx_fg_cfg_regs()
530 * REG_VSYNC_WIDTH1: [15:0]-VSA for channel2, [31:16]-VSA for channel3 in mipi_tx_fg_cfg_regs()
873 * n: - valid range [0 15] in mipi_tx_pll_setup()
1015 /* BitRate: > 1 Gbps && <= 1.5 Gbps: - slew rate control ON in set_slewrate_gt_1000()
1051 * BitRate: <= 1 Gbps: in set_slewrate_lt_1000()
1137 ndelay(15); in dphy_init_sequence()
[all …]
/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-board.c51 * busses the bus number is encoded in bits <15:8>.
221 /* The simulator gives you a simulated 1Gbps full duplex link */ in __cvmx_helper_board_link_get()
253 case 2: /* 1 Gbps */ in __cvmx_helper_board_link_get()
/linux/drivers/phy/
H A DKconfig130 tristate "APM X-Gene 15Gbps PHY support"
/linux/Documentation/ABI/testing/
H A Dsysfs-ata40 Behind each port, there is a ata_link. If there is a SATA PM in the topology, 15
61 eg. 1.5, 3 Gbps etc.
/linux/Documentation/networking/device_drivers/ethernet/intel/
H A Dixgbe.rst111 - 82599-based QSFP+ adapters only support 4x10 Gbps connections. 1x40 Gbps
113 4x10 Gbps.
115 The link speed must be configured to either 10 Gbps or 1 Gbps to match the link
251 0 - 15 VFs = Up to 8 traffic classes, depending on device support
/linux/drivers/scsi/isci/
H A Dinit.c116 MODULE_PARM_DESC(phy_gen, "PHY generation (1: 1.5Gbps 2: 3.0Gbps 3: 6.0Gbps)");
127 "host and device. If any bits > 15 are set (default) "
/linux/drivers/net/ethernet/intel/igc/
H A Digc_defines.h70 #define IGC_WUFC_EXT_FLX15 BIT(15) /* Flexible Filter 15 Enable */
105 * (RAR[15]) for our directed address used by controllers with
106 * manageability enabled, allowing us room for 15 multicast addresses.
217 #define IGC_COLLISION_THRESHOLD 15
239 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
426 IGC_RXPBSIZE_EXP(15) | IGC_BMC2OSPBSIZE(2) | IGC_RXPBSIZE_BE(15))
580 #define IGC_TS_SDP3_SEL_TT0 (0u << 15) /* Target time 0 is output on SDP3. */
581 #define IGC_TS_SDP3_SEL_TT1 (1u << 15) /* Target time 1 is output on SDP3. */
582 #define IGC_TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */
583 #define IGC_TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */
/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe.h264 #define XGBE_GEN_LO_MASK GENMASK(15, 0)
278 #define XGBE_MAC_SS_10G 0x00 /* 10Gbps - XGMII mode */
279 #define XGBE_MAC_SS_2_5G_GMII 0x02 /* 2.5Gbps - GMII mode (YC) */
280 #define XGBE_MAC_SS_2_5G_XGMII 0x06 /* 2.5Gbps - XGMII mode (P100a) */
281 #define XGBE_MAC_SS_1G 0x03 /* 1Gbps */
/linux/drivers/gpu/drm/bridge/
H A Dtc358767.c200 #define VID_SYNC_DLY GENMASK(15, 0)
204 #define H_TOTAL GENMASK(15, 0)
207 #define H_START GENMASK(15, 0)
210 #define H_ACT GENMASK(15, 0)
216 #define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15)
236 #define AUX_BYTES GENMASK(15, 8)
279 #define AUDIFDATA3 0x0714 /* DP0 Audio Info Frame Bytes 15 to 12 */
309 #define I2SCH0STAT3 0x0894 /* I2S Audio Channel 0 Status Bytes 15 to 12 */
315 #define I2SCH1STAT3 0x08ac /* I2S Audio Channel 1 Status Bytes 15 to 12 */
341 #define COLOR_B GENMASK(15, 8)
[all …]
/linux/Documentation/networking/device_drivers/ethernet/freescale/
H A Ddpaa.rst88 tgec ten gigabit Ethernet controller (10 Gbps)
174 * priorities 12 to 15 - traffic class 3 (high priority)
/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_init_fw_funcs.c50 /* PF WFQ Upper bound, in MB, 10 * burst size of 1ms in 50Gbps */
97 /* PF RL Upper bound is set to 10 * burst size of 1ms in 50Gbps */
158 #define QM_STOP_CMD_GROUP_ID_MASK 15
515 * Set max link speed (100Gbps) per rate limiter.
1579 /* Enable validation for connection region 5: CCFC_CTX_VALID1[15:8] */ in qed_enable_context_validation()
1583 /* Enable validation for connection region 1: TCFC_CTX_VALID0[15:8] */ in qed_enable_context_validation()
/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-clearfog-gtr.dtsi11 1. 6141 switch (2.5Gbps capable)
481 gpios = <15 GPIO_ACTIVE_LOW>;
/linux/Documentation/networking/devlink/
H A Dice.rst268 ice 0000:16:00.0: Available port split options and max port speeds (Gbps):
292 :widths: 15 85
355 0000000000000120 15 00 01 00 01 00 00 00 00 00 00 00 00 00 00 00
404 :widths: 15 85

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