xref: /linux/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml (revision ec71f661a572a770d7c861cd52a50cbbb0e1a8d1) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display color processor
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display color processor, namely COLOR, provides hue, luma and
15  saturation adjustments to get better picture quality and to have one panel
16  resemble the other in their output characteristics.
17  COLOR device node must be siblings to the central MMSYS_CONFIG node.
18  For a description of the MMSYS_CONFIG binding, see
19  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
20  for details.
21
22properties:
23  compatible:
24    oneOf:
25      - enum:
26          - mediatek,mt2701-disp-color
27          - mediatek,mt8167-disp-color
28          - mediatek,mt8173-disp-color
29          - mediatek,mt8195-mdp3-color
30      - items:
31          - enum:
32              - mediatek,mt8188-mdp3-color
33          - const: mediatek,mt8195-mdp3-color
34      - items:
35          - enum:
36              - mediatek,mt7623-disp-color
37              - mediatek,mt2712-disp-color
38          - const: mediatek,mt2701-disp-color
39      - items:
40          - enum:
41              - mediatek,mt6795-disp-color
42              - mediatek,mt8183-disp-color
43              - mediatek,mt8186-disp-color
44              - mediatek,mt8188-disp-color
45              - mediatek,mt8192-disp-color
46              - mediatek,mt8195-disp-color
47              - mediatek,mt8365-disp-color
48          - const: mediatek,mt8173-disp-color
49  reg:
50    maxItems: 1
51
52  interrupts:
53    maxItems: 1
54
55  power-domains:
56    description: A phandle and PM domain specifier as defined by bindings of
57      the power controller specified by phandle. See
58      Documentation/devicetree/bindings/power/power-domain.yaml for details.
59
60  clocks:
61    items:
62      - description: COLOR Clock
63
64  mediatek,gce-client-reg:
65    description: The register of client driver can be configured by gce with
66      4 arguments defined in this property, such as phandle of gce, subsys id,
67      register offset and size. Each GCE subsys id is mapping to a client
68      defined in the header include/dt-bindings/gce/<chip>-gce.h.
69    $ref: /schemas/types.yaml#/definitions/phandle-array
70    maxItems: 1
71
72  ports:
73    $ref: /schemas/graph.yaml#/properties/ports
74    description:
75      Input and output ports can have multiple endpoints, each of those
76      connects to either the primary, secondary, etc, display pipeline.
77
78    properties:
79      port@0:
80        $ref: /schemas/graph.yaml#/properties/port
81        description: COLOR input port
82
83      port@1:
84        $ref: /schemas/graph.yaml#/properties/port
85        description:
86          COLOR output to the input of the next desired component in the
87          display pipeline, for example one of the available CCORR or AAL
88          blocks.
89
90    required:
91      - port@0
92      - port@1
93
94required:
95  - compatible
96  - reg
97  - interrupts
98  - power-domains
99  - clocks
100
101additionalProperties: false
102
103examples:
104  - |
105    #include <dt-bindings/interrupt-controller/arm-gic.h>
106    #include <dt-bindings/clock/mt8173-clk.h>
107    #include <dt-bindings/power/mt8173-power.h>
108    #include <dt-bindings/gce/mt8173-gce.h>
109
110    soc {
111        #address-cells = <2>;
112        #size-cells = <2>;
113
114        color0: color@14013000 {
115            compatible = "mediatek,mt8173-disp-color";
116            reg = <0 0x14013000 0 0x1000>;
117            interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
118            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
119            clocks = <&mmsys CLK_MM_DISP_COLOR0>;
120            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
121        };
122    };
123