1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2021 Linaro Ltd.
4 * Author: Sam Protsenko <semen.protsenko@linaro.org>
5 *
6 * Common Clock Framework support for Exynos850 SoC.
7 */
8
9 #include <linux/clk-provider.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12
13 #include <dt-bindings/clock/exynos850.h>
14
15 #include "clk.h"
16 #include "clk-cpu.h"
17 #include "clk-exynos-arm64.h"
18
19 /* NOTE: Must be equal to the last clock ID increased by one */
20 #define CLKS_NR_TOP (CLK_DOUT_CPUCL1_SWITCH + 1)
21 #define CLKS_NR_APM (CLK_GOUT_MAILBOX_APM_AP_PCLK + 1)
22 #define CLKS_NR_AUD (CLK_GOUT_AUD_CMU_AUD_PCLK + 1)
23 #define CLKS_NR_CMGP (CLK_GOUT_SYSREG_CMGP_PCLK + 1)
24 #define CLKS_NR_CPUCL0 (CLK_CLUSTER0_SCLK + 1)
25 #define CLKS_NR_CPUCL1 (CLK_CLUSTER1_SCLK + 1)
26 #define CLKS_NR_G3D (CLK_GOUT_G3D_SYSREG_PCLK + 1)
27 #define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK + 1)
28 #define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1)
29 #define CLKS_NR_MFCMSCL (CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1)
30 #define CLKS_NR_PERI (CLK_GOUT_BUSIF_TMU_PCLK + 1)
31 #define CLKS_NR_CORE (CLK_GOUT_SPDMA_CORE_ACLK + 1)
32 #define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_PCLK + 1)
33
34 /* ---- CMU_TOP ------------------------------------------------------------- */
35
36 /* Register Offset definitions for CMU_TOP (0x120e0000) */
37 #define PLL_LOCKTIME_PLL_MMC 0x0000
38 #define PLL_LOCKTIME_PLL_SHARED0 0x0004
39 #define PLL_LOCKTIME_PLL_SHARED1 0x0008
40 #define PLL_CON0_PLL_MMC 0x0100
41 #define PLL_CON3_PLL_MMC 0x010c
42 #define PLL_CON0_PLL_SHARED0 0x0140
43 #define PLL_CON3_PLL_SHARED0 0x014c
44 #define PLL_CON0_PLL_SHARED1 0x0180
45 #define PLL_CON3_PLL_SHARED1 0x018c
46 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000
47 #define CLK_CON_MUX_MUX_CLKCMU_AUD 0x1004
48 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
49 #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
50 #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
51 #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020
52 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x1024
53 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1028
54 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG 0x102c
55 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1030
56 #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034
57 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038
58 #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
59 #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040
60 #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044
61 #define CLK_CON_MUX_MUX_CLKCMU_IS_BUS 0x1048
62 #define CLK_CON_MUX_MUX_CLKCMU_IS_GDC 0x104c
63 #define CLK_CON_MUX_MUX_CLKCMU_IS_ITP 0x1050
64 #define CLK_CON_MUX_MUX_CLKCMU_IS_VRA 0x1054
65 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG 0x1058
66 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M 0x105c
67 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC 0x1060
68 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC 0x1064
69 #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
70 #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
71 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
72 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c
73 #define CLK_CON_DIV_CLKCMU_AUD 0x1810
74 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820
75 #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
76 #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
77 #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c
78 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1830
79 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1834
80 #define CLK_CON_DIV_CLKCMU_CPUCL1_DBG 0x1838
81 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
82 #define CLK_CON_DIV_CLKCMU_DPU 0x1840
83 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844
84 #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
85 #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c
86 #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850
87 #define CLK_CON_DIV_CLKCMU_IS_BUS 0x1854
88 #define CLK_CON_DIV_CLKCMU_IS_GDC 0x1858
89 #define CLK_CON_DIV_CLKCMU_IS_ITP 0x185c
90 #define CLK_CON_DIV_CLKCMU_IS_VRA 0x1860
91 #define CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG 0x1864
92 #define CLK_CON_DIV_CLKCMU_MFCMSCL_M2M 0x1868
93 #define CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC 0x186c
94 #define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC 0x1870
95 #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c
96 #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
97 #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
98 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c
99 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890
100 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894
101 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898
102 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
103 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
104 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008
105 #define CLK_CON_GAT_GATE_CLKCMU_AUD 0x200c
106 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
107 #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
108 #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
109 #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028
110 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG 0x202c
111 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2030
112 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG 0x2034
113 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2038
114 #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c
115 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040
116 #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
117 #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048
118 #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c
119 #define CLK_CON_GAT_GATE_CLKCMU_IS_BUS 0x2050
120 #define CLK_CON_GAT_GATE_CLKCMU_IS_GDC 0x2054
121 #define CLK_CON_GAT_GATE_CLKCMU_IS_ITP 0x2058
122 #define CLK_CON_GAT_GATE_CLKCMU_IS_VRA 0x205c
123 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG 0x2060
124 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M 0x2064
125 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC 0x2068
126 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC 0x206c
127 #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
128 #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084
129 #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
130
131 static const unsigned long top_clk_regs[] __initconst = {
132 PLL_LOCKTIME_PLL_MMC,
133 PLL_LOCKTIME_PLL_SHARED0,
134 PLL_LOCKTIME_PLL_SHARED1,
135 PLL_CON0_PLL_MMC,
136 PLL_CON3_PLL_MMC,
137 PLL_CON0_PLL_SHARED0,
138 PLL_CON3_PLL_SHARED0,
139 PLL_CON0_PLL_SHARED1,
140 PLL_CON3_PLL_SHARED1,
141 CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
142 CLK_CON_MUX_MUX_CLKCMU_AUD,
143 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
144 CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
145 CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
146 CLK_CON_MUX_MUX_CLKCMU_CORE_SSS,
147 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
148 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
149 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG,
150 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
151 CLK_CON_MUX_MUX_CLKCMU_DPU,
152 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
153 CLK_CON_MUX_MUX_CLKCMU_HSI_BUS,
154 CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD,
155 CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD,
156 CLK_CON_MUX_MUX_CLKCMU_IS_BUS,
157 CLK_CON_MUX_MUX_CLKCMU_IS_GDC,
158 CLK_CON_MUX_MUX_CLKCMU_IS_ITP,
159 CLK_CON_MUX_MUX_CLKCMU_IS_VRA,
160 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG,
161 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M,
162 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC,
163 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC,
164 CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
165 CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
166 CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
167 CLK_CON_DIV_CLKCMU_APM_BUS,
168 CLK_CON_DIV_CLKCMU_AUD,
169 CLK_CON_DIV_CLKCMU_CORE_BUS,
170 CLK_CON_DIV_CLKCMU_CORE_CCI,
171 CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
172 CLK_CON_DIV_CLKCMU_CORE_SSS,
173 CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
174 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
175 CLK_CON_DIV_CLKCMU_CPUCL1_DBG,
176 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
177 CLK_CON_DIV_CLKCMU_DPU,
178 CLK_CON_DIV_CLKCMU_G3D_SWITCH,
179 CLK_CON_DIV_CLKCMU_HSI_BUS,
180 CLK_CON_DIV_CLKCMU_HSI_MMC_CARD,
181 CLK_CON_DIV_CLKCMU_HSI_USB20DRD,
182 CLK_CON_DIV_CLKCMU_IS_BUS,
183 CLK_CON_DIV_CLKCMU_IS_GDC,
184 CLK_CON_DIV_CLKCMU_IS_ITP,
185 CLK_CON_DIV_CLKCMU_IS_VRA,
186 CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG,
187 CLK_CON_DIV_CLKCMU_MFCMSCL_M2M,
188 CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC,
189 CLK_CON_DIV_CLKCMU_MFCMSCL_MFC,
190 CLK_CON_DIV_CLKCMU_PERI_BUS,
191 CLK_CON_DIV_CLKCMU_PERI_IP,
192 CLK_CON_DIV_CLKCMU_PERI_UART,
193 CLK_CON_DIV_PLL_SHARED0_DIV2,
194 CLK_CON_DIV_PLL_SHARED0_DIV3,
195 CLK_CON_DIV_PLL_SHARED0_DIV4,
196 CLK_CON_DIV_PLL_SHARED1_DIV2,
197 CLK_CON_DIV_PLL_SHARED1_DIV3,
198 CLK_CON_DIV_PLL_SHARED1_DIV4,
199 CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
200 CLK_CON_GAT_GATE_CLKCMU_AUD,
201 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
202 CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
203 CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
204 CLK_CON_GAT_GATE_CLKCMU_CORE_SSS,
205 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG,
206 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
207 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG,
208 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
209 CLK_CON_GAT_GATE_CLKCMU_DPU,
210 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
211 CLK_CON_GAT_GATE_CLKCMU_HSI_BUS,
212 CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD,
213 CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD,
214 CLK_CON_GAT_GATE_CLKCMU_IS_BUS,
215 CLK_CON_GAT_GATE_CLKCMU_IS_GDC,
216 CLK_CON_GAT_GATE_CLKCMU_IS_ITP,
217 CLK_CON_GAT_GATE_CLKCMU_IS_VRA,
218 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG,
219 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M,
220 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC,
221 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC,
222 CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
223 CLK_CON_GAT_GATE_CLKCMU_PERI_IP,
224 CLK_CON_GAT_GATE_CLKCMU_PERI_UART,
225 };
226
227 /*
228 * Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not set
229 * for those PLLs by default, so set_rate operation would fail.
230 */
231 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
232 /* CMU_TOP_PURECLKCOMP */
233 PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
234 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
235 NULL),
236 PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
237 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1,
238 NULL),
239 PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
240 PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
241 };
242
243 /* List of parent clocks for Muxes in CMU_TOP */
244 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
245 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
246 PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
247 /* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */
248 PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" };
249 /* List of parent clocks for Muxes in CMU_TOP: for CMU_AUD */
250 PNAME(mout_aud_p) = { "fout_shared1_pll", "dout_shared0_div2",
251 "dout_shared1_div2", "dout_shared0_div3" };
252 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
253 PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3",
254 "dout_shared1_div3", "dout_shared0_div4" };
255 PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2",
256 "dout_shared0_div3", "dout_shared1_div3" };
257 PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2",
258 "dout_shared1_div2", "dout_shared0_div3",
259 "dout_shared1_div3", "mout_mmc_pll",
260 "oscclk", "oscclk" };
261 PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3",
262 "dout_shared0_div4", "dout_shared1_div4" };
263 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL0 */
264 PNAME(mout_cpucl0_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
265 "dout_shared0_div2", "dout_shared1_div2" };
266 PNAME(mout_cpucl0_dbg_p) = { "dout_shared0_div4", "dout_shared1_div4" };
267 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL1 */
268 PNAME(mout_cpucl1_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
269 "dout_shared0_div2", "dout_shared1_div2" };
270 PNAME(mout_cpucl1_dbg_p) = { "dout_shared0_div4", "dout_shared1_div4" };
271 /* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
272 PNAME(mout_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
273 "dout_shared0_div3", "dout_shared1_div3" };
274 /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */
275 PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" };
276 PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2",
277 "dout_shared1_div2", "dout_shared0_div3",
278 "dout_shared1_div3", "mout_mmc_pll",
279 "oscclk", "oscclk" };
280 PNAME(mout_hsi_usb20drd_p) = { "oscclk", "dout_shared0_div4",
281 "dout_shared1_div4", "oscclk" };
282 /* List of parent clocks for Muxes in CMU_TOP: for CMU_IS */
283 PNAME(mout_is_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
284 "dout_shared0_div3", "dout_shared1_div3" };
285 PNAME(mout_is_itp_p) = { "dout_shared0_div2", "dout_shared1_div2",
286 "dout_shared0_div3", "dout_shared1_div3" };
287 PNAME(mout_is_vra_p) = { "dout_shared0_div2", "dout_shared1_div2",
288 "dout_shared0_div3", "dout_shared1_div3" };
289 PNAME(mout_is_gdc_p) = { "dout_shared0_div2", "dout_shared1_div2",
290 "dout_shared0_div3", "dout_shared1_div3" };
291 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MFCMSCL */
292 PNAME(mout_mfcmscl_mfc_p) = { "dout_shared1_div2", "dout_shared0_div3",
293 "dout_shared1_div3", "dout_shared0_div4" };
294 PNAME(mout_mfcmscl_m2m_p) = { "dout_shared1_div2", "dout_shared0_div3",
295 "dout_shared1_div3", "dout_shared0_div4" };
296 PNAME(mout_mfcmscl_mcsc_p) = { "dout_shared1_div2", "dout_shared0_div3",
297 "dout_shared1_div3", "dout_shared0_div4" };
298 PNAME(mout_mfcmscl_jpeg_p) = { "dout_shared0_div3", "dout_shared1_div3",
299 "dout_shared0_div4", "dout_shared1_div4" };
300 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
301 PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
302 PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4",
303 "dout_shared1_div4", "oscclk" };
304 PNAME(mout_peri_ip_p) = { "oscclk", "dout_shared0_div4",
305 "dout_shared1_div4", "oscclk" };
306 /* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */
307 PNAME(mout_dpu_p) = { "dout_shared0_div3", "dout_shared1_div3",
308 "dout_shared0_div4", "dout_shared1_div4" };
309
310 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
311 /* CMU_TOP_PURECLKCOMP */
312 MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
313 PLL_CON0_PLL_SHARED0, 4, 1),
314 MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
315 PLL_CON0_PLL_SHARED1, 4, 1),
316 MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
317 PLL_CON0_PLL_MMC, 4, 1),
318
319 /* APM */
320 MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus",
321 mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
322
323 /* AUD */
324 MUX(CLK_MOUT_AUD, "mout_aud", mout_aud_p,
325 CLK_CON_MUX_MUX_CLKCMU_AUD, 0, 2),
326
327 /* CORE */
328 MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
329 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
330 MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p,
331 CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
332 MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p,
333 CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3),
334 MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p,
335 CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2),
336
337 /* CPUCL0 */
338 MUX(CLK_MOUT_CPUCL0_DBG, "mout_cpucl0_dbg", mout_cpucl0_dbg_p,
339 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, 0, 1),
340 MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cpucl0_switch", mout_cpucl0_switch_p,
341 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
342
343 /* CPUCL1 */
344 MUX(CLK_MOUT_CPUCL1_DBG, "mout_cpucl1_dbg", mout_cpucl1_dbg_p,
345 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG, 0, 1),
346 MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cpucl1_switch", mout_cpucl1_switch_p,
347 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
348
349 /* DPU */
350 MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p,
351 CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2),
352
353 /* G3D */
354 MUX(CLK_MOUT_G3D_SWITCH, "mout_g3d_switch", mout_g3d_switch_p,
355 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
356
357 /* HSI */
358 MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p,
359 CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1),
360 MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p,
361 CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3),
362 MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p,
363 CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2),
364
365 /* IS */
366 MUX(CLK_MOUT_IS_BUS, "mout_is_bus", mout_is_bus_p,
367 CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 0, 2),
368 MUX(CLK_MOUT_IS_ITP, "mout_is_itp", mout_is_itp_p,
369 CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 0, 2),
370 MUX(CLK_MOUT_IS_VRA, "mout_is_vra", mout_is_vra_p,
371 CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 0, 2),
372 MUX(CLK_MOUT_IS_GDC, "mout_is_gdc", mout_is_gdc_p,
373 CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 0, 2),
374
375 /* MFCMSCL */
376 MUX(CLK_MOUT_MFCMSCL_MFC, "mout_mfcmscl_mfc", mout_mfcmscl_mfc_p,
377 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 0, 2),
378 MUX(CLK_MOUT_MFCMSCL_M2M, "mout_mfcmscl_m2m", mout_mfcmscl_m2m_p,
379 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M, 0, 2),
380 MUX(CLK_MOUT_MFCMSCL_MCSC, "mout_mfcmscl_mcsc", mout_mfcmscl_mcsc_p,
381 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC, 0, 2),
382 MUX(CLK_MOUT_MFCMSCL_JPEG, "mout_mfcmscl_jpeg", mout_mfcmscl_jpeg_p,
383 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG, 0, 2),
384
385 /* PERI */
386 MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
387 CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
388 MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p,
389 CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2),
390 MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p,
391 CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2),
392 };
393
394 static const struct samsung_div_clock top_div_clks[] __initconst = {
395 /* CMU_TOP_PURECLKCOMP */
396 DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
397 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
398 DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
399 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
400 DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
401 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
402 DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
403 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
404 DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
405 CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
406 DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
407 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
408
409 /* APM */
410 DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus",
411 "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
412
413 /* AUD */
414 DIV(CLK_DOUT_AUD, "dout_aud", "gout_aud",
415 CLK_CON_DIV_CLKCMU_AUD, 0, 4),
416
417 /* CORE */
418 DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
419 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
420 DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci",
421 CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4),
422 DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd",
423 CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9),
424 DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss",
425 CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4),
426
427 /* CPUCL0 */
428 DIV(CLK_DOUT_CPUCL0_DBG, "dout_cpucl0_dbg", "gout_cpucl0_dbg",
429 CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3),
430 DIV(CLK_DOUT_CPUCL0_SWITCH, "dout_cpucl0_switch", "gout_cpucl0_switch",
431 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
432
433 /* CPUCL1 */
434 DIV(CLK_DOUT_CPUCL1_DBG, "dout_cpucl1_dbg", "gout_cpucl1_dbg",
435 CLK_CON_DIV_CLKCMU_CPUCL1_DBG, 0, 3),
436 DIV(CLK_DOUT_CPUCL1_SWITCH, "dout_cpucl1_switch", "gout_cpucl1_switch",
437 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
438
439 /* DPU */
440 DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu",
441 CLK_CON_DIV_CLKCMU_DPU, 0, 4),
442
443 /* G3D */
444 DIV(CLK_DOUT_G3D_SWITCH, "dout_g3d_switch", "gout_g3d_switch",
445 CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
446
447 /* HSI */
448 DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus",
449 CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4),
450 DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card",
451 CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9),
452 DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd",
453 CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4),
454
455 /* IS */
456 DIV(CLK_DOUT_IS_BUS, "dout_is_bus", "gout_is_bus",
457 CLK_CON_DIV_CLKCMU_IS_BUS, 0, 4),
458 DIV(CLK_DOUT_IS_ITP, "dout_is_itp", "gout_is_itp",
459 CLK_CON_DIV_CLKCMU_IS_ITP, 0, 4),
460 DIV(CLK_DOUT_IS_VRA, "dout_is_vra", "gout_is_vra",
461 CLK_CON_DIV_CLKCMU_IS_VRA, 0, 4),
462 DIV(CLK_DOUT_IS_GDC, "dout_is_gdc", "gout_is_gdc",
463 CLK_CON_DIV_CLKCMU_IS_GDC, 0, 4),
464
465 /* MFCMSCL */
466 DIV(CLK_DOUT_MFCMSCL_MFC, "dout_mfcmscl_mfc", "gout_mfcmscl_mfc",
467 CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 0, 4),
468 DIV(CLK_DOUT_MFCMSCL_M2M, "dout_mfcmscl_m2m", "gout_mfcmscl_m2m",
469 CLK_CON_DIV_CLKCMU_MFCMSCL_M2M, 0, 4),
470 DIV(CLK_DOUT_MFCMSCL_MCSC, "dout_mfcmscl_mcsc", "gout_mfcmscl_mcsc",
471 CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC, 0, 4),
472 DIV(CLK_DOUT_MFCMSCL_JPEG, "dout_mfcmscl_jpeg", "gout_mfcmscl_jpeg",
473 CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG, 0, 4),
474
475 /* PERI */
476 DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
477 CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
478 DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart",
479 CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4),
480 DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip",
481 CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
482 };
483
484 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
485 /* CORE */
486 GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus",
487 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
488 GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci",
489 CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0),
490 GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd",
491 CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0),
492 GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss",
493 CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0),
494
495 /* APM */
496 GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus",
497 "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0),
498
499 /* AUD */
500 GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud",
501 CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0),
502
503 /* CPUCL0 */
504 GATE(CLK_GOUT_CPUCL0_DBG, "gout_cpucl0_dbg", "mout_cpucl0_dbg",
505 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG, 21, 0, 0),
506 GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cpucl0_switch", "mout_cpucl0_switch",
507 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, 0, 0),
508
509 /* CPUCL1 */
510 GATE(CLK_GOUT_CPUCL1_DBG, "gout_cpucl1_dbg", "mout_cpucl1_dbg",
511 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG, 21, 0, 0),
512 GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cpucl1_switch", "mout_cpucl1_switch",
513 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, 0, 0),
514
515 /* DPU */
516 GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
517 CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
518
519 /* G3D */
520 GATE(CLK_GOUT_G3D_SWITCH, "gout_g3d_switch", "mout_g3d_switch",
521 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
522
523 /* HSI */
524 GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus",
525 CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0),
526 GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card",
527 CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0),
528 GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd",
529 CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0),
530
531 /* IS */
532 /* TODO: These clocks have to be always enabled to access CMU_IS regs */
533 GATE(CLK_GOUT_IS_BUS, "gout_is_bus", "mout_is_bus",
534 CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 21, CLK_IS_CRITICAL, 0),
535 GATE(CLK_GOUT_IS_ITP, "gout_is_itp", "mout_is_itp",
536 CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 21, CLK_IS_CRITICAL, 0),
537 GATE(CLK_GOUT_IS_VRA, "gout_is_vra", "mout_is_vra",
538 CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 21, CLK_IS_CRITICAL, 0),
539 GATE(CLK_GOUT_IS_GDC, "gout_is_gdc", "mout_is_gdc",
540 CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 21, CLK_IS_CRITICAL, 0),
541
542 /* MFCMSCL */
543 /* TODO: These have to be always enabled to access CMU_MFCMSCL regs */
544 GATE(CLK_GOUT_MFCMSCL_MFC, "gout_mfcmscl_mfc", "mout_mfcmscl_mfc",
545 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 21, CLK_IS_CRITICAL, 0),
546 GATE(CLK_GOUT_MFCMSCL_M2M, "gout_mfcmscl_m2m", "mout_mfcmscl_m2m",
547 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M, 21, CLK_IS_CRITICAL, 0),
548 GATE(CLK_GOUT_MFCMSCL_MCSC, "gout_mfcmscl_mcsc", "mout_mfcmscl_mcsc",
549 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC, 21, CLK_IS_CRITICAL, 0),
550 GATE(CLK_GOUT_MFCMSCL_JPEG, "gout_mfcmscl_jpeg", "mout_mfcmscl_jpeg",
551 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG, 21, CLK_IS_CRITICAL, 0),
552
553 /* PERI */
554 GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
555 CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
556 GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart",
557 CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0),
558 GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip",
559 CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0),
560 };
561
562 static const struct samsung_cmu_info top_cmu_info __initconst = {
563 .pll_clks = top_pll_clks,
564 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
565 .mux_clks = top_mux_clks,
566 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
567 .div_clks = top_div_clks,
568 .nr_div_clks = ARRAY_SIZE(top_div_clks),
569 .gate_clks = top_gate_clks,
570 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
571 .nr_clk_ids = CLKS_NR_TOP,
572 .clk_regs = top_clk_regs,
573 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
574 };
575
exynos850_cmu_top_init(struct device_node * np)576 static void __init exynos850_cmu_top_init(struct device_node *np)
577 {
578 exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
579 }
580
581 /* Register CMU_TOP early, as it's a dependency for other early domains */
582 CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top",
583 exynos850_cmu_top_init);
584
585 /* ---- CMU_APM ------------------------------------------------------------- */
586
587 /* Register Offset definitions for CMU_APM (0x11800000) */
588 #define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600
589 #define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610
590 #define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620
591 #define PLL_CON0_MUX_DLL_USER 0x0630
592 #define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000
593 #define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004
594 #define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008
595 #define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800
596 #define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804
597 #define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808
598 #define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000
599 #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014
600 #define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018
601 #define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020
602 #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024
603 #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028
604 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034
605 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038
606 #define CLK_CON_GAT_GOUT_APM_MAILBOX_APM_AP_PCLK 0x2060
607 #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc
608 #define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0
609
610 static const unsigned long apm_clk_regs[] __initconst = {
611 PLL_CON0_MUX_CLKCMU_APM_BUS_USER,
612 PLL_CON0_MUX_CLK_RCO_APM_I3C_USER,
613 PLL_CON0_MUX_CLK_RCO_APM_USER,
614 PLL_CON0_MUX_DLL_USER,
615 CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS,
616 CLK_CON_MUX_MUX_CLK_APM_BUS,
617 CLK_CON_MUX_MUX_CLK_APM_I3C,
618 CLK_CON_DIV_CLKCMU_CHUB_BUS,
619 CLK_CON_DIV_DIV_CLK_APM_BUS,
620 CLK_CON_DIV_DIV_CLK_APM_I3C,
621 CLK_CON_GAT_CLKCMU_CMGP_BUS,
622 CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS,
623 CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK,
624 CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK,
625 CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK,
626 CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK,
627 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK,
628 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK,
629 CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK,
630 CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK,
631 CLK_CON_GAT_GOUT_APM_MAILBOX_APM_AP_PCLK,
632 };
633
634 /* List of parent clocks for Muxes in CMU_APM */
635 PNAME(mout_apm_bus_user_p) = { "oscclk_rco_apm", "dout_clkcmu_apm_bus" };
636 PNAME(mout_rco_apm_i3c_user_p) = { "oscclk_rco_apm", "clk_rco_i3c_pmic" };
637 PNAME(mout_rco_apm_user_p) = { "oscclk_rco_apm", "clk_rco_apm__alv" };
638 PNAME(mout_dll_user_p) = { "oscclk_rco_apm", "clk_dll_dco" };
639 PNAME(mout_clkcmu_chub_bus_p) = { "mout_apm_bus_user", "mout_dll_user" };
640 PNAME(mout_apm_bus_p) = { "mout_rco_apm_user", "mout_apm_bus_user",
641 "mout_dll_user", "oscclk_rco_apm" };
642 PNAME(mout_apm_i3c_p) = { "dout_apm_i3c", "mout_rco_apm_i3c_user" };
643
644 static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
645 FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000),
646 FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000),
647 FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000),
648 FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000),
649 };
650
651 static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
652 MUX(CLK_MOUT_APM_BUS_USER, "mout_apm_bus_user", mout_apm_bus_user_p,
653 PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1),
654 MUX(CLK_MOUT_RCO_APM_I3C_USER, "mout_rco_apm_i3c_user",
655 mout_rco_apm_i3c_user_p, PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 4, 1),
656 MUX(CLK_MOUT_RCO_APM_USER, "mout_rco_apm_user", mout_rco_apm_user_p,
657 PLL_CON0_MUX_CLK_RCO_APM_USER, 4, 1),
658 MUX(CLK_MOUT_DLL_USER, "mout_dll_user", mout_dll_user_p,
659 PLL_CON0_MUX_DLL_USER, 4, 1),
660 MUX(CLK_MOUT_CLKCMU_CHUB_BUS, "mout_clkcmu_chub_bus",
661 mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1),
662 MUX(CLK_MOUT_APM_BUS, "mout_apm_bus", mout_apm_bus_p,
663 CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2),
664 MUX(CLK_MOUT_APM_I3C, "mout_apm_i3c", mout_apm_i3c_p,
665 CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1),
666 };
667
668 static const struct samsung_div_clock apm_div_clks[] __initconst = {
669 DIV(CLK_DOUT_CLKCMU_CHUB_BUS, "dout_clkcmu_chub_bus",
670 "gout_clkcmu_chub_bus",
671 CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3),
672 DIV(CLK_DOUT_APM_BUS, "dout_apm_bus", "mout_apm_bus",
673 CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3),
674 DIV(CLK_DOUT_APM_I3C, "dout_apm_i3c", "mout_apm_bus",
675 CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3),
676 };
677
678 static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
679 GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus",
680 CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, CLK_SET_RATE_PARENT, 0),
681 GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus",
682 "mout_clkcmu_chub_bus",
683 CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0),
684 GATE(CLK_GOUT_RTC_PCLK, "gout_rtc_pclk", "dout_apm_bus",
685 CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0),
686 GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus",
687 CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0),
688 /* TODO: Should be dealt with or enabled in PMIC ACPM driver */
689 GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus",
690 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, CLK_IS_CRITICAL, 0),
691 GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c",
692 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, CLK_IS_CRITICAL, 0),
693 GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus",
694 CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0),
695 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
696 GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus",
697 CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED,
698 0),
699 GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus",
700 CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, CLK_IS_CRITICAL, 0),
701 GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus",
702 CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0),
703 GATE(CLK_GOUT_MAILBOX_APM_AP_PCLK, "gout_mailbox_apm_ap_pclk",
704 "dout_apm_func",
705 CLK_CON_GAT_GOUT_APM_MAILBOX_APM_AP_PCLK, 21, 0, 0),
706 };
707
708 static const struct samsung_cmu_info apm_cmu_info __initconst = {
709 .mux_clks = apm_mux_clks,
710 .nr_mux_clks = ARRAY_SIZE(apm_mux_clks),
711 .div_clks = apm_div_clks,
712 .nr_div_clks = ARRAY_SIZE(apm_div_clks),
713 .gate_clks = apm_gate_clks,
714 .nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
715 .fixed_clks = apm_fixed_clks,
716 .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
717 .nr_clk_ids = CLKS_NR_APM,
718 .clk_regs = apm_clk_regs,
719 .nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
720 .clk_name = "dout_clkcmu_apm_bus",
721 };
722
723 /* ---- CMU_AUD ------------------------------------------------------------- */
724
725 #define PLL_LOCKTIME_PLL_AUD 0x0000
726 #define PLL_CON0_PLL_AUD 0x0100
727 #define PLL_CON3_PLL_AUD 0x010c
728 #define PLL_CON0_MUX_CLKCMU_AUD_CPU_USER 0x0600
729 #define PLL_CON0_MUX_TICK_USB_USER 0x0610
730 #define CLK_CON_MUX_MUX_CLK_AUD_CPU 0x1000
731 #define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH 0x1004
732 #define CLK_CON_MUX_MUX_CLK_AUD_FM 0x1008
733 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF0 0x100c
734 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF1 0x1010
735 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF2 0x1014
736 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF3 0x1018
737 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF4 0x101c
738 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF5 0x1020
739 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF6 0x1024
740 #define CLK_CON_DIV_DIV_CLK_AUD_MCLK 0x1800
741 #define CLK_CON_DIV_DIV_CLK_AUD_AUDIF 0x1804
742 #define CLK_CON_DIV_DIV_CLK_AUD_BUSD 0x1808
743 #define CLK_CON_DIV_DIV_CLK_AUD_BUSP 0x180c
744 #define CLK_CON_DIV_DIV_CLK_AUD_CNT 0x1810
745 #define CLK_CON_DIV_DIV_CLK_AUD_CPU 0x1814
746 #define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK 0x1818
747 #define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG 0x181c
748 #define CLK_CON_DIV_DIV_CLK_AUD_FM 0x1820
749 #define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY 0x1824
750 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF0 0x1828
751 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF1 0x182c
752 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF2 0x1830
753 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF3 0x1834
754 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF4 0x1838
755 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF5 0x183c
756 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF6 0x1840
757 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT 0x2000
758 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0 0x2004
759 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1 0x2008
760 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2 0x200c
761 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3 0x2010
762 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014
763 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018
764 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c
765 #define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK 0x2020
766 #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048
767 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c
768 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050
769 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32 0x2054
770 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP 0x2058
771 #define CLK_CON_GAT_GOUT_AUD_CODEC_MCLK 0x206c
772 #define CLK_CON_GAT_GOUT_AUD_TZPC_PCLK 0x2070
773 #define CLK_CON_GAT_GOUT_AUD_GPIO_PCLK 0x2074
774 #define CLK_CON_GAT_GOUT_AUD_PPMU_ACLK 0x2088
775 #define CLK_CON_GAT_GOUT_AUD_PPMU_PCLK 0x208c
776 #define CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1 0x20b4
777 #define CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK 0x20b8
778 #define CLK_CON_GAT_GOUT_AUD_WDT_PCLK 0x20bc
779
780 static const unsigned long aud_clk_regs[] __initconst = {
781 PLL_LOCKTIME_PLL_AUD,
782 PLL_CON0_PLL_AUD,
783 PLL_CON3_PLL_AUD,
784 PLL_CON0_MUX_CLKCMU_AUD_CPU_USER,
785 PLL_CON0_MUX_TICK_USB_USER,
786 CLK_CON_MUX_MUX_CLK_AUD_CPU,
787 CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH,
788 CLK_CON_MUX_MUX_CLK_AUD_FM,
789 CLK_CON_MUX_MUX_CLK_AUD_UAIF0,
790 CLK_CON_MUX_MUX_CLK_AUD_UAIF1,
791 CLK_CON_MUX_MUX_CLK_AUD_UAIF2,
792 CLK_CON_MUX_MUX_CLK_AUD_UAIF3,
793 CLK_CON_MUX_MUX_CLK_AUD_UAIF4,
794 CLK_CON_MUX_MUX_CLK_AUD_UAIF5,
795 CLK_CON_MUX_MUX_CLK_AUD_UAIF6,
796 CLK_CON_DIV_DIV_CLK_AUD_MCLK,
797 CLK_CON_DIV_DIV_CLK_AUD_AUDIF,
798 CLK_CON_DIV_DIV_CLK_AUD_BUSD,
799 CLK_CON_DIV_DIV_CLK_AUD_BUSP,
800 CLK_CON_DIV_DIV_CLK_AUD_CNT,
801 CLK_CON_DIV_DIV_CLK_AUD_CPU,
802 CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK,
803 CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG,
804 CLK_CON_DIV_DIV_CLK_AUD_FM,
805 CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY,
806 CLK_CON_DIV_DIV_CLK_AUD_UAIF0,
807 CLK_CON_DIV_DIV_CLK_AUD_UAIF1,
808 CLK_CON_DIV_DIV_CLK_AUD_UAIF2,
809 CLK_CON_DIV_DIV_CLK_AUD_UAIF3,
810 CLK_CON_DIV_DIV_CLK_AUD_UAIF4,
811 CLK_CON_DIV_DIV_CLK_AUD_UAIF5,
812 CLK_CON_DIV_DIV_CLK_AUD_UAIF6,
813 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT,
814 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0,
815 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1,
816 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2,
817 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3,
818 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4,
819 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5,
820 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6,
821 CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK,
822 CLK_CON_GAT_GOUT_AUD_ABOX_ACLK,
823 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY,
824 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB,
825 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32,
826 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP,
827 CLK_CON_GAT_GOUT_AUD_CODEC_MCLK,
828 CLK_CON_GAT_GOUT_AUD_TZPC_PCLK,
829 CLK_CON_GAT_GOUT_AUD_GPIO_PCLK,
830 CLK_CON_GAT_GOUT_AUD_PPMU_ACLK,
831 CLK_CON_GAT_GOUT_AUD_PPMU_PCLK,
832 CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1,
833 CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK,
834 CLK_CON_GAT_GOUT_AUD_WDT_PCLK,
835 };
836
837 /* List of parent clocks for Muxes in CMU_AUD */
838 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll" };
839 PNAME(mout_aud_cpu_user_p) = { "oscclk", "dout_aud" };
840 PNAME(mout_aud_cpu_p) = { "dout_aud_cpu", "mout_aud_cpu_user" };
841 PNAME(mout_aud_cpu_hch_p) = { "mout_aud_cpu", "oscclk" };
842 PNAME(mout_aud_uaif0_p) = { "dout_aud_uaif0", "ioclk_audiocdclk0" };
843 PNAME(mout_aud_uaif1_p) = { "dout_aud_uaif1", "ioclk_audiocdclk1" };
844 PNAME(mout_aud_uaif2_p) = { "dout_aud_uaif2", "ioclk_audiocdclk2" };
845 PNAME(mout_aud_uaif3_p) = { "dout_aud_uaif3", "ioclk_audiocdclk3" };
846 PNAME(mout_aud_uaif4_p) = { "dout_aud_uaif4", "ioclk_audiocdclk4" };
847 PNAME(mout_aud_uaif5_p) = { "dout_aud_uaif5", "ioclk_audiocdclk5" };
848 PNAME(mout_aud_uaif6_p) = { "dout_aud_uaif6", "ioclk_audiocdclk6" };
849 PNAME(mout_aud_tick_usb_user_p) = { "oscclk", "tick_usb" };
850 PNAME(mout_aud_fm_p) = { "oscclk", "dout_aud_fm_spdy" };
851
852 /*
853 * Do not provide PLL table to PLL_AUD, as MANUAL_PLL_CTRL bit is not set
854 * for that PLL by default, so set_rate operation would fail.
855 */
856 static const struct samsung_pll_clock aud_pll_clks[] __initconst = {
857 PLL(pll_0831x, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
858 PLL_LOCKTIME_PLL_AUD, PLL_CON3_PLL_AUD, NULL),
859 };
860
861 static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
862 FRATE(IOCLK_AUDIOCDCLK0, "ioclk_audiocdclk0", NULL, 0, 25000000),
863 FRATE(IOCLK_AUDIOCDCLK1, "ioclk_audiocdclk1", NULL, 0, 25000000),
864 FRATE(IOCLK_AUDIOCDCLK2, "ioclk_audiocdclk2", NULL, 0, 25000000),
865 FRATE(IOCLK_AUDIOCDCLK3, "ioclk_audiocdclk3", NULL, 0, 25000000),
866 FRATE(IOCLK_AUDIOCDCLK4, "ioclk_audiocdclk4", NULL, 0, 25000000),
867 FRATE(IOCLK_AUDIOCDCLK5, "ioclk_audiocdclk5", NULL, 0, 25000000),
868 FRATE(IOCLK_AUDIOCDCLK6, "ioclk_audiocdclk6", NULL, 0, 25000000),
869 FRATE(TICK_USB, "tick_usb", NULL, 0, 60000000),
870 };
871
872 static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
873 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p,
874 PLL_CON0_PLL_AUD, 4, 1),
875 MUX(CLK_MOUT_AUD_CPU_USER, "mout_aud_cpu_user", mout_aud_cpu_user_p,
876 PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 4, 1),
877 MUX(CLK_MOUT_AUD_TICK_USB_USER, "mout_aud_tick_usb_user",
878 mout_aud_tick_usb_user_p,
879 PLL_CON0_MUX_TICK_USB_USER, 4, 1),
880 MUX(CLK_MOUT_AUD_CPU, "mout_aud_cpu", mout_aud_cpu_p,
881 CLK_CON_MUX_MUX_CLK_AUD_CPU, 0, 1),
882 MUX(CLK_MOUT_AUD_CPU_HCH, "mout_aud_cpu_hch", mout_aud_cpu_hch_p,
883 CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0, 1),
884 MUX(CLK_MOUT_AUD_UAIF0, "mout_aud_uaif0", mout_aud_uaif0_p,
885 CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0, 1),
886 MUX(CLK_MOUT_AUD_UAIF1, "mout_aud_uaif1", mout_aud_uaif1_p,
887 CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0, 1),
888 MUX(CLK_MOUT_AUD_UAIF2, "mout_aud_uaif2", mout_aud_uaif2_p,
889 CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0, 1),
890 MUX(CLK_MOUT_AUD_UAIF3, "mout_aud_uaif3", mout_aud_uaif3_p,
891 CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0, 1),
892 MUX(CLK_MOUT_AUD_UAIF4, "mout_aud_uaif4", mout_aud_uaif4_p,
893 CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0, 1),
894 MUX(CLK_MOUT_AUD_UAIF5, "mout_aud_uaif5", mout_aud_uaif5_p,
895 CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0, 1),
896 MUX(CLK_MOUT_AUD_UAIF6, "mout_aud_uaif6", mout_aud_uaif6_p,
897 CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0, 1),
898 MUX(CLK_MOUT_AUD_FM, "mout_aud_fm", mout_aud_fm_p,
899 CLK_CON_MUX_MUX_CLK_AUD_FM, 0, 1),
900 };
901
902 static const struct samsung_div_clock aud_div_clks[] __initconst = {
903 DIV(CLK_DOUT_AUD_CPU, "dout_aud_cpu", "mout_aud_pll",
904 CLK_CON_DIV_DIV_CLK_AUD_CPU, 0, 4),
905 DIV(CLK_DOUT_AUD_BUSD, "dout_aud_busd", "mout_aud_pll",
906 CLK_CON_DIV_DIV_CLK_AUD_BUSD, 0, 4),
907 DIV(CLK_DOUT_AUD_BUSP, "dout_aud_busp", "mout_aud_pll",
908 CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0, 4),
909 DIV(CLK_DOUT_AUD_AUDIF, "dout_aud_audif", "mout_aud_pll",
910 CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0, 9),
911 DIV(CLK_DOUT_AUD_CPU_ACLK, "dout_aud_cpu_aclk", "mout_aud_cpu_hch",
912 CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0, 3),
913 DIV(CLK_DOUT_AUD_CPU_PCLKDBG, "dout_aud_cpu_pclkdbg",
914 "mout_aud_cpu_hch",
915 CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0, 3),
916 DIV(CLK_DOUT_AUD_MCLK, "dout_aud_mclk", "dout_aud_audif",
917 CLK_CON_DIV_DIV_CLK_AUD_MCLK, 0, 2),
918 DIV(CLK_DOUT_AUD_CNT, "dout_aud_cnt", "dout_aud_audif",
919 CLK_CON_DIV_DIV_CLK_AUD_CNT, 0, 10),
920 DIV(CLK_DOUT_AUD_UAIF0, "dout_aud_uaif0", "dout_aud_audif",
921 CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0, 10),
922 DIV(CLK_DOUT_AUD_UAIF1, "dout_aud_uaif1", "dout_aud_audif",
923 CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0, 10),
924 DIV(CLK_DOUT_AUD_UAIF2, "dout_aud_uaif2", "dout_aud_audif",
925 CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0, 10),
926 DIV(CLK_DOUT_AUD_UAIF3, "dout_aud_uaif3", "dout_aud_audif",
927 CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0, 10),
928 DIV(CLK_DOUT_AUD_UAIF4, "dout_aud_uaif4", "dout_aud_audif",
929 CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0, 10),
930 DIV(CLK_DOUT_AUD_UAIF5, "dout_aud_uaif5", "dout_aud_audif",
931 CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0, 10),
932 DIV(CLK_DOUT_AUD_UAIF6, "dout_aud_uaif6", "dout_aud_audif",
933 CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0, 10),
934 DIV(CLK_DOUT_AUD_FM_SPDY, "dout_aud_fm_spdy", "mout_aud_tick_usb_user",
935 CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0, 1),
936 DIV(CLK_DOUT_AUD_FM, "dout_aud_fm", "mout_aud_fm",
937 CLK_CON_DIV_DIV_CLK_AUD_FM, 0, 10),
938 };
939
940 static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
941 GATE(CLK_GOUT_AUD_CMU_AUD_PCLK, "gout_aud_cmu_aud_pclk",
942 "dout_aud_busd",
943 CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 21, CLK_IGNORE_UNUSED, 0),
944 GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch",
945 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0),
946 GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk",
947 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 21, 0, 0),
948 GATE(CLK_GOUT_AUD_DAP_CCLK, "gout_aud_dap_cclk", "dout_aud_cpu_pclkdbg",
949 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 21, 0, 0),
950 /* TODO: Should be enabled in ABOX driver (or made CLK_IS_CRITICAL) */
951 GATE(CLK_GOUT_AUD_ABOX_ACLK, "gout_aud_abox_aclk", "dout_aud_busd",
952 CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0),
953 GATE(CLK_GOUT_AUD_GPIO_PCLK, "gout_aud_gpio_pclk", "dout_aud_busd",
954 CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 21, 0, 0),
955 GATE(CLK_GOUT_AUD_PPMU_ACLK, "gout_aud_ppmu_aclk", "dout_aud_busd",
956 CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 21, 0, 0),
957 GATE(CLK_GOUT_AUD_PPMU_PCLK, "gout_aud_ppmu_pclk", "dout_aud_busd",
958 CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 21, 0, 0),
959 GATE(CLK_GOUT_AUD_SYSMMU_CLK, "gout_aud_sysmmu_clk", "dout_aud_busd",
960 CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 21, 0, 0),
961 GATE(CLK_GOUT_AUD_SYSREG_PCLK, "gout_aud_sysreg_pclk", "dout_aud_busd",
962 CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 21, 0, 0),
963 GATE(CLK_GOUT_AUD_WDT_PCLK, "gout_aud_wdt_pclk", "dout_aud_busd",
964 CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 21, 0, 0),
965 GATE(CLK_GOUT_AUD_TZPC_PCLK, "gout_aud_tzpc_pclk", "dout_aud_busp",
966 CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 21, 0, 0),
967 GATE(CLK_GOUT_AUD_CODEC_MCLK, "gout_aud_codec_mclk", "dout_aud_mclk",
968 CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 21, 0, 0),
969 GATE(CLK_GOUT_AUD_CNT_BCLK, "gout_aud_cnt_bclk", "dout_aud_cnt",
970 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 21, 0, 0),
971 GATE(CLK_GOUT_AUD_UAIF0_BCLK, "gout_aud_uaif0_bclk", "mout_aud_uaif0",
972 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 21, 0, 0),
973 GATE(CLK_GOUT_AUD_UAIF1_BCLK, "gout_aud_uaif1_bclk", "mout_aud_uaif1",
974 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 21, 0, 0),
975 GATE(CLK_GOUT_AUD_UAIF2_BCLK, "gout_aud_uaif2_bclk", "mout_aud_uaif2",
976 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 21, 0, 0),
977 GATE(CLK_GOUT_AUD_UAIF3_BCLK, "gout_aud_uaif3_bclk", "mout_aud_uaif3",
978 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 21, 0, 0),
979 GATE(CLK_GOUT_AUD_UAIF4_BCLK, "gout_aud_uaif4_bclk", "mout_aud_uaif4",
980 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 21, 0, 0),
981 GATE(CLK_GOUT_AUD_UAIF5_BCLK, "gout_aud_uaif5_bclk", "mout_aud_uaif5",
982 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 21, 0, 0),
983 GATE(CLK_GOUT_AUD_UAIF6_BCLK, "gout_aud_uaif6_bclk", "mout_aud_uaif6",
984 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 21, 0, 0),
985 GATE(CLK_GOUT_AUD_SPDY_BCLK, "gout_aud_spdy_bclk", "dout_aud_fm",
986 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 21, 0, 0),
987 };
988
989 static const struct samsung_cmu_info aud_cmu_info __initconst = {
990 .pll_clks = aud_pll_clks,
991 .nr_pll_clks = ARRAY_SIZE(aud_pll_clks),
992 .mux_clks = aud_mux_clks,
993 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
994 .div_clks = aud_div_clks,
995 .nr_div_clks = ARRAY_SIZE(aud_div_clks),
996 .gate_clks = aud_gate_clks,
997 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
998 .fixed_clks = aud_fixed_clks,
999 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
1000 .nr_clk_ids = CLKS_NR_AUD,
1001 .clk_regs = aud_clk_regs,
1002 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
1003 .clk_name = "dout_aud",
1004 };
1005
1006 /* ---- CMU_CMGP ------------------------------------------------------------ */
1007
1008 /* Register Offset definitions for CMU_CMGP (0x11c00000) */
1009 #define CLK_CON_MUX_CLK_CMGP_ADC 0x1000
1010 #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004
1011 #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008
1012 #define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800
1013 #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804
1014 #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808
1015 #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c
1016 #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010
1017 #define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018
1018 #define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040
1019 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044
1020 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048
1021 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c
1022 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050
1023
1024 static const unsigned long cmgp_clk_regs[] __initconst = {
1025 CLK_CON_MUX_CLK_CMGP_ADC,
1026 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0,
1027 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1,
1028 CLK_CON_DIV_DIV_CLK_CMGP_ADC,
1029 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0,
1030 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1,
1031 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0,
1032 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1,
1033 CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK,
1034 CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK,
1035 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK,
1036 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK,
1037 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK,
1038 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK,
1039 };
1040
1041 /* List of parent clocks for Muxes in CMU_CMGP */
1042 PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
1043 PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
1044 PNAME(mout_cmgp_adc_p) = { "oscclk", "dout_cmgp_adc" };
1045
1046 static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = {
1047 FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000),
1048 };
1049
1050 static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = {
1051 MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p,
1052 CLK_CON_MUX_CLK_CMGP_ADC, 0, 1),
1053 MUX_F(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p,
1054 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1, CLK_SET_RATE_PARENT, 0),
1055 MUX_F(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p,
1056 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1, CLK_SET_RATE_PARENT, 0),
1057 };
1058
1059 static const struct samsung_div_clock cmgp_div_clks[] __initconst = {
1060 DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus",
1061 CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4),
1062 DIV_F(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0",
1063 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5, CLK_SET_RATE_PARENT, 0),
1064 DIV_F(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1",
1065 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5, CLK_SET_RATE_PARENT, 0),
1066 };
1067
1068 static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = {
1069 GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk",
1070 "gout_clkcmu_cmgp_bus",
1071 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0),
1072 GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk",
1073 "gout_clkcmu_cmgp_bus",
1074 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0),
1075 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
1076 GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk",
1077 "gout_clkcmu_cmgp_bus",
1078 CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1079 GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0",
1080 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, CLK_SET_RATE_PARENT, 0),
1081 GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk",
1082 "gout_clkcmu_cmgp_bus",
1083 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0),
1084 GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1",
1085 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, CLK_SET_RATE_PARENT, 0),
1086 GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk",
1087 "gout_clkcmu_cmgp_bus",
1088 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0),
1089 GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk",
1090 "gout_clkcmu_cmgp_bus",
1091 CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0),
1092 };
1093
1094 static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
1095 .mux_clks = cmgp_mux_clks,
1096 .nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks),
1097 .div_clks = cmgp_div_clks,
1098 .nr_div_clks = ARRAY_SIZE(cmgp_div_clks),
1099 .gate_clks = cmgp_gate_clks,
1100 .nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks),
1101 .fixed_clks = cmgp_fixed_clks,
1102 .nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks),
1103 .nr_clk_ids = CLKS_NR_CMGP,
1104 .clk_regs = cmgp_clk_regs,
1105 .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs),
1106 .clk_name = "gout_clkcmu_cmgp_bus",
1107 };
1108
1109 /* ---- CMU_CPUCL0 ---------------------------------------------------------- */
1110
1111 /* Register Offset definitions for CMU_CPUCL0 (0x10900000) */
1112 #define PLL_LOCKTIME_PLL_CPUCL0 0x0000
1113 #define PLL_CON0_PLL_CPUCL0 0x0100
1114 #define PLL_CON1_PLL_CPUCL0 0x0104
1115 #define PLL_CON3_PLL_CPUCL0 0x010c
1116 #define PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER 0x0600
1117 #define PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER 0x0610
1118 #define CLK_CON_MUX_MUX_CLK_CPUCL0_PLL 0x100c
1119 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK 0x1800
1120 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK 0x1808
1121 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG 0x180c
1122 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK 0x1810
1123 #define CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF 0x1814
1124 #define CLK_CON_DIV_DIV_CLK_CPUCL0_CPU 0x1818
1125 #define CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK 0x181c
1126 #define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK 0x2000
1127 #define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK 0x2004
1128 #define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK 0x2008
1129 #define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK 0x200c
1130 #define CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK 0x2010
1131 #define CLK_CON_GAT_GATE_CLK_CPUCL0_CPU 0x2020
1132
1133 static const unsigned long cpucl0_clk_regs[] __initconst = {
1134 PLL_LOCKTIME_PLL_CPUCL0,
1135 PLL_CON0_PLL_CPUCL0,
1136 PLL_CON1_PLL_CPUCL0,
1137 PLL_CON3_PLL_CPUCL0,
1138 PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER,
1139 PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER,
1140 CLK_CON_MUX_MUX_CLK_CPUCL0_PLL,
1141 CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK,
1142 CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK,
1143 CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG,
1144 CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK,
1145 CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF,
1146 CLK_CON_DIV_DIV_CLK_CPUCL0_CPU,
1147 CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK,
1148 CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK,
1149 CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK,
1150 CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK,
1151 CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK,
1152 CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK,
1153 CLK_CON_GAT_GATE_CLK_CPUCL0_CPU,
1154 };
1155
1156 /* List of parent clocks for Muxes in CMU_CPUCL0 */
1157 PNAME(mout_pll_cpucl0_p) = { "oscclk", "fout_cpucl0_pll" };
1158 PNAME(mout_cpucl0_switch_user_p) = { "oscclk", "dout_cpucl0_switch" };
1159 PNAME(mout_cpucl0_dbg_user_p) = { "oscclk", "dout_cpucl0_dbg" };
1160 PNAME(mout_cpucl0_pll_p) = { "mout_pll_cpucl0",
1161 "mout_cpucl0_switch_user" };
1162
1163 static const struct samsung_pll_rate_table cpu_pll_rates[] __initconst = {
1164 PLL_35XX_RATE(26 * MHZ, 2210000000U, 255, 3, 0),
1165 PLL_35XX_RATE(26 * MHZ, 2106000000U, 243, 3, 0),
1166 PLL_35XX_RATE(26 * MHZ, 2002000000U, 231, 3, 0),
1167 PLL_35XX_RATE(26 * MHZ, 1846000000U, 213, 3, 0),
1168 PLL_35XX_RATE(26 * MHZ, 1742000000U, 201, 3, 0),
1169 PLL_35XX_RATE(26 * MHZ, 1586000000U, 183, 3, 0),
1170 PLL_35XX_RATE(26 * MHZ, 1456000000U, 168, 3, 0),
1171 PLL_35XX_RATE(26 * MHZ, 1300000000U, 150, 3, 0),
1172 PLL_35XX_RATE(26 * MHZ, 1157000000U, 267, 3, 1),
1173 PLL_35XX_RATE(26 * MHZ, 1053000000U, 243, 3, 1),
1174 PLL_35XX_RATE(26 * MHZ, 949000000U, 219, 3, 1),
1175 PLL_35XX_RATE(26 * MHZ, 806000000U, 186, 3, 1),
1176 PLL_35XX_RATE(26 * MHZ, 650000000U, 150, 3, 1),
1177 PLL_35XX_RATE(26 * MHZ, 546000000U, 252, 3, 2),
1178 PLL_35XX_RATE(26 * MHZ, 442000000U, 204, 3, 2),
1179 PLL_35XX_RATE(26 * MHZ, 351000000U, 162, 3, 2),
1180 PLL_35XX_RATE(26 * MHZ, 247000000U, 114, 3, 2),
1181 PLL_35XX_RATE(26 * MHZ, 182000000U, 168, 3, 3),
1182 PLL_35XX_RATE(26 * MHZ, 130000000U, 120, 3, 3),
1183 };
1184
1185 static const struct samsung_pll_clock cpucl0_pll_clks[] __initconst = {
1186 PLL(pll_0822x, CLK_FOUT_CPUCL0_PLL, "fout_cpucl0_pll", "oscclk",
1187 PLL_LOCKTIME_PLL_CPUCL0, PLL_CON3_PLL_CPUCL0, cpu_pll_rates),
1188 };
1189
1190 static const struct samsung_mux_clock cpucl0_mux_clks[] __initconst = {
1191 MUX_F(CLK_MOUT_PLL_CPUCL0, "mout_pll_cpucl0", mout_pll_cpucl0_p,
1192 PLL_CON0_PLL_CPUCL0, 4, 1,
1193 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
1194 MUX_F(CLK_MOUT_CPUCL0_SWITCH_USER, "mout_cpucl0_switch_user",
1195 mout_cpucl0_switch_user_p,
1196 PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 4, 1,
1197 CLK_SET_RATE_PARENT, 0),
1198 MUX(CLK_MOUT_CPUCL0_DBG_USER, "mout_cpucl0_dbg_user",
1199 mout_cpucl0_dbg_user_p,
1200 PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER, 4, 1),
1201 MUX_F(CLK_MOUT_CPUCL0_PLL, "mout_cpucl0_pll", mout_cpucl0_pll_p,
1202 CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
1203 };
1204
1205 static const struct samsung_div_clock cpucl0_div_clks[] __initconst = {
1206 DIV_F(CLK_DOUT_CPUCL0_CPU, "dout_cpucl0_cpu", "mout_cpucl0_pll",
1207 CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, 0, 1,
1208 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1209 DIV_F(CLK_DOUT_CPUCL0_CMUREF, "dout_cpucl0_cmuref", "dout_cpucl0_cpu",
1210 CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF, 0, 3,
1211 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1212 DIV_F(CLK_DOUT_CPUCL0_PCLK, "dout_cpucl0_pclk", "dout_cpucl0_cpu",
1213 CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK, 0, 4,
1214 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1215
1216 /* EMBEDDED_CMU_CPUCL0 */
1217 DIV_F(CLK_DOUT_CLUSTER0_ACLK, "dout_cluster0_aclk", "gout_cluster0_cpu",
1218 CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0, 4,
1219 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1220 DIV_F(CLK_DOUT_CLUSTER0_ATCLK, "dout_cluster0_atclk",
1221 "gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, 0, 4,
1222 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1223 DIV_F(CLK_DOUT_CLUSTER0_PCLKDBG, "dout_cluster0_pclkdbg",
1224 "gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG, 0, 4,
1225 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1226 DIV_F(CLK_DOUT_CLUSTER0_PERIPHCLK, "dout_cluster0_periphclk",
1227 "gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK, 0, 4,
1228 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1229 };
1230
1231 static const struct samsung_gate_clock cpucl0_gate_clks[] __initconst = {
1232 GATE(CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK, "gout_cpucl0_cmu_cpucl0_pclk",
1233 "dout_cpucl0_pclk",
1234 CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1235
1236 /* EMBEDDED_CMU_CPUCL0 */
1237 GATE(CLK_GOUT_CLUSTER0_CPU, "gout_cluster0_cpu", "dout_cpucl0_cpu",
1238 CLK_CON_GAT_GATE_CLK_CPUCL0_CPU, 21, CLK_IGNORE_UNUSED, 0),
1239 GATE(CLK_GOUT_CLUSTER0_SCLK, "gout_cluster0_sclk", "gout_cluster0_cpu",
1240 CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK, 21, CLK_IGNORE_UNUSED, 0),
1241 GATE(CLK_GOUT_CLUSTER0_ATCLK, "gout_cluster0_atclk",
1242 "dout_cluster0_atclk",
1243 CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK, 21, CLK_IGNORE_UNUSED, 0),
1244 GATE(CLK_GOUT_CLUSTER0_PERIPHCLK, "gout_cluster0_periphclk",
1245 "dout_cluster0_periphclk",
1246 CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK, 21,
1247 CLK_IGNORE_UNUSED, 0),
1248 GATE(CLK_GOUT_CLUSTER0_PCLK, "gout_cluster0_pclk",
1249 "dout_cluster0_pclkdbg",
1250 CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1251 };
1252
1253 /*
1254 * Each parameter is going to be written into the corresponding DIV register. So
1255 * the actual divider value for each parameter will be 1/(param+1). All these
1256 * parameters must be in the range of 0..15, as the divider range for all of
1257 * these DIV clocks is 1..16. The default values for these dividers is
1258 * (1, 3, 3, 1).
1259 */
1260 #define E850_CPU_DIV0(aclk, atclk, pclkdbg, periphclk) \
1261 (((aclk) << 16) | ((atclk) << 12) | ((pclkdbg) << 8) | \
1262 ((periphclk) << 4))
1263
1264 static const struct exynos_cpuclk_cfg_data exynos850_cluster_clk_d[] __initconst
1265 = {
1266 { 2210000, E850_CPU_DIV0(1, 3, 3, 1) },
1267 { 2106000, E850_CPU_DIV0(1, 3, 3, 1) },
1268 { 2002000, E850_CPU_DIV0(1, 3, 3, 1) },
1269 { 1846000, E850_CPU_DIV0(1, 3, 3, 1) },
1270 { 1742000, E850_CPU_DIV0(1, 3, 3, 1) },
1271 { 1586000, E850_CPU_DIV0(1, 3, 3, 1) },
1272 { 1456000, E850_CPU_DIV0(1, 3, 3, 1) },
1273 { 1300000, E850_CPU_DIV0(1, 3, 3, 1) },
1274 { 1157000, E850_CPU_DIV0(1, 3, 3, 1) },
1275 { 1053000, E850_CPU_DIV0(1, 3, 3, 1) },
1276 { 949000, E850_CPU_DIV0(1, 3, 3, 1) },
1277 { 806000, E850_CPU_DIV0(1, 3, 3, 1) },
1278 { 650000, E850_CPU_DIV0(1, 3, 3, 1) },
1279 { 546000, E850_CPU_DIV0(1, 3, 3, 1) },
1280 { 442000, E850_CPU_DIV0(1, 3, 3, 1) },
1281 { 351000, E850_CPU_DIV0(1, 3, 3, 1) },
1282 { 247000, E850_CPU_DIV0(1, 3, 3, 1) },
1283 { 182000, E850_CPU_DIV0(1, 3, 3, 1) },
1284 { 130000, E850_CPU_DIV0(1, 3, 3, 1) },
1285 { 0 }
1286 };
1287
1288 static const struct samsung_cpu_clock cpucl0_cpu_clks[] __initconst = {
1289 CPU_CLK(CLK_CLUSTER0_SCLK, "cluster0_clk", CLK_MOUT_PLL_CPUCL0,
1290 CLK_MOUT_CPUCL0_SWITCH_USER, 0, 0x0, CPUCLK_LAYOUT_E850_CL0,
1291 exynos850_cluster_clk_d),
1292 };
1293
1294 static const struct samsung_cmu_info cpucl0_cmu_info __initconst = {
1295 .pll_clks = cpucl0_pll_clks,
1296 .nr_pll_clks = ARRAY_SIZE(cpucl0_pll_clks),
1297 .mux_clks = cpucl0_mux_clks,
1298 .nr_mux_clks = ARRAY_SIZE(cpucl0_mux_clks),
1299 .div_clks = cpucl0_div_clks,
1300 .nr_div_clks = ARRAY_SIZE(cpucl0_div_clks),
1301 .gate_clks = cpucl0_gate_clks,
1302 .nr_gate_clks = ARRAY_SIZE(cpucl0_gate_clks),
1303 .cpu_clks = cpucl0_cpu_clks,
1304 .nr_cpu_clks = ARRAY_SIZE(cpucl0_cpu_clks),
1305 .nr_clk_ids = CLKS_NR_CPUCL0,
1306 .clk_regs = cpucl0_clk_regs,
1307 .nr_clk_regs = ARRAY_SIZE(cpucl0_clk_regs),
1308 .clk_name = "dout_cpucl0_switch",
1309 .manual_plls = true,
1310 };
1311
exynos850_cmu_cpucl0_init(struct device_node * np)1312 static void __init exynos850_cmu_cpucl0_init(struct device_node *np)
1313 {
1314 exynos_arm64_register_cmu(NULL, np, &cpucl0_cmu_info);
1315 }
1316
1317 /* Register CMU_CPUCL0 early, as CPU clocks should be available ASAP */
1318 CLK_OF_DECLARE(exynos850_cmu_cpucl0, "samsung,exynos850-cmu-cpucl0",
1319 exynos850_cmu_cpucl0_init);
1320
1321 /* ---- CMU_CPUCL1 ---------------------------------------------------------- */
1322
1323 /* Register Offset definitions for CMU_CPUCL1 (0x10800000) */
1324 #define PLL_LOCKTIME_PLL_CPUCL1 0x0000
1325 #define PLL_CON0_PLL_CPUCL1 0x0100
1326 #define PLL_CON1_PLL_CPUCL1 0x0104
1327 #define PLL_CON3_PLL_CPUCL1 0x010c
1328 #define PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER 0x0600
1329 #define PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER 0x0610
1330 #define CLK_CON_MUX_MUX_CLK_CPUCL1_PLL 0x1000
1331 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK 0x1800
1332 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK 0x1808
1333 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG 0x180c
1334 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK 0x1810
1335 #define CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF 0x1814
1336 #define CLK_CON_DIV_DIV_CLK_CPUCL1_CPU 0x1818
1337 #define CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK 0x181c
1338 #define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK 0x2000
1339 #define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK 0x2004
1340 #define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK 0x2008
1341 #define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK 0x200c
1342 #define CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK 0x2010
1343 #define CLK_CON_GAT_GATE_CLK_CPUCL1_CPU 0x2020
1344
1345 static const unsigned long cpucl1_clk_regs[] __initconst = {
1346 PLL_LOCKTIME_PLL_CPUCL1,
1347 PLL_CON0_PLL_CPUCL1,
1348 PLL_CON1_PLL_CPUCL1,
1349 PLL_CON3_PLL_CPUCL1,
1350 PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER,
1351 PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER,
1352 CLK_CON_MUX_MUX_CLK_CPUCL1_PLL,
1353 CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK,
1354 CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK,
1355 CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG,
1356 CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK,
1357 CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF,
1358 CLK_CON_DIV_DIV_CLK_CPUCL1_CPU,
1359 CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK,
1360 CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK,
1361 CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK,
1362 CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK,
1363 CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK,
1364 CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK,
1365 CLK_CON_GAT_GATE_CLK_CPUCL1_CPU,
1366 };
1367
1368 /* List of parent clocks for Muxes in CMU_CPUCL1 */
1369 PNAME(mout_pll_cpucl1_p) = { "oscclk", "fout_cpucl1_pll" };
1370 PNAME(mout_cpucl1_switch_user_p) = { "oscclk", "dout_cpucl1_switch" };
1371 PNAME(mout_cpucl1_dbg_user_p) = { "oscclk", "dout_cpucl1_dbg" };
1372 PNAME(mout_cpucl1_pll_p) = { "mout_pll_cpucl1",
1373 "mout_cpucl1_switch_user" };
1374
1375 static const struct samsung_pll_clock cpucl1_pll_clks[] __initconst = {
1376 PLL(pll_0822x, CLK_FOUT_CPUCL1_PLL, "fout_cpucl1_pll", "oscclk",
1377 PLL_LOCKTIME_PLL_CPUCL1, PLL_CON3_PLL_CPUCL1, cpu_pll_rates),
1378 };
1379
1380 static const struct samsung_mux_clock cpucl1_mux_clks[] __initconst = {
1381 MUX_F(CLK_MOUT_PLL_CPUCL1, "mout_pll_cpucl1", mout_pll_cpucl1_p,
1382 PLL_CON0_PLL_CPUCL1, 4, 1,
1383 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
1384 MUX_F(CLK_MOUT_CPUCL1_SWITCH_USER, "mout_cpucl1_switch_user",
1385 mout_cpucl1_switch_user_p,
1386 PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 4, 1,
1387 CLK_SET_RATE_PARENT, 0),
1388 MUX(CLK_MOUT_CPUCL1_DBG_USER, "mout_cpucl1_dbg_user",
1389 mout_cpucl1_dbg_user_p,
1390 PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER, 4, 1),
1391 MUX_F(CLK_MOUT_CPUCL1_PLL, "mout_cpucl1_pll", mout_cpucl1_pll_p,
1392 CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
1393 };
1394
1395 static const struct samsung_div_clock cpucl1_div_clks[] __initconst = {
1396 DIV_F(CLK_DOUT_CPUCL1_CPU, "dout_cpucl1_cpu", "mout_cpucl1_pll",
1397 CLK_CON_DIV_DIV_CLK_CPUCL1_CPU, 0, 1,
1398 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1399 DIV_F(CLK_DOUT_CPUCL1_CMUREF, "dout_cpucl1_cmuref", "dout_cpucl1_cpu",
1400 CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF, 0, 3,
1401 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1402 DIV_F(CLK_DOUT_CPUCL1_PCLK, "dout_cpucl1_pclk", "dout_cpucl1_cpu",
1403 CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK, 0, 4,
1404 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1405
1406 /* EMBEDDED_CMU_CPUCL1 */
1407 DIV_F(CLK_DOUT_CLUSTER1_ACLK, "dout_cluster1_aclk", "gout_cluster1_cpu",
1408 CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0, 4,
1409 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1410 DIV_F(CLK_DOUT_CLUSTER1_ATCLK, "dout_cluster1_atclk",
1411 "gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, 0, 4,
1412 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1413 DIV_F(CLK_DOUT_CLUSTER1_PCLKDBG, "dout_cluster1_pclkdbg",
1414 "gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG, 0, 4,
1415 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1416 DIV_F(CLK_DOUT_CLUSTER1_PERIPHCLK, "dout_cluster1_periphclk",
1417 "gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK, 0, 4,
1418 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1419 };
1420
1421 static const struct samsung_gate_clock cpucl1_gate_clks[] __initconst = {
1422 GATE(CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK, "gout_cpucl1_cmu_cpucl1_pclk",
1423 "dout_cpucl1_pclk",
1424 CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1425
1426 /* EMBEDDED_CMU_CPUCL1 */
1427 GATE(CLK_GOUT_CLUSTER1_CPU, "gout_cluster1_cpu", "dout_cpucl1_cpu",
1428 CLK_CON_GAT_GATE_CLK_CPUCL1_CPU, 21, CLK_IGNORE_UNUSED, 0),
1429 GATE(CLK_GOUT_CLUSTER1_SCLK, "gout_cluster1_sclk", "gout_cluster1_cpu",
1430 CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK, 21, CLK_IGNORE_UNUSED, 0),
1431 GATE(CLK_GOUT_CLUSTER1_ATCLK, "gout_cluster1_atclk",
1432 "dout_cluster1_atclk",
1433 CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK, 21, CLK_IGNORE_UNUSED, 0),
1434 GATE(CLK_GOUT_CLUSTER1_PERIPHCLK, "gout_cluster1_periphclk",
1435 "dout_cluster1_periphclk",
1436 CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK, 21,
1437 CLK_IGNORE_UNUSED, 0),
1438 GATE(CLK_GOUT_CLUSTER1_PCLK, "gout_cluster1_pclk",
1439 "dout_cluster1_pclkdbg",
1440 CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1441 };
1442
1443 static const struct samsung_cpu_clock cpucl1_cpu_clks[] __initconst = {
1444 CPU_CLK(CLK_CLUSTER1_SCLK, "cluster1_clk", CLK_MOUT_PLL_CPUCL1,
1445 CLK_MOUT_CPUCL1_SWITCH_USER, 0, 0x0, CPUCLK_LAYOUT_E850_CL1,
1446 exynos850_cluster_clk_d),
1447 };
1448
1449 static const struct samsung_cmu_info cpucl1_cmu_info __initconst = {
1450 .pll_clks = cpucl1_pll_clks,
1451 .nr_pll_clks = ARRAY_SIZE(cpucl1_pll_clks),
1452 .mux_clks = cpucl1_mux_clks,
1453 .nr_mux_clks = ARRAY_SIZE(cpucl1_mux_clks),
1454 .div_clks = cpucl1_div_clks,
1455 .nr_div_clks = ARRAY_SIZE(cpucl1_div_clks),
1456 .gate_clks = cpucl1_gate_clks,
1457 .nr_gate_clks = ARRAY_SIZE(cpucl1_gate_clks),
1458 .cpu_clks = cpucl1_cpu_clks,
1459 .nr_cpu_clks = ARRAY_SIZE(cpucl1_cpu_clks),
1460 .nr_clk_ids = CLKS_NR_CPUCL1,
1461 .clk_regs = cpucl1_clk_regs,
1462 .nr_clk_regs = ARRAY_SIZE(cpucl1_clk_regs),
1463 .clk_name = "dout_cpucl1_switch",
1464 .manual_plls = true,
1465 };
1466
exynos850_cmu_cpucl1_init(struct device_node * np)1467 static void __init exynos850_cmu_cpucl1_init(struct device_node *np)
1468 {
1469 exynos_arm64_register_cmu(NULL, np, &cpucl1_cmu_info);
1470 }
1471
1472 /* Register CMU_CPUCL1 early, as CPU clocks should be available ASAP */
1473 CLK_OF_DECLARE(exynos850_cmu_cpucl1, "samsung,exynos850-cmu-cpucl1",
1474 exynos850_cmu_cpucl1_init);
1475
1476 /* ---- CMU_G3D ------------------------------------------------------------- */
1477
1478 /* Register Offset definitions for CMU_G3D (0x11400000) */
1479 #define PLL_LOCKTIME_PLL_G3D 0x0000
1480 #define PLL_CON0_PLL_G3D 0x0100
1481 #define PLL_CON3_PLL_G3D 0x010c
1482 #define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER 0x0600
1483 #define CLK_CON_MUX_MUX_CLK_G3D_BUSD 0x1000
1484 #define CLK_CON_DIV_DIV_CLK_G3D_BUSP 0x1804
1485 #define CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK 0x2000
1486 #define CLK_CON_GAT_CLK_G3D_GPU_CLK 0x2004
1487 #define CLK_CON_GAT_GOUT_G3D_TZPC_PCLK 0x200c
1488 #define CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK 0x2010
1489 #define CLK_CON_GAT_GOUT_G3D_BUSD_CLK 0x2024
1490 #define CLK_CON_GAT_GOUT_G3D_BUSP_CLK 0x2028
1491 #define CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK 0x202c
1492
1493 static const unsigned long g3d_clk_regs[] __initconst = {
1494 PLL_LOCKTIME_PLL_G3D,
1495 PLL_CON0_PLL_G3D,
1496 PLL_CON3_PLL_G3D,
1497 PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER,
1498 CLK_CON_MUX_MUX_CLK_G3D_BUSD,
1499 CLK_CON_DIV_DIV_CLK_G3D_BUSP,
1500 CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK,
1501 CLK_CON_GAT_CLK_G3D_GPU_CLK,
1502 CLK_CON_GAT_GOUT_G3D_TZPC_PCLK,
1503 CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK,
1504 CLK_CON_GAT_GOUT_G3D_BUSD_CLK,
1505 CLK_CON_GAT_GOUT_G3D_BUSP_CLK,
1506 CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK,
1507 };
1508
1509 /* List of parent clocks for Muxes in CMU_G3D */
1510 PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll" };
1511 PNAME(mout_g3d_switch_user_p) = { "oscclk", "dout_g3d_switch" };
1512 PNAME(mout_g3d_busd_p) = { "mout_g3d_pll", "mout_g3d_switch_user" };
1513
1514 /*
1515 * Do not provide PLL table to PLL_G3D, as MANUAL_PLL_CTRL bit is not set
1516 * for that PLL by default, so set_rate operation would fail.
1517 */
1518 static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
1519 PLL(pll_0818x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
1520 PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL),
1521 };
1522
1523 static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
1524 MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
1525 PLL_CON0_PLL_G3D, 4, 1),
1526 MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_g3d_switch_user",
1527 mout_g3d_switch_user_p,
1528 PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 4, 1),
1529 MUX(CLK_MOUT_G3D_BUSD, "mout_g3d_busd", mout_g3d_busd_p,
1530 CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0, 1),
1531 };
1532
1533 static const struct samsung_div_clock g3d_div_clks[] __initconst = {
1534 DIV(CLK_DOUT_G3D_BUSP, "dout_g3d_busp", "mout_g3d_busd",
1535 CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0, 3),
1536 };
1537
1538 static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
1539 GATE(CLK_GOUT_G3D_CMU_G3D_PCLK, "gout_g3d_cmu_g3d_pclk",
1540 "dout_g3d_busp",
1541 CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1542 GATE(CLK_GOUT_G3D_GPU_CLK, "gout_g3d_gpu_clk", "mout_g3d_busd",
1543 CLK_CON_GAT_CLK_G3D_GPU_CLK, 21, 0, 0),
1544 GATE(CLK_GOUT_G3D_TZPC_PCLK, "gout_g3d_tzpc_pclk", "dout_g3d_busp",
1545 CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, 21, 0, 0),
1546 GATE(CLK_GOUT_G3D_GRAY2BIN_CLK, "gout_g3d_gray2bin_clk",
1547 "mout_g3d_busd",
1548 CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, 21, 0, 0),
1549 GATE(CLK_GOUT_G3D_BUSD_CLK, "gout_g3d_busd_clk", "mout_g3d_busd",
1550 CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 21, 0, 0),
1551 GATE(CLK_GOUT_G3D_BUSP_CLK, "gout_g3d_busp_clk", "dout_g3d_busp",
1552 CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 21, 0, 0),
1553 GATE(CLK_GOUT_G3D_SYSREG_PCLK, "gout_g3d_sysreg_pclk", "dout_g3d_busp",
1554 CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 21, 0, 0),
1555 };
1556
1557 static const struct samsung_cmu_info g3d_cmu_info __initconst = {
1558 .pll_clks = g3d_pll_clks,
1559 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
1560 .mux_clks = g3d_mux_clks,
1561 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
1562 .div_clks = g3d_div_clks,
1563 .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
1564 .gate_clks = g3d_gate_clks,
1565 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
1566 .nr_clk_ids = CLKS_NR_G3D,
1567 .clk_regs = g3d_clk_regs,
1568 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
1569 .clk_name = "dout_g3d_switch",
1570 };
1571
1572 /* ---- CMU_HSI ------------------------------------------------------------- */
1573
1574 /* Register Offset definitions for CMU_HSI (0x13400000) */
1575 #define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600
1576 #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610
1577 #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620
1578 #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000
1579 #define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK 0x2000
1580 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008
1581 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c
1582 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010
1583 #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018
1584 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024
1585 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028
1586 #define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK 0x202c
1587 #define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK 0x2030
1588 #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038
1589 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c
1590 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040
1591
1592 static const unsigned long hsi_clk_regs[] __initconst = {
1593 PLL_CON0_MUX_CLKCMU_HSI_BUS_USER,
1594 PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER,
1595 PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER,
1596 CLK_CON_MUX_MUX_CLK_HSI_RTC,
1597 CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK,
1598 CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV,
1599 CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50,
1600 CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26,
1601 CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK,
1602 CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK,
1603 CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN,
1604 CLK_CON_GAT_GOUT_HSI_PPMU_ACLK,
1605 CLK_CON_GAT_GOUT_HSI_PPMU_PCLK,
1606 CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK,
1607 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20,
1608 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY,
1609 };
1610
1611 /* List of parent clocks for Muxes in CMU_HSI */
1612 PNAME(mout_hsi_bus_user_p) = { "oscclk", "dout_hsi_bus" };
1613 PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" };
1614 PNAME(mout_hsi_usb20drd_user_p) = { "oscclk", "dout_hsi_usb20drd" };
1615 PNAME(mout_hsi_rtc_p) = { "rtcclk", "oscclk" };
1616
1617 static const struct samsung_mux_clock hsi_mux_clks[] __initconst = {
1618 MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p,
1619 PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1),
1620 MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user",
1621 mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER,
1622 4, 1, CLK_SET_RATE_PARENT, 0),
1623 MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user",
1624 mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER,
1625 4, 1),
1626 MUX(CLK_MOUT_HSI_RTC, "mout_hsi_rtc", mout_hsi_rtc_p,
1627 CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1),
1628 };
1629
1630 static const struct samsung_gate_clock hsi_gate_clks[] __initconst = {
1631 /* TODO: Should be enabled in corresponding driver */
1632 GATE(CLK_GOUT_HSI_CMU_HSI_PCLK, "gout_hsi_cmu_hsi_pclk",
1633 "mout_hsi_bus_user",
1634 CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1635 GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc",
1636 CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0),
1637 GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user",
1638 CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0),
1639 GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "oscclk",
1640 CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0),
1641 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
1642 GATE(CLK_GOUT_GPIO_HSI_PCLK, "gout_gpio_hsi_pclk", "mout_hsi_bus_user",
1643 CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1644 GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user",
1645 CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0),
1646 GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
1647 "mout_hsi_mmc_card_user",
1648 CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0),
1649 GATE(CLK_GOUT_HSI_PPMU_ACLK, "gout_hsi_ppmu_aclk", "mout_hsi_bus_user",
1650 CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 21, 0, 0),
1651 GATE(CLK_GOUT_HSI_PPMU_PCLK, "gout_hsi_ppmu_pclk", "mout_hsi_bus_user",
1652 CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 21, 0, 0),
1653 GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk",
1654 "mout_hsi_bus_user",
1655 CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0),
1656 GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user",
1657 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0),
1658 GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early",
1659 "mout_hsi_bus_user",
1660 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0),
1661 };
1662
1663 static const struct samsung_cmu_info hsi_cmu_info __initconst = {
1664 .mux_clks = hsi_mux_clks,
1665 .nr_mux_clks = ARRAY_SIZE(hsi_mux_clks),
1666 .gate_clks = hsi_gate_clks,
1667 .nr_gate_clks = ARRAY_SIZE(hsi_gate_clks),
1668 .nr_clk_ids = CLKS_NR_HSI,
1669 .clk_regs = hsi_clk_regs,
1670 .nr_clk_regs = ARRAY_SIZE(hsi_clk_regs),
1671 .clk_name = "dout_hsi_bus",
1672 };
1673
1674 /* ---- CMU_IS -------------------------------------------------------------- */
1675
1676 #define PLL_CON0_MUX_CLKCMU_IS_BUS_USER 0x0600
1677 #define PLL_CON0_MUX_CLKCMU_IS_GDC_USER 0x0610
1678 #define PLL_CON0_MUX_CLKCMU_IS_ITP_USER 0x0620
1679 #define PLL_CON0_MUX_CLKCMU_IS_VRA_USER 0x0630
1680 #define CLK_CON_DIV_DIV_CLK_IS_BUSP 0x1800
1681 #define CLK_CON_GAT_CLK_IS_CMU_IS_PCLK 0x2000
1682 #define CLK_CON_GAT_GOUT_IS_CSIS0_ACLK 0x2040
1683 #define CLK_CON_GAT_GOUT_IS_CSIS1_ACLK 0x2044
1684 #define CLK_CON_GAT_GOUT_IS_CSIS2_ACLK 0x2048
1685 #define CLK_CON_GAT_GOUT_IS_TZPC_PCLK 0x204c
1686 #define CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA 0x2050
1687 #define CLK_CON_GAT_GOUT_IS_CLK_GDC 0x2054
1688 #define CLK_CON_GAT_GOUT_IS_CLK_IPP 0x2058
1689 #define CLK_CON_GAT_GOUT_IS_CLK_ITP 0x205c
1690 #define CLK_CON_GAT_GOUT_IS_CLK_MCSC 0x2060
1691 #define CLK_CON_GAT_GOUT_IS_CLK_VRA 0x2064
1692 #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK 0x2074
1693 #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK 0x2078
1694 #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK 0x207c
1695 #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK 0x2080
1696 #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1 0x2098
1697 #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1 0x209c
1698 #define CLK_CON_GAT_GOUT_IS_SYSREG_PCLK 0x20a0
1699
1700 static const unsigned long is_clk_regs[] __initconst = {
1701 PLL_CON0_MUX_CLKCMU_IS_BUS_USER,
1702 PLL_CON0_MUX_CLKCMU_IS_GDC_USER,
1703 PLL_CON0_MUX_CLKCMU_IS_ITP_USER,
1704 PLL_CON0_MUX_CLKCMU_IS_VRA_USER,
1705 CLK_CON_DIV_DIV_CLK_IS_BUSP,
1706 CLK_CON_GAT_CLK_IS_CMU_IS_PCLK,
1707 CLK_CON_GAT_GOUT_IS_CSIS0_ACLK,
1708 CLK_CON_GAT_GOUT_IS_CSIS1_ACLK,
1709 CLK_CON_GAT_GOUT_IS_CSIS2_ACLK,
1710 CLK_CON_GAT_GOUT_IS_TZPC_PCLK,
1711 CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA,
1712 CLK_CON_GAT_GOUT_IS_CLK_GDC,
1713 CLK_CON_GAT_GOUT_IS_CLK_IPP,
1714 CLK_CON_GAT_GOUT_IS_CLK_ITP,
1715 CLK_CON_GAT_GOUT_IS_CLK_MCSC,
1716 CLK_CON_GAT_GOUT_IS_CLK_VRA,
1717 CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK,
1718 CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK,
1719 CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK,
1720 CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK,
1721 CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1,
1722 CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1,
1723 CLK_CON_GAT_GOUT_IS_SYSREG_PCLK,
1724 };
1725
1726 /* List of parent clocks for Muxes in CMU_IS */
1727 PNAME(mout_is_bus_user_p) = { "oscclk", "dout_is_bus" };
1728 PNAME(mout_is_itp_user_p) = { "oscclk", "dout_is_itp" };
1729 PNAME(mout_is_vra_user_p) = { "oscclk", "dout_is_vra" };
1730 PNAME(mout_is_gdc_user_p) = { "oscclk", "dout_is_gdc" };
1731
1732 static const struct samsung_mux_clock is_mux_clks[] __initconst = {
1733 MUX(CLK_MOUT_IS_BUS_USER, "mout_is_bus_user", mout_is_bus_user_p,
1734 PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 4, 1),
1735 MUX(CLK_MOUT_IS_ITP_USER, "mout_is_itp_user", mout_is_itp_user_p,
1736 PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 4, 1),
1737 MUX(CLK_MOUT_IS_VRA_USER, "mout_is_vra_user", mout_is_vra_user_p,
1738 PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 4, 1),
1739 MUX(CLK_MOUT_IS_GDC_USER, "mout_is_gdc_user", mout_is_gdc_user_p,
1740 PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 4, 1),
1741 };
1742
1743 static const struct samsung_div_clock is_div_clks[] __initconst = {
1744 DIV(CLK_DOUT_IS_BUSP, "dout_is_busp", "mout_is_bus_user",
1745 CLK_CON_DIV_DIV_CLK_IS_BUSP, 0, 2),
1746 };
1747
1748 static const struct samsung_gate_clock is_gate_clks[] __initconst = {
1749 /* TODO: Should be enabled in IS driver */
1750 GATE(CLK_GOUT_IS_CMU_IS_PCLK, "gout_is_cmu_is_pclk", "dout_is_busp",
1751 CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1752 GATE(CLK_GOUT_IS_CSIS0_ACLK, "gout_is_csis0_aclk", "mout_is_bus_user",
1753 CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 21, 0, 0),
1754 GATE(CLK_GOUT_IS_CSIS1_ACLK, "gout_is_csis1_aclk", "mout_is_bus_user",
1755 CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 21, 0, 0),
1756 GATE(CLK_GOUT_IS_CSIS2_ACLK, "gout_is_csis2_aclk", "mout_is_bus_user",
1757 CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 21, 0, 0),
1758 GATE(CLK_GOUT_IS_TZPC_PCLK, "gout_is_tzpc_pclk", "dout_is_busp",
1759 CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 21, 0, 0),
1760 GATE(CLK_GOUT_IS_CSIS_DMA_CLK, "gout_is_csis_dma_clk",
1761 "mout_is_bus_user",
1762 CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 21, 0, 0),
1763 GATE(CLK_GOUT_IS_GDC_CLK, "gout_is_gdc_clk", "mout_is_gdc_user",
1764 CLK_CON_GAT_GOUT_IS_CLK_GDC, 21, 0, 0),
1765 GATE(CLK_GOUT_IS_IPP_CLK, "gout_is_ipp_clk", "mout_is_bus_user",
1766 CLK_CON_GAT_GOUT_IS_CLK_IPP, 21, 0, 0),
1767 GATE(CLK_GOUT_IS_ITP_CLK, "gout_is_itp_clk", "mout_is_itp_user",
1768 CLK_CON_GAT_GOUT_IS_CLK_ITP, 21, 0, 0),
1769 GATE(CLK_GOUT_IS_MCSC_CLK, "gout_is_mcsc_clk", "mout_is_itp_user",
1770 CLK_CON_GAT_GOUT_IS_CLK_MCSC, 21, 0, 0),
1771 GATE(CLK_GOUT_IS_VRA_CLK, "gout_is_vra_clk", "mout_is_vra_user",
1772 CLK_CON_GAT_GOUT_IS_CLK_VRA, 21, 0, 0),
1773 GATE(CLK_GOUT_IS_PPMU_IS0_ACLK, "gout_is_ppmu_is0_aclk",
1774 "mout_is_bus_user",
1775 CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 21, 0, 0),
1776 GATE(CLK_GOUT_IS_PPMU_IS0_PCLK, "gout_is_ppmu_is0_pclk", "dout_is_busp",
1777 CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 21, 0, 0),
1778 GATE(CLK_GOUT_IS_PPMU_IS1_ACLK, "gout_is_ppmu_is1_aclk",
1779 "mout_is_itp_user",
1780 CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 21, 0, 0),
1781 GATE(CLK_GOUT_IS_PPMU_IS1_PCLK, "gout_is_ppmu_is1_pclk", "dout_is_busp",
1782 CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 21, 0, 0),
1783 GATE(CLK_GOUT_IS_SYSMMU_IS0_CLK, "gout_is_sysmmu_is0_clk",
1784 "mout_is_bus_user",
1785 CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 21, 0, 0),
1786 GATE(CLK_GOUT_IS_SYSMMU_IS1_CLK, "gout_is_sysmmu_is1_clk",
1787 "mout_is_itp_user",
1788 CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 21, 0, 0),
1789 GATE(CLK_GOUT_IS_SYSREG_PCLK, "gout_is_sysreg_pclk", "dout_is_busp",
1790 CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 21, 0, 0),
1791 };
1792
1793 static const struct samsung_cmu_info is_cmu_info __initconst = {
1794 .mux_clks = is_mux_clks,
1795 .nr_mux_clks = ARRAY_SIZE(is_mux_clks),
1796 .div_clks = is_div_clks,
1797 .nr_div_clks = ARRAY_SIZE(is_div_clks),
1798 .gate_clks = is_gate_clks,
1799 .nr_gate_clks = ARRAY_SIZE(is_gate_clks),
1800 .nr_clk_ids = CLKS_NR_IS,
1801 .clk_regs = is_clk_regs,
1802 .nr_clk_regs = ARRAY_SIZE(is_clk_regs),
1803 .clk_name = "dout_is_bus",
1804 };
1805
1806 /* ---- CMU_MFCMSCL --------------------------------------------------------- */
1807
1808 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER 0x0600
1809 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER 0x0610
1810 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER 0x0620
1811 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER 0x0630
1812 #define CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP 0x1800
1813 #define CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK 0x2000
1814 #define CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK 0x2038
1815 #define CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK 0x203c
1816 #define CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK 0x2048
1817 #define CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK 0x204c
1818 #define CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK 0x2050
1819 #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK 0x2054
1820 #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK 0x2058
1821 #define CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1 0x2074
1822 #define CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK 0x2078
1823
1824 static const unsigned long mfcmscl_clk_regs[] __initconst = {
1825 PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER,
1826 PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER,
1827 PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER,
1828 PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER,
1829 CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP,
1830 CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK,
1831 CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK,
1832 CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK,
1833 CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK,
1834 CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK,
1835 CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK,
1836 CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK,
1837 CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK,
1838 CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1,
1839 CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK,
1840 };
1841
1842 /* List of parent clocks for Muxes in CMU_MFCMSCL */
1843 PNAME(mout_mfcmscl_mfc_user_p) = { "oscclk", "dout_mfcmscl_mfc" };
1844 PNAME(mout_mfcmscl_m2m_user_p) = { "oscclk", "dout_mfcmscl_m2m" };
1845 PNAME(mout_mfcmscl_mcsc_user_p) = { "oscclk", "dout_mfcmscl_mcsc" };
1846 PNAME(mout_mfcmscl_jpeg_user_p) = { "oscclk", "dout_mfcmscl_jpeg" };
1847
1848 static const struct samsung_mux_clock mfcmscl_mux_clks[] __initconst = {
1849 MUX(CLK_MOUT_MFCMSCL_MFC_USER, "mout_mfcmscl_mfc_user",
1850 mout_mfcmscl_mfc_user_p,
1851 PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER, 4, 1),
1852 MUX(CLK_MOUT_MFCMSCL_M2M_USER, "mout_mfcmscl_m2m_user",
1853 mout_mfcmscl_m2m_user_p,
1854 PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER, 4, 1),
1855 MUX(CLK_MOUT_MFCMSCL_MCSC_USER, "mout_mfcmscl_mcsc_user",
1856 mout_mfcmscl_mcsc_user_p,
1857 PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER, 4, 1),
1858 MUX(CLK_MOUT_MFCMSCL_JPEG_USER, "mout_mfcmscl_jpeg_user",
1859 mout_mfcmscl_jpeg_user_p,
1860 PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER, 4, 1),
1861 };
1862
1863 static const struct samsung_div_clock mfcmscl_div_clks[] __initconst = {
1864 DIV(CLK_DOUT_MFCMSCL_BUSP, "dout_mfcmscl_busp", "mout_mfcmscl_mfc_user",
1865 CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP, 0, 3),
1866 };
1867
1868 static const struct samsung_gate_clock mfcmscl_gate_clks[] __initconst = {
1869 /* TODO: Should be enabled in MFC driver */
1870 GATE(CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK, "gout_mfcmscl_cmu_mfcmscl_pclk",
1871 "dout_mfcmscl_busp", CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK,
1872 21, CLK_IGNORE_UNUSED, 0),
1873 GATE(CLK_GOUT_MFCMSCL_TZPC_PCLK, "gout_mfcmscl_tzpc_pclk",
1874 "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK,
1875 21, 0, 0),
1876 GATE(CLK_GOUT_MFCMSCL_JPEG_ACLK, "gout_mfcmscl_jpeg_aclk",
1877 "mout_mfcmscl_jpeg_user", CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK,
1878 21, 0, 0),
1879 GATE(CLK_GOUT_MFCMSCL_M2M_ACLK, "gout_mfcmscl_m2m_aclk",
1880 "mout_mfcmscl_m2m_user", CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK,
1881 21, 0, 0),
1882 GATE(CLK_GOUT_MFCMSCL_MCSC_CLK, "gout_mfcmscl_mcsc_clk",
1883 "mout_mfcmscl_mcsc_user", CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK,
1884 21, 0, 0),
1885 GATE(CLK_GOUT_MFCMSCL_MFC_ACLK, "gout_mfcmscl_mfc_aclk",
1886 "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK,
1887 21, 0, 0),
1888 GATE(CLK_GOUT_MFCMSCL_PPMU_ACLK, "gout_mfcmscl_ppmu_aclk",
1889 "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK,
1890 21, 0, 0),
1891 GATE(CLK_GOUT_MFCMSCL_PPMU_PCLK, "gout_mfcmscl_ppmu_pclk",
1892 "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK,
1893 21, 0, 0),
1894 GATE(CLK_GOUT_MFCMSCL_SYSMMU_CLK, "gout_mfcmscl_sysmmu_clk",
1895 "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1,
1896 21, 0, 0),
1897 GATE(CLK_GOUT_MFCMSCL_SYSREG_PCLK, "gout_mfcmscl_sysreg_pclk",
1898 "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK,
1899 21, 0, 0),
1900 };
1901
1902 static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = {
1903 .mux_clks = mfcmscl_mux_clks,
1904 .nr_mux_clks = ARRAY_SIZE(mfcmscl_mux_clks),
1905 .div_clks = mfcmscl_div_clks,
1906 .nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks),
1907 .gate_clks = mfcmscl_gate_clks,
1908 .nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks),
1909 .nr_clk_ids = CLKS_NR_MFCMSCL,
1910 .clk_regs = mfcmscl_clk_regs,
1911 .nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs),
1912 .clk_name = "dout_mfcmscl_mfc",
1913 };
1914
1915 /* ---- CMU_PERI ------------------------------------------------------------ */
1916
1917 /* Register Offset definitions for CMU_PERI (0x10030000) */
1918 #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600
1919 #define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER 0x0610
1920 #define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER 0x0620
1921 #define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630
1922 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0 0x1800
1923 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1 0x1804
1924 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2 0x1808
1925 #define CLK_CON_DIV_DIV_CLK_PERI_SPI_0 0x180c
1926 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c
1927 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010
1928 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014
1929 #define CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK 0x2018
1930 #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020
1931 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024
1932 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028
1933 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK 0x202c
1934 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x2030
1935 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK 0x2034
1936 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2038
1937 #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x203c
1938 #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x2040
1939 #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2044
1940 #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2048
1941 #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x204c
1942 #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x2050
1943 #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2054
1944 #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x205c
1945 #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2064
1946 #define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK 0x209c
1947 #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x20a0
1948 #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20a4
1949 #define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8
1950 #define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac
1951 #define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK 0x20b0
1952 #define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK 0x20b4
1953
1954 static const unsigned long peri_clk_regs[] __initconst = {
1955 PLL_CON0_MUX_CLKCMU_PERI_BUS_USER,
1956 PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER,
1957 PLL_CON0_MUX_CLKCMU_PERI_SPI_USER,
1958 PLL_CON0_MUX_CLKCMU_PERI_UART_USER,
1959 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0,
1960 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1,
1961 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2,
1962 CLK_CON_DIV_DIV_CLK_PERI_SPI_0,
1963 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0,
1964 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1,
1965 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2,
1966 CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK,
1967 CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK,
1968 CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK,
1969 CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK,
1970 CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK,
1971 CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK,
1972 CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK,
1973 CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK,
1974 CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK,
1975 CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK,
1976 CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK,
1977 CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK,
1978 CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK,
1979 CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK,
1980 CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK,
1981 CLK_CON_GAT_GOUT_PERI_MCT_PCLK,
1982 CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK,
1983 CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK,
1984 CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK,
1985 CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK,
1986 CLK_CON_GAT_GOUT_PERI_UART_IPCLK,
1987 CLK_CON_GAT_GOUT_PERI_UART_PCLK,
1988 CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK,
1989 CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK,
1990 };
1991
1992 /* List of parent clocks for Muxes in CMU_PERI */
1993 PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" };
1994 PNAME(mout_peri_uart_user_p) = { "oscclk", "dout_peri_uart" };
1995 PNAME(mout_peri_hsi2c_user_p) = { "oscclk", "dout_peri_ip" };
1996 PNAME(mout_peri_spi_user_p) = { "oscclk", "dout_peri_ip" };
1997
1998 static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
1999 MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p,
2000 PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1),
2001 MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user",
2002 mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1),
2003 MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user",
2004 mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1),
2005 MUX_F(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user",
2006 mout_peri_spi_user_p, PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1,
2007 CLK_SET_RATE_PARENT, 0),
2008 };
2009
2010 static const struct samsung_div_clock peri_div_clks[] __initconst = {
2011 DIV(CLK_DOUT_PERI_HSI2C0, "dout_peri_hsi2c0", "gout_peri_hsi2c0",
2012 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5),
2013 DIV(CLK_DOUT_PERI_HSI2C1, "dout_peri_hsi2c1", "gout_peri_hsi2c1",
2014 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5),
2015 DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2",
2016 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5),
2017 DIV_F(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user",
2018 CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5, CLK_SET_RATE_PARENT, 0),
2019 };
2020
2021 static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
2022 GATE(CLK_GOUT_PERI_HSI2C0, "gout_peri_hsi2c0", "mout_peri_hsi2c_user",
2023 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0),
2024 GATE(CLK_GOUT_PERI_HSI2C1, "gout_peri_hsi2c1", "mout_peri_hsi2c_user",
2025 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0),
2026 GATE(CLK_GOUT_PERI_HSI2C2, "gout_peri_hsi2c2", "mout_peri_hsi2c_user",
2027 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0),
2028 GATE(CLK_GOUT_HSI2C0_IPCLK, "gout_hsi2c0_ipclk", "dout_peri_hsi2c0",
2029 CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0),
2030 GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user",
2031 CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0),
2032 GATE(CLK_GOUT_HSI2C1_IPCLK, "gout_hsi2c1_ipclk", "dout_peri_hsi2c1",
2033 CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0),
2034 GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user",
2035 CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0),
2036 GATE(CLK_GOUT_HSI2C2_IPCLK, "gout_hsi2c2_ipclk", "dout_peri_hsi2c2",
2037 CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0),
2038 GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user",
2039 CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0),
2040 GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user",
2041 CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0),
2042 GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user",
2043 CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0),
2044 GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user",
2045 CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0),
2046 GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user",
2047 CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0),
2048 GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user",
2049 CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0),
2050 GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user",
2051 CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0),
2052 GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user",
2053 CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0),
2054 GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user",
2055 CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0),
2056 GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk",
2057 "mout_peri_bus_user",
2058 CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0),
2059 GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0",
2060 CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, CLK_SET_RATE_PARENT, 0),
2061 GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user",
2062 CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0),
2063 GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk",
2064 "mout_peri_bus_user",
2065 CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0),
2066 GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user",
2067 CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0),
2068 GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user",
2069 CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0),
2070 GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user",
2071 CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0),
2072 GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user",
2073 CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0),
2074 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
2075 GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk",
2076 "mout_peri_bus_user",
2077 CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
2078 GATE(CLK_GOUT_BUSIF_TMU_PCLK, "gout_busif_tmu_pclk",
2079 "mout_peri_bus_user",
2080 CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK, 21, 0, 0),
2081 };
2082
2083 static const struct samsung_cmu_info peri_cmu_info __initconst = {
2084 .mux_clks = peri_mux_clks,
2085 .nr_mux_clks = ARRAY_SIZE(peri_mux_clks),
2086 .div_clks = peri_div_clks,
2087 .nr_div_clks = ARRAY_SIZE(peri_div_clks),
2088 .gate_clks = peri_gate_clks,
2089 .nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
2090 .nr_clk_ids = CLKS_NR_PERI,
2091 .clk_regs = peri_clk_regs,
2092 .nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
2093 .clk_name = "dout_peri_bus",
2094 };
2095
exynos850_cmu_peri_init(struct device_node * np)2096 static void __init exynos850_cmu_peri_init(struct device_node *np)
2097 {
2098 exynos_arm64_register_cmu(NULL, np, &peri_cmu_info);
2099 }
2100
2101 /* Register CMU_PERI early, as it's needed for MCT timer */
2102 CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri",
2103 exynos850_cmu_peri_init);
2104
2105 /* ---- CMU_CORE ------------------------------------------------------------ */
2106
2107 /* Register Offset definitions for CMU_CORE (0x12000000) */
2108 #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600
2109 #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0610
2110 #define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620
2111 #define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER 0x0630
2112 #define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000
2113 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
2114 #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038
2115 #define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040
2116 #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044
2117 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8
2118 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec
2119 #define CLK_CON_GAT_GOUT_CORE_PDMA_ACLK 0x20f0
2120 #define CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK 0x2124
2121 #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128
2122 #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c
2123 #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130
2124
2125 static const unsigned long core_clk_regs[] __initconst = {
2126 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
2127 PLL_CON0_MUX_CLKCMU_CORE_CCI_USER,
2128 PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER,
2129 PLL_CON0_MUX_CLKCMU_CORE_SSS_USER,
2130 CLK_CON_MUX_MUX_CLK_CORE_GIC,
2131 CLK_CON_DIV_DIV_CLK_CORE_BUSP,
2132 CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,
2133 CLK_CON_GAT_GOUT_CORE_GIC_CLK,
2134 CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK,
2135 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK,
2136 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
2137 CLK_CON_GAT_GOUT_CORE_PDMA_ACLK,
2138 CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK,
2139 CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK,
2140 CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK,
2141 CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK,
2142 };
2143
2144 /* List of parent clocks for Muxes in CMU_CORE */
2145 PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" };
2146 PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" };
2147 PNAME(mout_core_mmc_embd_user_p) = { "oscclk", "dout_core_mmc_embd" };
2148 PNAME(mout_core_sss_user_p) = { "oscclk", "dout_core_sss" };
2149 PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" };
2150
2151 static const struct samsung_mux_clock core_mux_clks[] __initconst = {
2152 MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
2153 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
2154 MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p,
2155 PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1),
2156 MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user",
2157 mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER,
2158 4, 1, CLK_SET_RATE_PARENT, 0),
2159 MUX(CLK_MOUT_CORE_SSS_USER, "mout_core_sss_user", mout_core_sss_user_p,
2160 PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 4, 1),
2161 MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p,
2162 CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1),
2163 };
2164
2165 static const struct samsung_div_clock core_div_clks[] __initconst = {
2166 DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
2167 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
2168 };
2169
2170 static const struct samsung_gate_clock core_gate_clks[] __initconst = {
2171 /* CCI (interconnect) clock must be always running */
2172 GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user",
2173 CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
2174 /* GIC (interrupt controller) clock must be always running */
2175 GATE(CLK_GOUT_GIC_CLK, "gout_gic_clk", "mout_core_gic",
2176 CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0),
2177 GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp",
2178 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0),
2179 GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin",
2180 "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
2181 21, CLK_SET_RATE_PARENT, 0),
2182 GATE(CLK_GOUT_PDMA_CORE_ACLK, "gout_pdma_core_aclk",
2183 "mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_PDMA_ACLK, 21, 0, 0),
2184 GATE(CLK_GOUT_SPDMA_CORE_ACLK, "gout_spdma_core_aclk",
2185 "mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK, 21, 0, 0),
2186 GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user",
2187 CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0),
2188 GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp",
2189 CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0),
2190 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
2191 GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp",
2192 CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0),
2193 GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk",
2194 "dout_core_busp",
2195 CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0),
2196 };
2197
2198 static const struct samsung_cmu_info core_cmu_info __initconst = {
2199 .mux_clks = core_mux_clks,
2200 .nr_mux_clks = ARRAY_SIZE(core_mux_clks),
2201 .div_clks = core_div_clks,
2202 .nr_div_clks = ARRAY_SIZE(core_div_clks),
2203 .gate_clks = core_gate_clks,
2204 .nr_gate_clks = ARRAY_SIZE(core_gate_clks),
2205 .nr_clk_ids = CLKS_NR_CORE,
2206 .clk_regs = core_clk_regs,
2207 .nr_clk_regs = ARRAY_SIZE(core_clk_regs),
2208 .clk_name = "dout_core_bus",
2209 };
2210
2211 /* ---- CMU_DPU ------------------------------------------------------------- */
2212
2213 /* Register Offset definitions for CMU_DPU (0x13000000) */
2214 #define PLL_CON0_MUX_CLKCMU_DPU_USER 0x0600
2215 #define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800
2216 #define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK 0x2004
2217 #define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0 0x2010
2218 #define CLK_CON_GAT_GOUT_DPU_ACLK_DMA 0x2014
2219 #define CLK_CON_GAT_GOUT_DPU_ACLK_DPP 0x2018
2220 #define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK 0x2028
2221 #define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK 0x202c
2222 #define CLK_CON_GAT_GOUT_DPU_SMMU_CLK 0x2038
2223 #define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK 0x203c
2224
2225 static const unsigned long dpu_clk_regs[] __initconst = {
2226 PLL_CON0_MUX_CLKCMU_DPU_USER,
2227 CLK_CON_DIV_DIV_CLK_DPU_BUSP,
2228 CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK,
2229 CLK_CON_GAT_GOUT_DPU_ACLK_DECON0,
2230 CLK_CON_GAT_GOUT_DPU_ACLK_DMA,
2231 CLK_CON_GAT_GOUT_DPU_ACLK_DPP,
2232 CLK_CON_GAT_GOUT_DPU_PPMU_ACLK,
2233 CLK_CON_GAT_GOUT_DPU_PPMU_PCLK,
2234 CLK_CON_GAT_GOUT_DPU_SMMU_CLK,
2235 CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK,
2236 };
2237
2238 /* List of parent clocks for Muxes in CMU_DPU */
2239 PNAME(mout_dpu_user_p) = { "oscclk", "dout_dpu" };
2240
2241 static const struct samsung_mux_clock dpu_mux_clks[] __initconst = {
2242 MUX(CLK_MOUT_DPU_USER, "mout_dpu_user", mout_dpu_user_p,
2243 PLL_CON0_MUX_CLKCMU_DPU_USER, 4, 1),
2244 };
2245
2246 static const struct samsung_div_clock dpu_div_clks[] __initconst = {
2247 DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_user",
2248 CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3),
2249 };
2250
2251 static const struct samsung_gate_clock dpu_gate_clks[] __initconst = {
2252 /* TODO: Should be enabled in DSIM driver */
2253 GATE(CLK_GOUT_DPU_CMU_DPU_PCLK, "gout_dpu_cmu_dpu_pclk",
2254 "dout_dpu_busp",
2255 CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
2256 GATE(CLK_GOUT_DPU_DECON0_ACLK, "gout_dpu_decon0_aclk", "mout_dpu_user",
2257 CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0),
2258 GATE(CLK_GOUT_DPU_DMA_ACLK, "gout_dpu_dma_aclk", "mout_dpu_user",
2259 CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0),
2260 GATE(CLK_GOUT_DPU_DPP_ACLK, "gout_dpu_dpp_aclk", "mout_dpu_user",
2261 CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0),
2262 GATE(CLK_GOUT_DPU_PPMU_ACLK, "gout_dpu_ppmu_aclk", "mout_dpu_user",
2263 CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0),
2264 GATE(CLK_GOUT_DPU_PPMU_PCLK, "gout_dpu_ppmu_pclk", "dout_dpu_busp",
2265 CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0),
2266 GATE(CLK_GOUT_DPU_SMMU_CLK, "gout_dpu_smmu_clk", "mout_dpu_user",
2267 CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0),
2268 GATE(CLK_GOUT_DPU_SYSREG_PCLK, "gout_dpu_sysreg_pclk", "dout_dpu_busp",
2269 CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0),
2270 };
2271
2272 static const struct samsung_cmu_info dpu_cmu_info __initconst = {
2273 .mux_clks = dpu_mux_clks,
2274 .nr_mux_clks = ARRAY_SIZE(dpu_mux_clks),
2275 .div_clks = dpu_div_clks,
2276 .nr_div_clks = ARRAY_SIZE(dpu_div_clks),
2277 .gate_clks = dpu_gate_clks,
2278 .nr_gate_clks = ARRAY_SIZE(dpu_gate_clks),
2279 .nr_clk_ids = CLKS_NR_DPU,
2280 .clk_regs = dpu_clk_regs,
2281 .nr_clk_regs = ARRAY_SIZE(dpu_clk_regs),
2282 .clk_name = "dout_dpu",
2283 };
2284
2285 /* ---- platform_driver ----------------------------------------------------- */
2286
exynos850_cmu_probe(struct platform_device * pdev)2287 static int __init exynos850_cmu_probe(struct platform_device *pdev)
2288 {
2289 const struct samsung_cmu_info *info;
2290 struct device *dev = &pdev->dev;
2291
2292 info = of_device_get_match_data(dev);
2293 exynos_arm64_register_cmu(dev, dev->of_node, info);
2294
2295 return 0;
2296 }
2297
2298 static const struct of_device_id exynos850_cmu_of_match[] = {
2299 {
2300 .compatible = "samsung,exynos850-cmu-apm",
2301 .data = &apm_cmu_info,
2302 }, {
2303 .compatible = "samsung,exynos850-cmu-aud",
2304 .data = &aud_cmu_info,
2305 }, {
2306 .compatible = "samsung,exynos850-cmu-cmgp",
2307 .data = &cmgp_cmu_info,
2308 }, {
2309 .compatible = "samsung,exynos850-cmu-g3d",
2310 .data = &g3d_cmu_info,
2311 }, {
2312 .compatible = "samsung,exynos850-cmu-hsi",
2313 .data = &hsi_cmu_info,
2314 }, {
2315 .compatible = "samsung,exynos850-cmu-is",
2316 .data = &is_cmu_info,
2317 }, {
2318 .compatible = "samsung,exynos850-cmu-mfcmscl",
2319 .data = &mfcmscl_cmu_info,
2320 }, {
2321 .compatible = "samsung,exynos850-cmu-core",
2322 .data = &core_cmu_info,
2323 }, {
2324 .compatible = "samsung,exynos850-cmu-dpu",
2325 .data = &dpu_cmu_info,
2326 }, {
2327 },
2328 };
2329
2330 static struct platform_driver exynos850_cmu_driver __refdata = {
2331 .driver = {
2332 .name = "exynos850-cmu",
2333 .of_match_table = exynos850_cmu_of_match,
2334 .suppress_bind_attrs = true,
2335 },
2336 .probe = exynos850_cmu_probe,
2337 };
2338
exynos850_cmu_init(void)2339 static int __init exynos850_cmu_init(void)
2340 {
2341 return platform_driver_register(&exynos850_cmu_driver);
2342 }
2343 core_initcall(exynos850_cmu_init);
2344