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/linux/Documentation/devicetree/bindings/regulator/
H A Dtps51632-regulator.txt9 - ti,dvfs-step-20mV: The 20mV step voltage when PWM DVFS enabled. Missing this
10 will set 10mV step voltage in PWM DVFS mode. In normal mode, the voltage
11 step is 10mV as per datasheet.
26 ti,dvfs-step-20mV;
H A Dmediatek,mt6358-regulator.yaml79 description: LDOs with fixed 1.2V output and 0~100/10mV tuning
88 LDOs with fixed 1.8V output and 0~100/10mV tuning (vcn18 on MT6366 has variable output)
96 description: LDOs with fixed 2.2V output and 0~100/10mV tuning
104 description: LDOs with fixed 2.8V output and 0~100/10mV tuning
112 description: LDOs with fixed 3.0V output and 0~100/10mV tuning
128 description: LDOs with variable output and 0~100/10mV tuning
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_aldebaran.h48 #define FEATURE_DS_FCLK_BIT 10
121 #define THORTTLER_SPARE_10 10
292 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
293 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
342 int16_t GFX_Guardband_Voltage_Cold[8]; // mV [signed]
343 int16_t GFX_Guardband_Voltage_Mid[8]; // mV [signed]
344 int16_t GFX_Guardband_Voltage_Hot[8]; // mV [signed]
347 int16_t SOC_Guardband_Voltage_Cold[8]; // mV [signed]
348 int16_t SOC_Guardband_Voltage_Mid[8]; // mV [signed]
349 int16_t SOC_Guardband_Voltage_Hot[8]; // mV [signed]
[all …]
H A Dsmu11_driver_if_navi10.h83 #define FEATURE_DS_GFXCLK_BIT 10
184 #define THROTTLER_TEMP_PLX_BIT 10
465 #define HBM_DIE_TEMPERATURE_THROTTLING_BIT 10
558 uint16_t UlvVoltageOffsetSoc; // In mV(Q2)
559 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
569 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
570 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode
574 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
575 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
576 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
[all …]
H A Dsmu14_driver_if_v14_0.h56 #define FEATURE_DS_GFXCLK_BIT 10
205 #define THROTTLER_TEMP_LIQUID1_BIT 10
229 #define FW_DSTATE_HSR_NON_STROBE_BIT 10
595 MEM_VENDOR_PLACEHOLDER1, // 10
703 #define PP_OD_FEATURE_FCLK_BIT 10
757 uint16_t VddGfxVmax; // in mV
820 uint16_t VddGfxVmax; // in mV
964 uint16_t InitGfx; // In mV(Q2) , should be 0?
965 uint16_t InitSoc; // In mV(Q2)
966 uint16_t InitVddIoMem; // In mV(Q2) MemVdd
[all …]
H A Dsmu11_driver_if_arcturus.h67 #define FEATURE_DS_FCLK_BIT 10
197 #define THROTTLER_PPT1_BIT 10
497 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
504 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
505 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
506 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
507 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
526 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2)
583 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2
588 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2
[all …]
H A Dsmu11_driver_if_sienna_cichlid.h86 #define FEATURE_MEM_VDDCI_SCALING_BIT 10
205 #define THROTTLER_TEMP_PLX_BIT 10
229 #define FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT 10
633 uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS]; // mV(Q2)
636 uint16_t PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //In mV(Q2)
646 uint16_t UlvVoltageOffsetSoc; // In mV(Q2)
647 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
649 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
650 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode
652 uint16_t SocLIVmin; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC
[all …]
H A Dsmu13_driver_if_v13_0_7.h59 #define FEATURE_VDDIO_MEM_SCALING_BIT 10
197 #define THROTTLER_TEMP_LIQUID0_BIT 10
222 #define FW_DSTATE_HSR_NON_STROBE_BIT 10
691 #define PP_OD_FEATURE_TEMPERATURE_BIT 10
872 uint16_t InitGfx; // In mV(Q2) , should be 0?
873 uint16_t InitSoc; // In mV(Q2)
874 uint16_t InitU; // In Mv(Q2) not applicable
928 uint16_t DcTol; // mV Q2
929 uint16_t DcBtcGb; // mV Q2
931 uint16_t DcBtcMin; // mV Q2
[all …]
H A Dsmu13_driver_if_v13_0_0.h58 #define FEATURE_VDDIO_MEM_SCALING_BIT 10
196 #define THROTTLER_TEMP_LIQUID0_BIT 10
221 #define FW_DSTATE_HSR_NON_STROBE_BIT 10
677 #define PP_OD_FEATURE_TEMPERATURE_BIT 10
863 uint16_t InitGfx; // In mV(Q2) , should be 0?
864 uint16_t InitSoc; // In mV(Q2)
865 uint16_t InitU; // In Mv(Q2)
919 uint16_t DcTol; // mV Q2
920 uint16_t DcBtcGb; // mV Q2
922 uint16_t DcBtcMin; // mV Q2
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/volt/
H A Dgk20a.c54 int mv; in gk20a_volt_get_cvb_voltage() local
56 mv = DIV_ROUND_CLOSEST(coef->c2 * speedo, s_scale); in gk20a_volt_get_cvb_voltage()
57 mv = DIV_ROUND_CLOSEST((mv + coef->c1) * speedo, s_scale) + coef->c0; in gk20a_volt_get_cvb_voltage()
58 return mv; in gk20a_volt_get_cvb_voltage()
70 int cvb_mv, mv; in gk20a_volt_get_cvb_t_voltage() local
74 mv = DIV_ROUND_CLOSEST(coef->c3 * speedo, s_scale) + coef->c4 + in gk20a_volt_get_cvb_t_voltage()
76 mv = DIV_ROUND_CLOSEST(mv * temp, t_scale) + cvb_mv; in gk20a_volt_get_cvb_t_voltage()
77 return mv; in gk20a_volt_get_cvb_t_voltage()
84 int mv; in gk20a_volt_calc_voltage() local
86 mv = gk20a_volt_get_cvb_t_voltage(speedo, -10, 100, 10, coef); in gk20a_volt_calc_voltage()
[all …]
/linux/arch/riscv/lib/
H A Duaccess_vector.S27 mv t6, ra
32 mv ra, t6
41 fixup vle8.v vData, (pSrc), 10f
49 10:
50 mv a0, iNum
60 j 10b
/linux/Documentation/devicetree/bindings/phy/
H A Dphy-stm32-usbphyc.yaml103 description: Decreases the HS driver slew rate by 10%
110 - <1> increases the level by 5 to 7 mV
111 - <2> increases the level by 10 to 14 mV
112 - <3> decreases the level by 5 to 7 mV
139 - <10> = 21.82 mA target current / nominal + 15.6%
166 - <1> = threshold shift by +7 mV
167 - <2> = threshold shift by -5 mV
168 - <3> = threshold shift by +14 mV
182 - <1> = offset of +5 mV
183 - <2> = offset of +10 mV
[all …]
/linux/Documentation/hwmon/
H A Dina209.rst40 in0_input shunt voltage (mV)
41 in0_input_highest shunt voltage historical maximum reading (mV)
42 in0_input_lowest shunt voltage historical minimum reading (mV)
44 in0_max shunt voltage max alarm limit (mV)
45 in0_min shunt voltage min alarm limit (mV)
46 in0_crit_max shunt voltage crit max alarm limit (mV)
47 in0_crit_min shunt voltage crit min alarm limit (mV)
53 in1_input bus voltage (mV)
54 in1_input_highest bus voltage historical maximum reading (mV)
55 in1_input_lowest bus voltage historical minimum reading (mV)
[all …]
H A Dvt1211.rst82 Voltages are sampled by an 8-bit ADC with a LSB of ~10mV. The supported input
98 +2.5V 2K 10K 1.2 2083 mV
99 VccP --- --- 1.0 1400 mV [1]_
100 +5V 14K 10K 2.4 2083 mV
101 +12V 47K 10K 5.7 2105 mV
102 +3.3V (int) 2K 3.4K 1.588 3300 mV [2]_
103 +3.3V (ext) 6.8K 10K 1.68 1964 mV
157 Vpin = 2200 * Rth / (Rs + Rth) (2200 is the ADC max limit of 2200 mV)
H A Dxdpe12284.rst41 - VR12.0 mode, 5-mV DAC - 0x01.
42 - VR12.5 mode, 10-mV DAC - 0x02.
43 - IMVP9 mode, 5-mV DAC - 0x03.
44 - AMD mode 6.25mV - 0x10.
H A Dmc13783-adc.rst29 Among other things they contain a 10-bit A/D converter. The converter has 16
31 A/D converter has a resolution of 2.25mV.
48 1 Battery Current (BATT - BATTISNS) -50 - 50 mV x20
50 3 Charger Voltage (CHRGRAW) 0 - 10V / /5
51 0 - 20V /10
60 10 General Purpose ADIN10 0 - 2.30V No
74 1 Battery Current (BATT - BATTISNSCC) -60 - 60 mV x20
77 0 - 20V /10
/linux/Documentation/devicetree/bindings/sound/
H A Dcs35l33.txt22 0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with
23 a value of 1 and will increase at a step size of 100mV until a maximum of
24 8000mV.
62 stage enters LDO operation. Starts as a default value of 50mV for a value
63 of 1 and increases with a step size of 50mV to a maximum of 750mV (value of
72 from 0 to 7 for delays of 5ms, 10ms, 50ms, 100ms, 200ms, 500ms, 1000ms.
80 The reference voltage starts at 3000mV with a value of 0x3 and is increased
81 by 100mV per step to a maximum of 5500mV.
91 1800mV with a step size of 50mV up to a maximum value of 1750mV.
92 Default is 1800mV.
[all …]
H A Dcs35l36.txt14 converter's output voltage in mV. The range is from 2550mV to 12000mV with
15 increments of 50mV.
66 2 = 10ms
75 weak-FET operation. The range is 50mV to 700mV in 50mV increments.
/linux/drivers/cpufreq/
H A Dlonghaul.c82 /* Clock ratios multiplied by 10 */
111 khz = (mult/10)*fsb; in calc_speed()
112 if (mult%10) in calc_speed()
276 fsb, mult/10, mult%10, print_speed(speed/1000)); in longhaul_setstate()
419 return speeds[i] / 10; in guess_fsb()
460 minmult/10, minmult%10, maxmult/10, maxmult%10); in longhaul_get_ranges()
557 if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) { in longhaul_setup_voltagescaling()
559 minvid.mV/1000, minvid.mV%1000, in longhaul_setup_voltagescaling()
560 maxvid.mV/1000, maxvid.mV%1000); in longhaul_setup_voltagescaling()
564 if (minvid.mV == maxvid.mV) { in longhaul_setup_voltagescaling()
[all …]
/linux/drivers/scsi/
H A Dch.c301 u_char cmd[10], data[16]; in ch_readconfig()
315 result = ch_do_scsi(ch, cmd, 10, buffer, 255, REQ_OP_DRV_IN); in ch_readconfig()
318 result = ch_do_scsi(ch, cmd, 10, buffer, 255, REQ_OP_DRV_IN); in ch_readconfig()
326 (buffer[buffer[3]+10] << 8) | buffer[buffer[3]+11]; in ch_readconfig()
429 u_char cmd[10]; in ch_position()
442 return ch_do_scsi(ch, cmd, 10, NULL, 0, REQ_OP_DRV_IN); in ch_position()
462 cmd[10] = rotate ? 1 : 0; in ch_move()
487 cmd[10] = (rotate1 ? 1 : 0) | (rotate2 ? 2 : 0); in ch_exchange()
710 struct changer_move mv; in ch_ioctl() local
712 if (copy_from_user(&mv, argp, sizeof (mv))) in ch_ioctl()
[all …]
/linux/Documentation/power/regulator/
H A Doverview.rst100 - voltage output is in the range 800mV -> 3500mV.
102 10mA @ 10V.
108 - Domain-1 voltage is 3300mV
109 - Domain-2 voltage is 1400mV -> 1600mV
116 from 5mA to 10mA to increase LCD illumination. This passes
/linux/drivers/media/platform/rockchip/rkvdec/
H A Drkvdec-vp9.c38 struct rkvdec_vp9_intra_mode_probs intra_mode[10];
62 u8 classes[2][10];
64 u8 bits[2][10];
69 } mv; member
109 u32 y_mode[4][10];
110 u32 uv_mode[10][10];
121 u32 bits[2][10][2];
290 /* mv related 6 x 128 */ in init_inter_probs()
291 memcpy(rkprobs->mv.joint, probs->mv.joint, in init_inter_probs()
292 sizeof(rkprobs->mv.joint)); in init_inter_probs()
[all …]
/linux/drivers/media/v4l2-core/
H A Dv4l2-vp9.c14 const u8 v4l2_vp9_kf_y_mode_prob[10][10][9] = {
154 const u8 v4l2_vp9_kf_uv_mode_prob[10][9] = {
307 { 10, 70, 135 },
356 { 10, 103, 177 },
364 { 10, 104, 178 },
417 { 10, 131, 185 },
609 { 10, 54, 86 },
718 { 10, 98, 150 },
817 { 1, 10, 16 },
844 { 10, 222, 223 },
[all …]
/linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_vp9_req_lat_if.c54 u8 classes[10];
59 u8 bits[10];
70 u8 uv_mode_prob[10][16];
111 u32 uv_mode[10][10];
127 u32 bits[10][2];
155 u32 y_mode[4][10];
160 u32 bits[2][10][2];
340 * @mv: mv working buffer
359 struct vdec_vp9_slice_mem mv[2]; member
429 * @mv: mv working buffer
[all …]
/linux/include/linux/regulator/
H A Dtps51632-regulator.h21 * @dvfs_step_20mV: Step for DVFS is 20mV or 10mV.

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