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Searched +full:0 +full:xd4 (Results 1 – 25 of 496) sorted by relevance

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/linux/drivers/ufs/host/
H A Dufs-renesas.c39 ufshcd_dump_regs(hba, 0xc0, 0x40, "regs: 0xc0 + "); in ufs_renesas_dbg_register_dump()
67 ufs_renesas_write(hba, 0xd0, data_d0); in ufs_renesas_write_d0_d4()
68 ufs_renesas_write(hba, 0xd4, data_d4); in ufs_renesas_write_d0_d4()
74 ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100); in ufs_renesas_write_800_80c_poll()
75 ufs_renesas_write_d0_d4(hba, 0x00000800, (data_800 << 16) | BIT(8) | addr); in ufs_renesas_write_800_80c_poll()
76 ufs_renesas_write(hba, 0xd0, 0x0000080c); in ufs_renesas_write_800_80c_poll()
77 ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8)); in ufs_renesas_write_800_80c_poll()
82 ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100); in ufs_renesas_write_804_80c_poll()
83 ufs_renesas_write_d0_d4(hba, 0x00000804, (data_804 << 16) | BIT(8) | addr); in ufs_renesas_write_804_80c_poll()
84 ufs_renesas_write(hba, 0xd0, 0x0000080c); in ufs_renesas_write_804_80c_poll()
[all …]
/linux/fs/unicode/
H A Dutf8data.c_shipped8 0,
9 0x10100,
10 0x20000,
11 0x20100,
12 0x30000,
13 0x30100,
14 0x30200,
15 0x40000,
16 0x40100,
17 0x50000,
[all …]
/linux/drivers/scsi/aic7xxx/
H A Daic7xxx_seq.h_shipped9 0xb2, 0x00, 0x00, 0x08,
10 0xf7, 0x11, 0x22, 0x08,
11 0x00, 0x65, 0xee, 0x59,
12 0xf7, 0x01, 0x02, 0x08,
13 0xff, 0x6a, 0x24, 0x08,
14 0x40, 0x00, 0x40, 0x68,
15 0x08, 0x1f, 0x3e, 0x10,
16 0x40, 0x00, 0x40, 0x68,
17 0xff, 0x40, 0x3c, 0x60,
18 0x08, 0x1f, 0x3e, 0x10,
[all …]
H A Daic79xx_seq.h_shipped9 0xff, 0x02, 0x06, 0x78,
10 0x00, 0xea, 0x6e, 0x59,
11 0x01, 0xea, 0x04, 0x30,
12 0xff, 0x04, 0x0c, 0x78,
13 0x19, 0xea, 0x6e, 0x59,
14 0x19, 0xea, 0x04, 0x00,
15 0x33, 0xea, 0x68, 0x59,
16 0x33, 0xea, 0x00, 0x00,
17 0x60, 0x3a, 0x3a, 0x68,
18 0x04, 0x4d, 0x35, 0x78,
[all …]
/linux/arch/arm/mach-footbridge/
H A Ddma-isa.c24 #define ISA_DMA_MASK 0
34 { 0x0a, 0x0b, 0x0c, 0x487, 0x087, 0x00, 0x01 },
35 { 0x0a, 0x0b, 0x0c, 0x483, 0x083, 0x02, 0x03 },
36 { 0x0a, 0x0b, 0x0c, 0x481, 0x081, 0x04, 0x05 },
37 { 0x0a, 0x0b, 0x0c, 0x482, 0x082, 0x06, 0x07 },
38 { 0xd4, 0xd6, 0xd8, 0x000, 0x000, 0xc0, 0xc2 },
39 { 0xd4, 0xd6, 0xd8, 0x48b, 0x08b, 0xc4, 0xc6 },
40 { 0xd4, 0xd6, 0xd8, 0x489, 0x089, 0xc8, 0xca },
41 { 0xd4, 0xd6, 0xd8, 0x48a, 0x08a, 0xcc, 0xce }
57 .coherent_dma_mask = ~(dma_addr_t)0,
[all …]
/linux/drivers/hid/
H A Dhid-uclogic-core-test.c22 .event = { 0xA1, 0xB2, 0xC3, 0xD4 },
26 .event = { 0x1F, 0x2E, 0x3D, 0x4C, 0x5B, 0x6A },
33 .event = { 0xA1, 0xB2, 0xC3, 0xD4 },
38 .event = { 0x1F, 0x2E, 0x3D, 0x4C, 0x5B, 0x6A },
43 .event = { 0xA1, 0xB2, 0xC3 },
48 .event = { 0xA1, 0xB2, 0xC3, 0xD4, 0x00 },
53 .event = { 0x2E, 0x3D, 0x4C, 0x5B, 0x6A, 0x1F },
66 struct uclogic_params p = {0, }; in hid_test_uclogic_exec_event_hook_test()
76 for (n = 0; n < ARRAY_SIZE(hook_events); n++) { in hid_test_uclogic_exec_event_hook_test()
83 memcpy(filter->event, &hook_events[n].event[0], filter->size); in hid_test_uclogic_exec_event_hook_test()
[all …]
/linux/lib/crypto/tests/
H A Dsha384-testvecs.h9 .data_len = 0,
11 0x38, 0xb0, 0x60, 0xa7, 0x51, 0xac, 0x96, 0x38,
12 0x4c, 0xd9, 0x32, 0x7e, 0xb1, 0xb1, 0xe3, 0x6a,
13 0x21, 0xfd, 0xb7, 0x11, 0x14, 0xbe, 0x07, 0x43,
14 0x4c, 0x0c, 0xc7, 0xbf, 0x63, 0xf6, 0xe1, 0xda,
15 0x27, 0x4e, 0xde, 0xbf, 0xe7, 0x6f, 0x65, 0xfb,
16 0xd5, 0x1a, 0xd2, 0xf1, 0x48, 0x98, 0xb9, 0x5b,
22 0x07, 0x34, 0x9d, 0x74, 0x48, 0x76, 0xa5, 0x72,
23 0x78, 0x02, 0xb8, 0x6e, 0x21, 0x59, 0xb0, 0x75,
24 0x09, 0x68, 0x11, 0x39, 0x53, 0x61, 0xee, 0x8d,
[all …]
H A Dpolyval-testvecs.h9 .data_len = 0,
11 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
12 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
18 0xb5, 0x51, 0x69, 0x89, 0xd4, 0x3c, 0x59, 0xca,
19 0x6a, 0x1c, 0x2a, 0xe9, 0xa1, 0x9c, 0x6c, 0x83,
25 0xf4, 0x50, 0xaf, 0x07, 0xda, 0x42, 0xa7, 0x41,
26 0x4d, 0x24, 0x88, 0x87, 0xe3, 0x40, 0x73, 0x7c,
32 0x9e, 0x88, 0x78, 0x71, 0x4c, 0x55, 0x87, 0xe8,
33 0xb4, 0x96, 0x3d, 0x56, 0xc8, 0xb2, 0xe1, 0x68,
39 0x9e, 0x81, 0x37, 0x8f, 0x49, 0xf7, 0xa2, 0xe4,
[all …]
H A Dblake2b-testvecs.h9 .data_len = 0,
11 0x78, 0x6a, 0x02, 0xf7, 0x42, 0x01, 0x59, 0x03,
12 0xc6, 0xc6, 0xfd, 0x85, 0x25, 0x52, 0xd2, 0x72,
13 0x91, 0x2f, 0x47, 0x40, 0xe1, 0x58, 0x47, 0x61,
14 0x8a, 0x86, 0xe2, 0x17, 0xf7, 0x1f, 0x54, 0x19,
15 0xd2, 0x5e, 0x10, 0x31, 0xaf, 0xee, 0x58, 0x53,
16 0x13, 0x89, 0x64, 0x44, 0x93, 0x4e, 0xb0, 0x4b,
17 0x90, 0x3a, 0x68, 0x5b, 0x14, 0x48, 0xb7, 0x55,
18 0xd5, 0x6f, 0x70, 0x1a, 0xfe, 0x9b, 0xe2, 0xce,
24 0x6f, 0x2e, 0xcc, 0x83, 0x53, 0xa3, 0x20, 0x16,
[all …]
/linux/drivers/gpu/drm/gma500/
H A Dgma_device.c17 0, 0); in gma_get_core_freq()
20 /*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/ in gma_get_core_freq()
21 /*pci_write_config_dword(pci_root, 0xD0, 0xE0033000);*/ in gma_get_core_freq()
23 pci_write_config_dword(pci_root, 0xD0, 0xD0050300); in gma_get_core_freq()
24 pci_read_config_dword(pci_root, 0xD4, &clock); in gma_get_core_freq()
27 switch (clock & 0x07) { in gma_get_core_freq()
28 case 0: in gma_get_core_freq()
49 dev_priv->core_freq = 0; in gma_get_core_freq()
/linux/drivers/pcmcia/
H A Do2micro.h35 #define O2_MUX_CONTROL 0x90 /* 32 bit */
36 #define O2_MUX_RING_OUT 0x0000000f
37 #define O2_MUX_SKTB_ACTV 0x000000f0
38 #define O2_MUX_SCTA_ACTV_ENA 0x00000100
39 #define O2_MUX_SCTB_ACTV_ENA 0x00000200
40 #define O2_MUX_SER_IRQ_ROUTE 0x0000e000
41 #define O2_MUX_SER_PCI 0x00010000
43 #define O2_MUX_SKTA_TURBO 0x000c0000 /* for 6833, 6860 */
44 #define O2_MUX_SKTB_TURBO 0x00300000
45 #define O2_MUX_AUX_VCC_3V 0x00400000
[all …]
/linux/arch/x86/kernel/cpu/microcode/
H A Damd_shas.c3 { 0x8001227, {
4 0x99,0xc0,0x9b,0x2b,0xcc,0x9f,0x52,0x1b,
5 0x1a,0x5f,0x1d,0x83,0xa1,0x6c,0xc4,0x46,
6 0xe2,0x6c,0xda,0x73,0xfb,0x2d,0x23,0xa8,
7 0x77,0xdc,0x15,0x31,0x33,0x4a,0x46,0x18,
10 { 0x8001250, {
11 0xc0,0x0b,0x6b,0x19,0xfd,0x5c,0x39,0x60,
12 0xd5,0xc3,0x57,0x46,0x54,0xe4,0xd1,0xaa,
13 0xa8,0xf7,0x1f,0xa8,0x6a,0x60,0x3e,0xe3,
14 0x27,0x39,0x8e,0x53,0x30,0xf8,0x49,0x19,
[all …]
/linux/fs/nls/
H A Dnls_cp950.c17 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x00-0x07 */
18 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x08-0x0F */
19 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x10-0x17 */
20 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x18-0x1F */
21 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x20-0x27 */
22 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x28-0x2F */
23 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x30-0x37 */
24 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x38-0x3F */
25 0x3000,0xFF0C,0x3001,0x3002,0xFF0E,0x2027,0xFF1B,0xFF1A,/* 0x40-0x47 */
26 0xFF1F,0xFF01,0xFE30,0x2026,0x2025,0xFE50,0xFE51,0xFE52,/* 0x48-0x4F */
[all …]
H A Dnls_cp936.c17 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x00-0x07 */
18 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x08-0x0F */
19 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x10-0x17 */
20 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x18-0x1F */
21 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x20-0x27 */
22 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x28-0x2F */
23 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x30-0x37 */
24 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x38-0x3F */
25 0x4E02,0x4E04,0x4E05,0x4E06,0x4E0F,0x4E12,0x4E17,0x4E1F,/* 0x40-0x47 */
26 0x4E20,0x4E21,0x4E23,0x4E26,0x4E29,0x4E2E,0x4E2F,0x4E31,/* 0x48-0x4F */
[all …]
H A Dnls_euc-jp.c17 #define IS_SJIS_LOW_BYTE(l) ((0x40 <= (l)) && ((l) <= 0xFC) && ((l) != 0x7F))
19 #define IS_SJIS_JISX0208(h, l) ((((0x81 <= (h)) && ((h) <= 0x9F)) \
20 || ((0xE0 <= (h)) && ((h) <= 0xEA))) \
22 #define IS_SJIS_JISX0201KANA(c) ((0xA1 <= (c)) && ((c) <= 0xDF))
23 #define IS_SJIS_UDC_LOW(h, l) (((0xF0 <= (h)) && ((h) <= 0xF4)) \
25 #define IS_SJIS_UDC_HI(h, l) (((0xF5 <= (h)) && ((h) <= 0xF9)) \
27 #define IS_SJIS_IBM(h, l) (((0xFA <= (h)) && ((h) <= 0xFC)) \
29 #define IS_SJIS_NECIBM(h, l) (((0xED <= (h)) && ((h) <= 0xEE)) \
32 if ((sjis_lo) >= 0x9F) { \
37 (euc_lo) = (sjis_lo) + ((sjis_lo) >= 0x7F ? 0x60 : 0x61); \
[all …]
H A Dnls_cp949.c17 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x00-0x07 */
18 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x08-0x0F */
19 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x10-0x17 */
20 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x18-0x1F */
21 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x20-0x27 */
22 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x28-0x2F */
23 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x30-0x37 */
24 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x38-0x3F */
25 0x0000,0xAC02,0xAC03,0xAC05,0xAC06,0xAC0B,0xAC0C,0xAC0D,/* 0x40-0x47 */
26 0xAC0E,0xAC0F,0xAC18,0xAC1E,0xAC1F,0xAC21,0xAC22,0xAC23,/* 0x48-0x4F */
[all …]
/linux/drivers/media/usb/gspca/
H A Dtopro.c22 0xff, 0xd8, /* jpeg */
25 0xff, 0xdb, 0x00, 0x84, /* DQT */
26 0,
28 0x10, 0x0b, 0x0c, 0x0e, 0x0c, 0x0a, 0x10, 0x0e,
29 0x0d, 0x0e, 0x12, 0x11, 0x10, 0x13, 0x18, 0x28,
30 0x1a, 0x18, 0x16, 0x16, 0x18, 0x31, 0x23, 0x25,
31 0x1d, 0x28, 0x3a, 0x33, 0x3d, 0x3c, 0x39, 0x33,
32 0x38, 0x37, 0x40, 0x48, 0x5c, 0x4e, 0x40, 0x44,
33 0x57, 0x45, 0x37, 0x38, 0x50, 0x6d, 0x51, 0x57,
34 0x5f, 0x62, 0x67, 0x68, 0x67, 0x3e, 0x4d, 0x71,
[all …]
/linux/drivers/platform/x86/
H A Dmsi-ec.c51 .address = 0xef,
52 .offset_start = 0x8a,
53 .offset_end = 0x80,
54 .range_min = 0x8a,
55 .range_max = 0xe4,
58 .address = 0x2e,
59 .block_address = 0x2f,
63 .address = 0xbf,
67 .address = 0x98,
71 .address = 0xf2,
[all …]
/linux/include/dt-bindings/clock/
H A Dam3.h8 #define AM3_CLKCTRL_OFFSET 0x0
12 #define AM3_L4LS_CLKCTRL_OFFSET 0x38
14 #define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38)
15 #define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c)
16 #define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40)
17 #define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44)
18 #define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48)
19 #define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c)
20 #define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50)
21 #define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60)
[all …]
/linux/drivers/gpu/drm/panel/
H A Dpanel-himax-hx83121a.c26 module_param(enable_dsc, bool, 0);
76 return ctx->desc->is_dual_dsi ? ctx->dsi[1] : ctx->dsi[0]; in to_primary_dsi()
83 gpiod_set_value_cansleep(ctx->reset_gpio, 0); in himax_reset()
97 if (ret < 0) in himax_prepare()
109 if (ret < 0) { in himax_prepare()
142 if (ret < 0) in himax_unprepare()
148 return 0; in himax_unprepare()
163 for (i = 0; i < num_modes; i++) { in himax_get_modes()
175 if (i == 0) in himax_get_modes()
199 int ret = 0; in himax_bl_update_status()
[all …]
/linux/lib/crc/
H A Dcrc7.c18 0x00, 0x12, 0x24, 0x36, 0x48, 0x5a, 0x6c, 0x7e,
19 0x90, 0x82, 0xb4, 0xa6, 0xd8, 0xca, 0xfc, 0xee,
20 0x32, 0x20, 0x16, 0x04, 0x7a, 0x68, 0x5e, 0x4c,
21 0xa2, 0xb0, 0x86, 0x94, 0xea, 0xf8, 0xce, 0xdc,
22 0x64, 0x76, 0x40, 0x52, 0x2c, 0x3e, 0x08, 0x1a,
23 0xf4, 0xe6, 0xd0, 0xc2, 0xbc, 0xae, 0x98, 0x8a,
24 0x56, 0x44, 0x72, 0x60, 0x1e, 0x0c, 0x3a, 0x28,
25 0xc6, 0xd4, 0xe2, 0xf0, 0x8e, 0x9c, 0xaa, 0xb8,
26 0xc8, 0xda, 0xec, 0xfe, 0x80, 0x92, 0xa4, 0xb6,
27 0x58, 0x4a, 0x7c, 0x6e, 0x10, 0x02, 0x34, 0x26,
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-ln-shrd-v6.h9 #define QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL 0xa0
10 #define QSERDES_V6_LN_SHRD_RX_Q_EN_RATES 0xb0
11 #define QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1 0xb4
12 #define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1 0xc4
13 #define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2 0xc8
14 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0 0xd4
15 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1 0xd8
16 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2 0xdc
17 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3 0xe0
18 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4 0xe4
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-ufs-v8.h9 #define QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_TX (0x34)
10 #define QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_RX (0x38)
11 #define QSERDES_UFS_V8_TX_LANE_MODE_1 (0x80)
12 #define QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE2 (0x1bc)
13 #define QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE4 (0x1c4)
14 #define QSERDES_UFS_V8_RX_UCDR_SO_GAIN_RATE4 (0x1dc)
15 #define QSERDES_UFS_V8_RX_EQ_OFFSET_ADAPTOR_CNTRL1 (0x2c8)
16 #define QSERDES_UFS_V8_RX_UCDR_PI_CONTROLS (0x1e4)
17 #define QSERDES_UFS_V8_RX_OFFSET_ADAPTOR_CNTRL3 (0x2d0)
18 #define QSERDES_UFS_V8_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 (0x120)
[all …]
/linux/arch/powerpc/include/uapi/asm/
H A Dtm.h7 * the failure is persistent. PAPR saves 0xff-0xe0 for the hypervisor.
9 #define TM_CAUSE_PERSISTENT 0x01
10 #define TM_CAUSE_KVM_RESCHED 0xe0 /* From PAPR */
11 #define TM_CAUSE_KVM_FAC_UNAV 0xe2 /* From PAPR */
12 #define TM_CAUSE_RESCHED 0xde
13 #define TM_CAUSE_TLBI 0xdc
14 #define TM_CAUSE_FAC_UNAV 0xda
15 #define TM_CAUSE_SYSCALL 0xd8
16 #define TM_CAUSE_MISC 0xd6 /* future use */
17 #define TM_CAUSE_SIGNAL 0xd4
[all …]
/linux/drivers/regulator/
H A Dda9210-regulator.h15 #define DA9210_REG_PAGE_CON 0x00
18 #define DA9210_REG_STATUS_A 0x50
19 #define DA9210_REG_STATUS_B 0x51
20 #define DA9210_REG_EVENT_A 0x52
21 #define DA9210_REG_EVENT_B 0x53
22 #define DA9210_REG_MASK_A 0x54
23 #define DA9210_REG_MASK_B 0x55
24 #define DA9210_REG_CONTROL_A 0x56
27 #define DA9210_REG_GPIO_0_1 0x58
28 #define DA9210_REG_GPIO_2_3 0x59
[all …]

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