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Searched +full:0 +full:xd (Results 1 – 25 of 850) sorted by relevance

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/linux/drivers/thunderbolt/
H A D	xdomain.c	82 UUID_INIT(0xb638d70e, 0x42ff, 0x40bb, 83 0x97, 0xc2, 0x90, 0xe2, 0xc0, 0xb2, 0xf 165 tb_xdomain_response(struct tb_xdomain * xd,const void * response,size_t size,enum tb_cfg_pkg_type type) tb_xdomain_response() argument 217 tb_xdomain_request(struct tb_xdomain * xd,const void * request,size_t request_size,enum tb_cfg_pkg_type request_type,void * response,size_t response_size,enum tb_cfg_pkg_type response_type,unsigned int timeout_msec) tb_xdomain_request() argument 415 tb_xdp_properties_response(struct tb * tb,struct tb_ctl * ctl,struct tb_xdomain * xd,u8 sequence,const struct tb_xdp_properties * req) tb_xdp_properties_response() argument 538 tb_xdp_link_state_status_response(struct tb * tb,struct tb_ctl * ctl,struct tb_xdomain * xd,u8 sequence) tb_xdp_link_state_status_response() argument 648 update_property_block(struct tb_xdomain * xd) update_property_block() argument 708 start_handshake(struct tb_xdomain * xd) start_handshake() argument 716 __stop_handshake(struct tb_xdomain * xd) __stop_handshake() argument 723 stop_handshake(struct tb_xdomain * xd) stop_handshake() argument 736 struct tb_xdomain xd; tb_xdp_handle_request() local 1001 struct tb_xdomain xd = tb_service_parent(svc); tb_service_release() local 1019 struct tb_xdomain xd = data; remove_missing_service() local 1072 enumerate_services(struct tb_xdomain xd) enumerate_services() argument 1127 populate_properties(struct tb_xdomain * xd,struct tb_property_dir * dir) populate_properties() argument 1167 tb_xdomain_update_link_attributes(struct tb_xdomain * xd) tb_xdomain_update_link_attributes() argument 1199 tb_xdomain_get_uuid(struct tb_xdomain * xd) tb_xdomain_get_uuid() argument 1252 tb_xdomain_get_link_status(struct tb_xdomain * xd) tb_xdomain_get_link_status() argument 1284 tb_xdomain_link_state_change(struct tb_xdomain * xd,unsigned int width) tb_xdomain_link_state_change() argument 1325 tb_xdomain_bond_lanes_uuid_high(struct tb_xdomain * xd) tb_xdomain_bond_lanes_uuid_high() argument 1386 tb_xdomain_get_properties(struct tb_xdomain * xd) tb_xdomain_get_properties() argument 1501 tb_xdomain_queue_uuid(struct tb_xdomain * xd) tb_xdomain_queue_uuid() argument 1509 tb_xdomain_queue_link_status(struct tb_xdomain * xd) tb_xdomain_queue_link_status() argument 1517 tb_xdomain_queue_link_status2(struct tb_xdomain * xd) tb_xdomain_queue_link_status2() argument 1525 tb_xdomain_queue_bonding(struct tb_xdomain * xd) tb_xdomain_queue_bonding() argument 1540 tb_xdomain_queue_bonding_uuid_low(struct tb_xdomain * xd) tb_xdomain_queue_bonding_uuid_low() argument 1548 tb_xdomain_queue_properties(struct tb_xdomain * xd) tb_xdomain_queue_properties() argument 1556 tb_xdomain_queue_properties_changed(struct tb_xdomain * xd) tb_xdomain_queue_properties_changed() argument 1563 tb_xdomain_failed(struct tb_xdomain * xd) tb_xdomain_failed() argument 1572 struct tb_xdomain xd = container_of(work, typeof(xd), state_work.work); tb_xdomain_state_work() local 1690 struct tb_xdomain xd = container_of(work, typeof(xd), tb_xdomain_properties_changed() local 1716 struct tb_xdomain xd = container_of(dev, struct tb_xdomain, dev); device_show() local 1725 struct tb_xdomain xd = container_of(dev, struct tb_xdomain, dev); device_name_show() local 1740 struct tb_xdomain xd = container_of(dev, struct tb_xdomain, dev); maxhopid_show() local 1749 struct tb_xdomain xd = container_of(dev, struct tb_xdomain, dev); vendor_show() local 1758 struct tb_xdomain xd = container_of(dev, struct tb_xdomain, dev); vendor_name_show() local 1773 struct tb_xdomain xd = container_of(dev, struct tb_xdomain, dev); unique_id_show() local 1782 struct tb_xdomain xd = container_of(dev, struct tb_xdomain, dev); speed_show() local 1793 struct tb_xdomain xd = container_of(dev, struct tb_xdomain, dev); rx_lanes_show() local 1819 struct tb_xdomain xd = container_of(dev, struct tb_xdomain, dev); tx_lanes_show() local 1867 struct tb_xdomain xd = container_of(dev, struct tb_xdomain, dev); tb_xdomain_release() local 1907 tb_xdomain_link_init(struct tb_xdomain * xd,struct tb_port * down) tb_xdomain_link_init() argument 1924 tb_xdomain_link_exit(struct tb_xdomain * xd) tb_xdomain_link_exit() argument 1970 struct tb_xdomain xd; tb_xdomain_alloc() local 2045 tb_xdomain_add(struct tb_xdomain xd) tb_xdomain_add() argument 2065 tb_xdomain_remove(struct tb_xdomain * xd) tb_xdomain_remove() argument 2102 tb_xdomain_lane_bonding_enable(struct tb_xdomain * xd) tb_xdomain_lane_bonding_enable() argument 2154 tb_xdomain_lane_bonding_disable(struct tb_xdomain * xd) tb_xdomain_lane_bonding_disable() argument 2189 tb_xdomain_alloc_in_hopid(struct tb_xdomain * xd,int hopid) tb_xdomain_alloc_in_hopid() argument 2215 tb_xdomain_alloc_out_hopid(struct tb_xdomain * xd,int hopid) tb_xdomain_alloc_out_hopid() argument 2232 tb_xdomain_release_in_hopid(struct tb_xdomain * xd,int hopid) tb_xdomain_release_in_hopid() argument 2243 tb_xdomain_release_out_hopid(struct tb_xdomain * xd,int hopid) tb_xdomain_release_out_hopid() argument 2264 tb_xdomain_enable_paths(struct tb_xdomain * xd,int transmit_path,int transmit_ring,int receive_path,int receive_ring) tb_xdomain_enable_paths() argument 2289 tb_xdomain_disable_paths(struct tb_xdomain * xd,int transmit_path,int transmit_ring,int receive_path,int receive_ring) tb_xdomain_disable_paths() argument 2312 struct tb_xdomain xd; switch_find_xdomain() local 2358 struct tb_xdomain xd; tb_xdomain_find_by_uuid() local 2390 struct tb_xdomain xd; tb_xdomain_find_by_link_depth() local 2420 struct tb_xdomain xd; tb_xdomain_find_by_route() local 2475 struct tb_xdomain *xd; update_xdomain() local [all...]
H A D	icm.c	27 #define PCIE2CIO_CMD 0x30 36 #define PCIE2CIO_WRDATA 0x34 37 #define PCIE2CIO_RDDATA 0x38 39 #define PHY_PORT_CS1 0x37 75 * @max_boot_acl: Maximum number of preboot ACL entries (%0 if not supported) 138 #define EP_NAME_INTEL_VSS 0x10 150 #define INTEL_VSS_FLAGS_RTD3 BIT(0) 199 return link ? ((link - 1) ^ 0x01) + 1 : 0; in dual_link_from_link() 210 return depth ? route & ~(0xffUL in get_parent_route() 383 icm_xdomain_activated(struct tb_xdomain * xd,bool activated) icm_xdomain_activated() argument 582 icm_fr_approve_xdomain_paths(struct tb * tb,struct tb_xdomain * xd,int transmit_path,int transmit_ring,int receive_path,int receive_ring) icm_fr_approve_xdomain_paths() argument 613 icm_fr_disconnect_xdomain_paths(struct tb * tb,struct tb_xdomain * xd,int transmit_path,int transmit_ring,int receive_path,int receive_ring) icm_fr_disconnect_xdomain_paths() argument 708 struct tb_xdomain xd; add_xdomain() local 728 update_xdomain(struct tb_xdomain xd,u64 route,u8 link) update_xdomain() argument 735 remove_xdomain(struct tb_xdomain * xd) remove_xdomain() argument 754 struct tb_xdomain xd; icm_fr_device_connected() local 931 struct tb_xdomain xd; icm_fr_xdomain_connected() local 1017 struct tb_xdomain xd; icm_fr_xdomain_disconnected() local 1152 icm_tr_approve_xdomain_paths(struct tb tb,struct tb_xdomain * xd,int transmit_path,int transmit_ring,int receive_path,int receive_ring) icm_tr_approve_xdomain_paths() argument 1183 icm_tr_xdomain_tear_down(struct tb * tb,struct tb_xdomain * xd,int stage) icm_tr_xdomain_tear_down() argument 1209 icm_tr_disconnect_xdomain_paths(struct tb * tb,struct tb_xdomain * xd,int transmit_path,int transmit_ring,int receive_path,int receive_ring) icm_tr_disconnect_xdomain_paths() argument 1237 struct tb_xdomain xd; __icm_tr_device_connected() local 1360 struct tb_xdomain xd; icm_tr_xdomain_connected() local 1414 struct tb_xdomain *xd; icm_tr_xdomain_disconnected() local [all...]
H A D	dma_test.c	19 #define DMA_TEST_DATA_PATTERN 0x0123456789abcdefLL 72 * @xd: XDomain the service belongs to 81 * @link_speed: Expected link speed (Gb/s), %0 to use whatever is negotiated 82 * @link_width: Expected link width (Gb/s), %0 to use whatever is negotiated 93 struct tb_xdomain xd; 114 UUID_INIT(0x3188cd10, 0x6523, 0x4a5a, 115 0xa6, 0x8 94 struct tb_xdomain xd; global() member 139 struct tb_xdomain xd = dt->xd; dma_test_start_rings() local 638 struct tb_xdomain xd = tb_service_parent(svc); dma_test_probe() local [all...]
/linux/fs/jffs2/
H A D	xattr.c	`32 * is_xattr_datum_unchecked(c, xd) 34 * unchecked, it returns 0. 35 * unload_xattr_datum(c, xd) 41 * do_verify_xattr_datum(c, xd) 45 * 0 will be returned, if success. An negative return value means recoverable error, and 48 * do_load_xattr_datum(c, xd) 51 * load_xattr_datum(c, xd) 53 * If xd need to call do_verify_xattr_datum() at first, it's called before calling 55 * save_xattr_datum(c, xd) 56 * is used to write xdatum to medium. xd->version will be incremented. [all …]`
/linux/drivers/dma/
H A D	uniphier-xdmac.c	`20 #define XDMAC_CH_WIDTH 0x100 22 #define XDMAC_TFA 0x08 24 #define XDMAC_TFA_MASK GENMASK(5, 0) 25 #define XDMAC_SADM 0x10 29 #define XDMAC_SADM_SAM_INC 0 30 #define XDMAC_DADM 0x14 35 #define XDMAC_EXSAD 0x18 36 #define XDMAC_EXDAD 0x1c 37 #define XDMAC_SAD 0x20 38 #define XDMAC_DAD 0x24 [all …]`
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A D	mmhub_3_0_1_sh_mask.h	`29 …RDCLI0__VIRT_CHAN__SHIFT 0x0 30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 …RDCLI0__URG_HIGH__SHIFT 0x4 32 …RDCLI0__URG_LOW__SHIFT 0x8 33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 …RDCLI0__MAX_BW__SHIFT 0xd 35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 …DCLI0__MIN_BW__SHIFT 0x16 37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]`
H A D	mmhub_3_0_0_sh_mask.h	`29 …RDCLI0__VIRT_CHAN__SHIFT 0x0 30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 …RDCLI0__URG_HIGH__SHIFT 0x4 32 …RDCLI0__URG_LOW__SHIFT 0x8 33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 …RDCLI0__MAX_BW__SHIFT 0xd 35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 …DCLI0__MIN_BW__SHIFT 0x16 37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]`
H A D	mmhub_3_0_2_sh_mask.h	`29 …RDCLI0__VIRT_CHAN__SHIFT 0x0 30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 …RDCLI0__URG_HIGH__SHIFT 0x4 32 …RDCLI0__URG_LOW__SHIFT 0x8 33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 …RDCLI0__MAX_BW__SHIFT 0xd 35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 …DCLI0__MIN_BW__SHIFT 0x16 37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]`
H A D	mmhub_4_1_0_sh_mask.h	`29 …RDCLI0__VIRT_CHAN__SHIFT 0x0 30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 …RDCLI0__URG_HIGH__SHIFT 0x4 32 …RDCLI0__URG_LOW__SHIFT 0x8 33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 …RDCLI0__MAX_BW__SHIFT 0xd 35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 …DCLI0__MIN_BW__SHIFT 0x16 37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]`
H A D	mmhub_3_3_0_sh_mask.h	`29 …RDCLI0__VIRT_CHAN__SHIFT 0x0 30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 …RDCLI0__URG_HIGH__SHIFT 0x4 32 …RDCLI0__URG_LOW__SHIFT 0x8 33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 …RDCLI0__MAX_BW__SHIFT 0xd 35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 …DCLI0__MIN_BW__SHIFT 0x16 37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]`
H A D	mmhub_2_3_0_sh_mask.h	`27 …RDCLI0__VIRT_CHAN__SHIFT 0x0 28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 29 …RDCLI0__URG_HIGH__SHIFT 0x4 30 …RDCLI0__URG_LOW__SHIFT 0x8 31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 32 …RDCLI0__MAX_BW__SHIFT 0xd 33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 34 …DCLI0__MIN_BW__SHIFT 0x16 35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 36 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]`
H A D	mmhub_1_8_0_sh_mask.h	`29 …RDCLI0__VIRT_CHAN__SHIFT 0x0 30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 …RDCLI0__URG_HIGH__SHIFT 0x4 32 …RDCLI0__URG_LOW__SHIFT 0x8 33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 …RDCLI0__MAX_BW__SHIFT 0xd 35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 …DCLI0__MIN_BW__SHIFT 0x16 37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]`
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A D	dpcs_4_2_3_sh_mask.h	31 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 32 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL 34 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 35 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL 40 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 41 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL 43 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 44 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL 49 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 50 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL [all …]
H A D	dpcs_3_1_4_sh_mask.h	33 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0 34 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x1 35 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2 36 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT 0x3 37 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4 38 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT 0x7 39 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0x8 40 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT 0x9 41 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT 0xa 42 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xb [all …]
H A D	dpcs_4_2_2_sh_mask.h	14 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 15 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL 17 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 18 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL 23 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 24 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL 26 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 27 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL 32 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 33 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL [all …]
H A D	dpcs_4_2_0_sh_mask.h	27 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 28 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL 30 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 31 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL 36 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 37 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL 39 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 40 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL 45 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 46 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL [all …]
/linux/drivers/mtd/nand/raw/
H A D	sm_common.c	`4 * Common routines & support for xD format 21 return 0; in oob_sm_ooblayout_ecc() 28 case 0: in oob_sm_ooblayout_free() 30 oobregion->offset = 0; in oob_sm_ooblayout_free() 47 return 0; in oob_sm_ooblayout_free() 68 oobregion->offset = 0; in oob_sm_small_ooblayout_ecc() 70 return 0; in oob_sm_small_ooblayout_ecc() 77 case 0: in oob_sm_small_ooblayout_free() 91 return 0; in oob_sm_small_ooblayout_free() 107 oob.block_status = 0x0F; in sm_block_markbad() [all …]`
/linux/arch/arm64/boot/dts/freescale/
H A D	imx8ulp-pinfunc.h	13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0 14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1 15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0 16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1 17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0 18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0 19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0 20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0 21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0 22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0 [all …]
/linux/sound/pci/au88x0/
H A D	au88x0_wt.h	12 /* WT channels are grouped in banks. Each bank has 0x20 channels. / 13 / Bank register address boundary is 0x8000 / 15 #define NR_WT_PB 0x20 18 #define WT_BAR(x) (((x)&0xffe0)<<0x8) 21 #define WT_CTRL(bank) (((((bank)&1)<<0xd) + 0x00)<<2) / 0x0000 / 22 #define WT_SRAMP(bank) (((((bank)&1)<<0xd) + 0x01)<<2) / 0x0004 / 23 #define WT_DSREG(bank) (((((bank)&1)<<0xd) + 0x02)<<2) / 0x0008 / 24 #define WT_MRAMP(bank) (((((bank)&1)<<0xd) + 0x03)<<2) / 0x000c / 25 #define WT_GMODE(bank) (((((bank)&1)<<0xd) + 0x04)<<2) / 0x0010 / 26 #define WT_ARAMP(bank) (((((bank)&1)<<0xd) + 0x05)<<2) / 0x0014 */ [all …]
/linux/drivers/gpio/
H A D	gpio-104-dio-48e.c	32 module_param_hw_array(base, uint, ioport, &num_dio48e, 0); 37 module_param_hw_array(irq, uint, irq, &num_irq, 0); 40 #define DIO48E_ENABLE_INTERRUPT 0xB 42 #define DIO48E_ENABLE_COUNTER_TIMER_ADDRESSING 0xD 44 #define DIO48E_CLEAR_INTERRUPT 0xF 49 regmap_reg_range(0x0, 0x9), regmap_reg_range(0xB, 0xB), 50 regmap_reg_range(0xD, 0xD), regmap_reg_range(0xF, 0xF), 53 regmap_reg_range(0x0, 0x2), regmap_reg_range(0x4, 0x6), 54 regmap_reg_range(0xB, 0xB), regmap_reg_range(0xD, 0xD), 55 regmap_reg_range(0xF, 0xF), [all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A D	bif_5_0_sh_mask.h	`27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff 28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0 29 #define MM_INDEX__MM_APER_MASK 0x80000000 30 #define MM_INDEX__MM_APER__SHIFT 0x1f 31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff 32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 33 #define MM_DATA__MM_DATA_MASK 0xffffffff 34 #define MM_DATA__MM_DATA__SHIFT 0x0 35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2 36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1 [all …]`
/linux/drivers/phy/starfive/
H A D	phy-jh7110-dphy-tx.c	26 #define STF_DPHY_AON_POWER_READY_N_ACTIVE 0 27 #define STF_DPHY_AON_POWER_READY_N BIT(0) 43 #define STF_DPHY_RG_CDTX_L4N_HSTX_RES GENMASK(4, 0) 45 #define STF_DPHY_RG_CDTX_PLL_FBK_FRA GENMASK(23, 0) 47 #define STF_DPHY_RG_CDTX_PLL_FBK_INT GENMASK(8, 0) 54 #define STF_DPHY_RG_CLANE_HS_CLK_POST_TIME GENMASK(7, 0) 59 #define STF_DPHY_RG_CLANE_HS_ZERO_TIME GENMASK(7, 0) 64 #define STF_DPHY_RG_EXTD_CYCLE_SEL GENMASK(2, 0) 65 #define STF_DPHY_SCFG_C_HS_PRE_ZERO_TIME GENMASK(31, 0) 100 {160000000, 0x6a, 0xaa, 0x3, 0xa, 0x17, 0x11, 0x5, 0x2b, 0xd, 0x7, 0x3d}, [all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A D	oss_2_4_enum.h	`28 DC_IH_SRC_ID_START = 0x1, 29 DC_IH_SRC_ID_END = 0x1f, 30 VGA_IH_SRC_ID_START = 0x20, 31 VGA_IH_SRC_ID_END = 0x27, 32 CAP_IH_SRC_ID_START = 0x28, 33 CAP_IH_SRC_ID_END = 0x2f, 34 VIP_IH_SRC_ID_START = 0x30, 35 VIP_IH_SRC_ID_END = 0x3f, 36 ROM_IH_SRC_ID_START = 0x40, 37 ROM_IH_SRC_ID_END = 0x5d, [all …]`
/linux/arch/powerpc/kvm/
H A D	book3s_xive.c	33 #define __x_eoi_page(xd) ((void __iomem )((xd)->eoi_mmio)) argument 34 #define __x_trig_page(xd) ((void __iomem )((xd)->trig_mmio)) argument 63 cppr = ack & 0xff; in xive_vm_ack_pending() 80 static u8 xive_vm_esb_load(struct xive_irq_data xd, u32 offset) in xive_vm_esb_load() argument 84 if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI) in xive_vm_esb_load() 87 val = __raw_readq(__x_eoi_page(xd) + offset); in xive_vm_esb_load() 95 static void xive_vm_source_eoi(u32 hw_irq, struct xive_irq_data xd) in xive_vm_source_eoi() argument 98 if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI) in xive_vm_source_eoi() 99 __raw_writeq(0, __x_eoi_page(xd) + XIVE_ESB_STORE_EOI); in xive_vm_source_eoi() 100 else if (xd->flags & XIVE_IRQ_FLAG_LSI) { in xive_vm_source_eoi() [all …]
/linux/drivers/net/phy/mediatek/
H A D	mtk-ge-soc.c	`17 #define MTK_GPHY_ID_MT7981 0x03a29461 18 #define MTK_GPHY_ID_MT7988 0x03a29481 19 #define MTK_GPHY_ID_AN7581 0x03a294c1 20 #define MTK_GPHY_ID_AN7583 0xc0ff0420 22 #define MTK_EXT_PAGE_ACCESS 0x1f 23 #define MTK_PHY_PAGE_STANDARD 0x0000 24 #define MTK_PHY_PAGE_EXTENDED_3 0x0003 26 #define MTK_PHY_LPI_REG_14 0x14 27 #define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) 29 #define MTK_PHY_LPI_REG_1c 0x1c [all …]`

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