Home
last modified time | relevance | path

Searched +full:0 +full:x80010000 (Results 1 – 25 of 37) sorted by relevance

12

/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852a_table.c10 {0xF0FF0001, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03500FF, 0x00000002},
13 {0xF03200FF, 0x00000003},
14 {0xF03400FF, 0x0000000
[all...]
H A Drtw8852b_table.c10 {0x704, 0x601E0100},
11 {0x4000, 0x00000000},
12 {0x4004, 0xCA014000},
13 {0x4008, 0xC751D4F0},
14 {0x400C, 0x4451147
[all...]
H A Drtw8852c_table.c10 {0xF0FF0000, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03400FF, 0x00000002},
13 {0xF03500FF, 0x00000003},
14 {0xF03600FF, 0x0000000
[all...]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dmxs-spi.txt20 #size-cells = <0>;
22 reg = <0x80010000 0x2000>;
24 dmas = <&dma_apbh 0>;
H A Dmxs-spi.yaml50 #size-cells = <0>;
52 reg = <0x80010000 0x2000>;
54 dmas = <&dma_apbh 0>;
H A Dspi-controller.yaml20 pattern: "^spi(@.*|-([0-9]|[1-9][0-9]+))?$"
23 enum: [0, 1]
26 const: 0
36 cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;
40 cs0 : &gpio1 0 0
42 cs2 : &gpio1 1 0
43 cs3 : &gpio1 2 0
45 The second flag of a gpio descriptor can be GPIO_ACTIVE_HIGH (0)
46 or GPIO_ACTIVE_LOW(1). Legacy device trees often use 0.
109 "^.*@[0-9a-f]+$":
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dxlnx,spdif.txt13 - xlnx,spdif-mode: 0 :- receiver mode
24 interrupts = <0 91 4>;
25 reg = <0x0 0x80010000 0x0 0x10000>;
H A Dxlnx,audio-formatter.txt25 interrupts = <0 104 4>, <0 105 4>;
26 reg = <0x0 0x80010000 0x0 0x1000>;
28 clocks = <&clk 71>, <&clk_wiz_1 0>;
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dmxs-mmc.txt22 reg = <0x80010000 2000>;
24 dmas = <&dma_apbh 0>;
H A Dmxs-mmc.yaml53 reg = <0x80010000 2000>;
55 dmas = <&dma_apbh 0>;
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dcirrus,ep9301-eth.yaml55 reg = <0x80010000 0x10000>;
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dalphascale,acc.txt22 CLKID_AHB_ROM 0
102 reg = <0x80010000 0x4000>;
110 reg = <0x80088000 0x4000>;
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dspear300.dtsi15 ranges = <0x60000000 0x60000000 0x50000000
16 0xd0000000 0xd0000000 0x30000000>;
20 reg = <0x99000000 0x1000>;
25 reg = <0x60000000 0x1000>;
34 reg = <0x94000000 0x1000 /* FSMC Register */
35 0x80000000 0x0010 /* NAND Base DATA */
36 0x80020000 0x0010 /* NAND Base ADDR */
37 0x80010000 0x0010>; /* NAND Base CMD */
44 reg = <0x70000000 0x100>;
51 reg = <0x50000000 0x1000>;
[all …]
/freebsd/contrib/ofed/libibumad/
H A Dumad_types.h54 #define UMAD_QKEY 0x80010000
58 UMAD_CLASS_SUBN_LID_ROUTED = 0x01,
59 UMAD_CLASS_SUBN_DIRECTED_ROUTE = 0x81,
60 UMAD_CLASS_SUBN_ADM = 0x03,
61 UMAD_CLASS_PERF_MGMT = 0x04,
62 UMAD_CLASS_BM = 0x05,
63 UMAD_CLASS_DEVICE_MGMT = 0x06,
64 UMAD_CLASS_CM = 0x07,
65 UMAD_CLASS_SNMP = 0x08,
66 UMAD_CLASS_VENDOR_RANGE1_START = 0x09,
[all …]
/freebsd/sys/dev/pms/RefTisa/sallsdk/spc/
H A Dsadefs.h43 #define REGISTER_DUMP_BUFF_SIZE 0x4000 /**< Maximum Fatal Error …
55 #define MPI_QUEUE_NORMAL 0
65 #define DIR_NODATA 0x000
66 #define DIR_READ 0x100
67 #define DIR_WRITE 0x200
70 #define TLR_MASK 0x00000003
74 #define PORTID_MASK 0x0000000F
75 #define PORTID_V_MASK 0x000000FF
76 #define PHYID_MASK 0x0000000F
77 #define PHYID_V_MASK 0x000000FF
[all …]
/freebsd/sys/dev/qlnx/qlnxr/
H A Dqlnxr_cm.c99 // uint32_t delay_count = 0, gsi_cons = 0; in qlnxr_ll2_complete_rx_packet()
126 data->u.data_length_error ? -EINVAL : 0; in qlnxr_ll2_complete_rx_packet()
129 qp->rqe_wr_id[qp->rq.gsi_cons].sg_list[0].length = in qlnxr_ll2_complete_rx_packet()
131 *((u32 *)&qp->rqe_wr_id[qp->rq.gsi_cons].smac[0]) = in qlnxr_ll2_complete_rx_packet()
211 return 0; in qlnxr_check_gsi_qp_attrs()
224 memset(&ll2_tx_pkt, 0, sizeof(ll2_tx_pkt)); in qlnxr_ll2_post_tx()
235 ll2_tx_pkt.vlan = 0; /* ??? */ in qlnxr_ll2_post_tx()
263 for (i = 0; i < pkt->n_seg; i++) { in qlnxr_ll2_post_tx()
278 struct ecore_ll2_stats stats = {0}; in qlnxr_ll2_post_tx()
285 return 0; in qlnxr_ll2_post_tx()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/cirrus/
H A Dep93xx.dtsi18 reg = <0x80930000 0x1000>;
101 reg = <0x80900000 0x28>;
110 * windows in the 256MB space from 0x50000000 to 0x5fffffff.
116 reg = <0x80080000 0x20>;
125 reg = <0x80000000 0x0040>,
126 <0x80000040 0x0040>,
127 <0x80000080 0x0040>,
128 <0x800000c0 0x0040>,
129 <0x80000240 0x0040>,
130 <0x80000200 0x0040>,
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dredwood.dts18 dcr-parent = <&{/cpus/cpu@0}>;
27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0x00000000>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 cell-index = <0>;
53 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>;
[all …]
H A Dicon.dts18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
49 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
[all …]
H A Dkatmai.dts22 dcr-parent = <&{/cpus/cpu@0}>;
33 #size-cells = <0>;
35 cpu@0 {
38 reg = <0x00000000>;
39 clock-frequency = <0>; /* Filled in by zImage */
40 timebase-frequency = <0>; /* Filled in by zImage */
53 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
59 cell-index = <0>;
60 dcr-reg = <0x0c0 0x009>;
61 #address-cells = <0>;
[all …]
H A Dcanyonlands.dts18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
49 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
[all …]
H A Dglacier.dts18 dcr-parent = <&{/cpus/cpu@0}>;
31 #size-cells = <0>;
33 cpu@0 {
36 reg = <0x00000000>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
51 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
57 cell-index = <0>;
58 dcr-reg = <0x0c0 0x009>;
59 #address-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/mxs/
H A Dimx23.dtsi32 #size-cells = <0>;
34 cpu@0 {
37 reg = <0>;
45 reg = <0x80000000 0x80000>;
52 reg = <0x80000000 0x40000>;
59 reg = <0x80000000 0x2000>;
64 reg = <0x80004000 0x2000>;
65 interrupts = <0>, <14>, <20>, <0>,
73 reg = <0x80008000 0x2000>;
81 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
[all …]
H A Dimx28.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0>;
56 reg = <0x80000000 0x80000>;
63 reg = <0x80000000 0x3c900>;
70 reg = <0x80000000 0x2000>;
74 reg = <0x80002000 0x2000>;
83 reg = <0x80004000 0x2000>;
87 <87>, <86>, <0>, <0>;
94 reg = <0x80006000 0x800>;
[all …]
/freebsd/sys/ofed/include/rdma/
H A Dib_mad.h49 #define OPA_MGMT_BASE_VERSION 0x80
51 #define OPA_SMP_CLASS_VERSION 0x80
54 #define IB_MGMT_CLASS_SUBN_LID_ROUTED 0x01
55 #define IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE 0x81
56 #define IB_MGMT_CLASS_SUBN_ADM 0x03
57 #define IB_MGMT_CLASS_PERF_MGMT 0x04
58 #define IB_MGMT_CLASS_BM 0x05
59 #define IB_MGMT_CLASS_DEVICE_MGMT 0x06
60 #define IB_MGMT_CLASS_CM 0x07
61 #define IB_MGMT_CLASS_SNMP 0x08
[all …]

12