Lines Matching +full:0 +full:x80010000
22 dcr-parent = <&{/cpus/cpu@0}>;
33 #size-cells = <0>;
35 cpu@0 {
38 reg = <0x00000000>;
39 clock-frequency = <0>; /* Filled in by zImage */
40 timebase-frequency = <0>; /* Filled in by zImage */
53 reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
59 cell-index = <0>;
60 dcr-reg = <0x0c0 0x009>;
61 #address-cells = <0>;
62 #size-cells = <0>;
70 dcr-reg = <0x0d0 0x009>;
71 #address-cells = <0>;
72 #size-cells = <0>;
74 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
82 dcr-reg = <0x0e0 0x009>;
83 #address-cells = <0>;
84 #size-cells = <0>;
86 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
94 dcr-reg = <0x0f0 0x009>;
95 #address-cells = <0>;
96 #size-cells = <0>;
98 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
104 dcr-reg = <0x00e 0x002>;
109 dcr-reg = <0x00c 0x002>;
114 dcr-reg = <0x040 0x020>;
122 ranges = <0x4 0x00100000 0x4 0x00100000 0x00001000
123 0x4 0x00200000 0x4 0x00200000 0x00000400
124 0x4 0xe0000000 0x4 0xe0000000 0x20000000
125 0xc 0x00000000 0xc 0x00000000 0x20000000
126 0xd 0x00000000 0xd 0x00000000 0x80000000
127 0xd 0x80000000 0xd 0x80000000 0x80000000
128 0xe 0x00000000 0xe 0x00000000 0x80000000
129 0xe 0x80000000 0xe 0x80000000 0x80000000
130 0xf 0x00000000 0xf 0x00000000 0x80000000
131 0xf 0x80000000 0xf 0x80000000 0x80000000>;
132 clock-frequency = <0>; /* Filled in by zImage */
136 dcr-reg = <0x010 0x002>;
141 dcr-reg = <0x180 0x062>;
145 interrupts = <0x0 0x1 0x2 0x3 0x4>;
147 #address-cells = <0>;
148 #size-cells = <0>;
149 interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4
150 /*RXEOB*/ 0x1 &UIC1 0x7 0x4
151 /*SERR*/ 0x2 &UIC1 0x1 0x4
152 /*TXDE*/ 0x3 &UIC1 0x2 0x4
153 /*RXDE*/ 0x4 &UIC1 0x3 0x4>;
160 ranges = <0xe0000000 0x00000004 0xe0000000 0x20000000>;
161 clock-frequency = <0>; /* Filled in by zImage */
165 dcr-reg = <0x012 0x002>;
168 clock-frequency = <0>; /* Filled in by zImage */
170 interrupts = <0x5 0x1>;
173 nor_flash@0,0 {
176 reg = <0x00000000 0x00000000 0x01000000>;
179 partition@0 {
181 reg = <0x00000000 0x001e0000>;
185 reg = <0x001e0000 0x00020000>;
189 reg = <0x00200000 0x00200000>;
193 reg = <0x00400000 0x00b60000>;
197 reg = <0x00f60000 0x00040000>;
201 reg = <0x00fa0000 0x00060000>;
209 reg = <0xf0000200 0x00000008>;
210 virtual-reg = <0xa0000200>;
211 clock-frequency = <0>; /* Filled in by zImage */
214 interrupts = <0x0 0x4>;
220 reg = <0xf0000300 0x00000008>;
221 virtual-reg = <0xa0000300>;
222 clock-frequency = <0>;
223 current-speed = <0>;
225 interrupts = <0x1 0x4>;
232 reg = <0xf0000600 0x00000008>;
233 virtual-reg = <0xa0000600>;
234 clock-frequency = <0>;
235 current-speed = <0>;
237 interrupts = <0x5 0x4>;
242 reg = <0xf0000400 0x00000014>;
244 interrupts = <0x2 0x4>;
249 reg = <0xf0000500 0x00000014>;
251 interrupts = <0x3 0x4>;
255 linux,network-index = <0x0>;
259 interrupts = <0x1c 0x4 0x1d 0x4>;
260 reg = <0xf0000800 0x00000074>;
263 mal-tx-channel = <0>;
264 mal-rx-channel = <0>;
265 cell-index = <0>;
270 phy-map = <0x00000000>;
285 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
286 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
287 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
288 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
289 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
294 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
295 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
297 /* Inbound 4GB range starting at 0 */
298 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
300 /* This drives busses 0 to 0xf */
301 bus-range = <0x0 0xf>;
312 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
315 0x800 0x0 0x0 0x1 &UIC1 0x14 0x8
316 0x800 0x0 0x0 0x2 &UIC1 0x13 0x8
317 0x800 0x0 0x0 0x3 &UIC1 0x12 0x8
318 0x800 0x0 0x0 0x4 &UIC1 0x11 0x8
329 port = <0x0>; /* port number */
330 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
331 0x0000000c 0x10000000 0x00001000>; /* Registers */
332 dcr-reg = <0x100 0x020>;
333 sdr-base = <0x300>;
338 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
339 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
341 /* Inbound 4GB range starting at 0 */
342 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
344 /* This drives busses 0x10 to 0x1f */
345 bus-range = <0x10 0x1f>;
353 * The real slot is on idsel 0, so the swizzling is 1:1
355 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
357 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
358 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
359 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
360 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
370 port = <0x1>; /* port number */
371 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
372 0x0000000c 0x10001000 0x00001000>; /* Registers */
373 dcr-reg = <0x120 0x020>;
374 sdr-base = <0x340>;
379 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
380 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
382 /* Inbound 4GB range starting at 0 */
383 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
385 /* This drives busses 0x20 to 0x2f */
386 bus-range = <0x20 0x2f>;
394 * The real slot is on idsel 0, so the swizzling is 1:1
396 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
398 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
399 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
400 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
401 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
411 port = <0x2>; /* port number */
412 reg = <0x0000000d 0x40000000 0x20000000 /* Config space access */
413 0x0000000c 0x10002000 0x00001000>; /* Registers */
414 dcr-reg = <0x140 0x020>;
415 sdr-base = <0x370>;
420 ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000
421 0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>;
423 /* Inbound 4GB range starting at 0 */
424 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
426 /* This drives busses 0x30 to 0x3f */
427 bus-range = <0x30 0x3f>;
435 * The real slot is on idsel 0, so the swizzling is 1:1
437 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
439 0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */
440 0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */
441 0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
442 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
447 reg = <0x00000004 0x00100000 0x100>;
448 dcr-reg = <0x060 0x020>;
453 cell-index = <0>;
454 reg = <0x00000004 0x00100100 0x100>;
455 dcr-reg = <0x060 0x020>;
457 interrupts = <0 1>;
459 #address-cells = <0>;
460 #size-cells = <0>;
462 0 &UIC0 0x14 4
463 1 &UIC1 0x16 4>;
469 reg = <0x00000004 0x00100200 0x100>;
470 dcr-reg = <0x060 0x020>;
472 interrupts = <0 1>;
474 #address-cells = <0>;
475 #size-cells = <0>;
477 0 &UIC0 0x16 4
478 1 &UIC1 0x16 4>;
483 reg = <0x00000004 0x00200000 0x400>;
485 interrupts = <0x1f 4>;