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/linux/drivers/platform/x86/
H A Dacerhdf.c40 #define DRV_VER "0.7.0"
46 * measured by the on-die thermal monitor are within 0 <= Tj <= 90. So,
52 #define ACERHDF_FAN_OFF 0
86 module_param(kernelmode, uint, 0);
96 module_param_string(force_bios, force_bios, 16, 0);
98 module_param_string(force_product, force_product, 16, 0);
118 .mreg = 0x94,
119 .moff = 0xff,
142 [0] = { .temperature = ACERHDF_DEFAULT_TEMP_FANON,
155 {"Acer", "AOA110", "v0.3109", 0x55, 0x58, {0x1f, 0x00}, 0},
[all …]
/linux/crypto/
H A Dtestmgr.h33 * @ksize: Length of @key in bytes (0 if no key)
103 * @crypt_error: When @novrfy=0, the expected error from encrypt(). When
258 "\x2D\x5B\x25\x21\x76\x45\x9D\x1F\x39\x75\x41\xBA\x2A\x58\xFB\x65"
279 "\x9F\xC9\x86\x32\x15\x4F\x58\x83\xB1\x67\xA9\x67\xBF\x40\x2B\x4E"
336 "\x00\xFA\xAC\xE1\x37\x5E\x32\x11\x34\xC6\x72\x58\x2D\x91\x06\x3E"
342 "\x42\x21\x5E\xA0\xA1\x2A\x58\x35\xBB\x10\xE7\xBA\x27\x0A\x3B\xB3"
363 "\xC2\x18\xB1\x58\xB1\x50\x91\xB8\x61\x41\xB6\xA9\xCE\xD4\x7C\xBB"
380 "\x1A\xD3\x73\x58\x4B\xD8\xA0\x54\x25\x48\x83\x6F\x82\x6C\xAF\x36"
482 "\xA8\xF2\x1F\xEA\xDF\x3A\x37\x2D\xE5\x39\x39\xF8\x57\x58\x3C\x04"
504 "\xFD\x7B\x96\x7B\xFC\xC4\x26\x58\xC4\xFC\x7C\xAF\xB5\xE8\x95\x83"
[all …]
H A Ddh.c27 memset(ctx, 0, sizeof(*ctx)); in dh_clear_ctx()
50 return (p_len < 2048) ? -EINVAL : 0; in dh_check_params_length()
52 return (p_len < 1536) ? -EINVAL : 0; in dh_check_params_length()
68 return 0; in dh_set_params()
80 if (crypto_dh_decode_key(buf, len, &params) < 0) in dh_set_secret()
83 if (dh_set_params(ctx, &params) < 0) in dh_set_secret()
90 return 0; in dh_set_secret()
113 return 0; in dh_is_pubkey_valid()
126 if (mpi_cmp_ui(y, 1) < 1 || mpi_cmp(y, ctx->p) >= 0) in dh_is_pubkey_valid()
134 val = mpi_alloc(0); in dh_is_pubkey_valid()
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-skov-cpu.dtsi30 io-channels = <&adc 0>, /* 24V */
37 led-0 {
47 gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
61 pinctrl-0 = <&pinctrl_mdio>;
63 #size-cells = <0>;
67 switch: switch@0 {
70 pinctrl-0 = <&pinctrl_switch>;
74 reg = <0>;
78 #size-cells = <0>;
80 lan1: ports@0 {
[all …]
H A Dimx1-pinfunc.h15 * function: 0 - Primary function
18 * direction: 0 - Input
20 * gpio_oconf: 0 - A_IN
24 * gpio_iconfa/b: 0 - GPIO_IN
26 * 2 - 0
29 * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32
31 * the pin number on the specific port (between 0 and 31).
34 #define MX1_PAD_A24__A24 0x00 0x004
35 #define MX1_PAD_A24__GPIO1_0 0x00 0x032
36 #define MX1_PAD_A24__SPI2_CLK 0x00 0x006
[all …]
/linux/lib/crypto/
H A Daesgcm.c43 * Returns: 0 on success, or -EINVAL if @keysize or @authsize contain values
60 return 0; in aesgcm_expandkey()
67 while (len > 0) { in aesgcm_ghash()
114 while (len > 0) { in aesgcm_crypt()
209 "\x58\xe2\xfc\xce\xfa\x7e\x30\x61"
238 "\x3d\x58\xe0\x91\x47\x3f\x59\x85"
260 "\x3d\x58\xe0\x91"
272 "\x8e\xf4\xd4\x58\x75\x14\xf0\xfb";
293 "\x99\x24\xa7\xc8\x58\x73\x36\xbf"
375 "\x58\x83\xf0\xc3\x70\x14\xc0\x5b"
[all …]
/linux/fs/nls/
H A Dnls_ascii.c17 /* 0x00*/
18 0x0000, 0x0001, 0x0002, 0x0003,
19 0x0004, 0x0005, 0x0006, 0x0007,
20 0x0008, 0x0009, 0x000a, 0x000b,
21 0x000c, 0x000d, 0x000e, 0x000f,
22 /* 0x10*/
23 0x0010, 0x0011, 0x0012, 0x0013,
24 0x0014, 0x0015, 0x0016, 0x0017,
25 0x0018, 0x0019, 0x001a, 0x001b,
26 0x001c, 0x001d, 0x001e, 0x001f,
[all …]
H A Dnls_cp1251.c17 /* 0x00*/
18 0x0000, 0x0001, 0x0002, 0x0003,
19 0x0004, 0x0005, 0x0006, 0x0007,
20 0x0008, 0x0009, 0x000a, 0x000b,
21 0x000c, 0x000d, 0x000e, 0x000f,
22 /* 0x10*/
23 0x0010, 0x0011, 0x0012, 0x0013,
24 0x0014, 0x0015, 0x0016, 0x0017,
25 0x0018, 0x0019, 0x001a, 0x001b,
26 0x001c, 0x001d, 0x001e, 0x001f,
[all …]
H A Dnls_iso8859-6.c17 /* 0x00*/
18 0x0000, 0x0001, 0x0002, 0x0003,
19 0x0004, 0x0005, 0x0006, 0x0007,
20 0x0008, 0x0009, 0x000a, 0x000b,
21 0x000c, 0x000d, 0x000e, 0x000f,
22 /* 0x10*/
23 0x0010, 0x0011, 0x0012, 0x0013,
24 0x0014, 0x0015, 0x0016, 0x0017,
25 0x0018, 0x0019, 0x001a, 0x001b,
26 0x001c, 0x001d, 0x001e, 0x001f,
[all …]
H A Dnls_cp857.c17 /* 0x00*/
18 0x0000, 0x0001, 0x0002, 0x0003,
19 0x0004, 0x0005, 0x0006, 0x0007,
20 0x0008, 0x0009, 0x000a, 0x000b,
21 0x000c, 0x000d, 0x000e, 0x000f,
22 /* 0x10*/
23 0x0010, 0x0011, 0x0012, 0x0013,
24 0x0014, 0x0015, 0x0016, 0x0017,
25 0x0018, 0x0019, 0x001a, 0x001b,
26 0x001c, 0x001d, 0x001e, 0x001f,
[all …]
H A Dnls_cp866.c17 /* 0x00*/
18 0x0000, 0x0001, 0x0002, 0x0003,
19 0x0004, 0x0005, 0x0006, 0x0007,
20 0x0008, 0x0009, 0x000a, 0x000b,
21 0x000c, 0x000d, 0x000e, 0x000f,
22 /* 0x10*/
23 0x0010, 0x0011, 0x0012, 0x0013,
24 0x0014, 0x0015, 0x0016, 0x0017,
25 0x0018, 0x0019, 0x001a, 0x001b,
26 0x001c, 0x001d, 0x001e, 0x001f,
[all …]
H A Dnls_cp855.c17 /* 0x00*/
18 0x0000, 0x0001, 0x0002, 0x0003,
19 0x0004, 0x0005, 0x0006, 0x0007,
20 0x0008, 0x0009, 0x000a, 0x000b,
21 0x000c, 0x000d, 0x000e, 0x000f,
22 /* 0x10*/
23 0x0010, 0x0011, 0x0012, 0x0013,
24 0x0014, 0x0015, 0x0016, 0x0017,
25 0x0018, 0x0019, 0x001a, 0x001b,
26 0x001c, 0x001d, 0x001e, 0x001f,
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt8188-wpe.c17 .set_ofs = 0x0,
18 .clr_ofs = 0x0,
19 .sta_ofs = 0x0,
23 .set_ofs = 0x58,
24 .clr_ofs = 0x58,
25 .sta_ofs = 0x58,
29 .set_ofs = 0x5c,
30 .clr_ofs = 0x5c,
31 .sta_ofs = 0x5c,
52 GATE_WPE_VPP0_0(CLK_WPE_VPP0_VGEN, "wpe_vpp0_vgen", "top_img", 0),
[all …]
H A Dclk-mt8195-wpe.c14 .set_ofs = 0x0,
15 .clr_ofs = 0x0,
16 .sta_ofs = 0x0,
20 .set_ofs = 0x58,
21 .clr_ofs = 0x58,
22 .sta_ofs = 0x58,
26 .set_ofs = 0x5c,
27 .clr_ofs = 0x5c,
28 .sta_ofs = 0x5c,
52 GATE_WPE_VPP0(CLK_WPE_VPP0_VGEN, "wpe_vpp0_vgen", "top_img", 0),
[all …]
/linux/arch/mips/boot/dts/brcm/
H A Dbcm7420.dtsi9 #size-cells = <0>;
13 cpu@0 {
16 reg = <0>;
31 #address-cells = <0>;
41 #clock-cells = <0>;
47 #clock-cells = <0>;
57 ranges = <0 0x10000000 0x01000000>;
61 reg = <0x441400 0x30>, <0x441600 0x30>;
72 reg = <0x401800 0x30>;
81 reg = <0x400000 0xdc>;
[all …]
H A Dbcm7125.dtsi9 #size-cells = <0>;
13 cpu@0 {
16 reg = <0>;
31 #address-cells = <0>;
41 #clock-cells = <0>;
47 #clock-cells = <0>;
57 ranges = <0 0x10000000 0x01000000>;
61 reg = <0x441400 0x30>, <0x441600 0x30>;
72 reg = <0x401800 0x30>;
81 reg = <0x400000 0xdc>;
[all …]
H A Dbcm7358.dtsi9 #size-cells = <0>;
13 cpu@0 {
16 reg = <0>;
25 #address-cells = <0>;
35 #clock-cells = <0>;
41 #clock-cells = <0>;
51 ranges = <0 0x10000000 0x01000000>;
55 reg = <0x411400 0x30>;
66 reg = <0x403000 0x30>;
75 reg = <0x400000 0xdc>;
[all …]
/linux/include/dt-bindings/clock/
H A Domap4.h8 #define OMAP4_CLKCTRL_OFFSET 0x20
12 #define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
15 #define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
18 #define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
19 #define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
20 #define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
21 #define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
22 #define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
23 #define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48)
24 #define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
[all …]
/linux/include/linux/soc/mmp/
H A Dcputype.h12 * PXA168 S0 0x56158400 0x0000C910
13 * PXA168 A0 0x56158400 0x00A0A168
14 * PXA910 Y1 0x56158400 0x00F2C920
15 * PXA910 A0 0x56158400 0x00F2C910
16 * PXA910 A1 0x56158400 0x00A0C910
17 * PXA920 Y0 0x56158400 0x00F2C920
18 * PXA920 A0 0x56158400 0x00A0C920
19 * PXA920 A1 0x56158400 0x00A1C920
20 * MMP2 Z0 0x560f5811 0x00F00410
21 * MMP2 Z1 0x560f5811 0x00E00410
[all …]
/linux/arch/sparc/include/uapi/asm/
H A Dptrace.h16 #define PT_REGS_MAGIC 0x57ac6c00
142 #define UREG_G0 0
169 #define TRACEREG_SZ 0xa0
170 #define STACKFRAME_SZ 0xc0
172 #define TRACEREG32_SZ 0x50
173 #define STACKFRAME32_SZ 0x60
185 #define TRACEREG_SZ 0x50
186 #define STACKFRAME_SZ 0x60
193 #define PT_V9_G0 0x00
194 #define PT_V9_G1 0x08
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-txrx-v6.h9 #define QSERDES_V6_TX_CLKBUF_ENABLE 0x08
10 #define QSERDES_V6_TX_TX_EMP_POST1_LVL 0x0c
11 #define QSERDES_V6_TX_TX_DRV_LVL 0x14
12 #define QSERDES_V6_TX_RESET_TSYNC_EN 0x1c
13 #define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN 0x20
14 #define QSERDES_V6_TX_TX_BAND 0x24
15 #define QSERDES_V6_TX_INTERFACE_SELECT 0x2c
16 #define QSERDES_V6_TX_RES_CODE_LANE_TX 0x34
17 #define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38
18 #define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c
[all …]
/linux/drivers/regulator/
H A Dpv88090-regulator.h11 #define PV88090_REG_EVENT_A 0x03
12 #define PV88090_REG_MASK_A 0x06
13 #define PV88090_REG_MASK_B 0x07
16 #define PV88090_REG_BUCK1_CONF0 0x18
17 #define PV88090_REG_BUCK1_CONF1 0x19
18 #define PV88090_REG_BUCK1_CONF2 0x1a
19 #define PV88090_REG_BUCK2_CONF0 0x1b
20 #define PV88090_REG_BUCK2_CONF1 0x1c
21 #define PV88090_REG_BUCK2_CONF2 0x58
22 #define PV88090_REG_BUCK3_CONF0 0x1d
[all …]
/linux/Documentation/devicetree/bindings/nvmem/
H A Dsocionext,uniphier-efuse.yaml34 reg = <0x100 0x28>;
39 reg = <0x200 0x68>;
45 reg = <0x54 1>;
49 reg = <0x55 1>;
53 reg = <0x58 1>;
57 reg = <0x59 1>;
60 usb_sel_t0: trim@54,0 {
61 reg = <0x54 1>;
62 bits = <0 4>;
64 usb_sel_t1: trim@55,0 {
[all …]
/linux/drivers/video/fbdev/
H A Doffb.c67 #define AVIVO_DC_LUT_RW_SELECT 0x6480
68 #define AVIVO_DC_LUT_RW_MODE 0x6484
69 #define AVIVO_DC_LUT_RW_INDEX 0x6488
70 #define AVIVO_DC_LUT_SEQ_COLOR 0x648c
71 #define AVIVO_DC_LUT_PWL_DATA 0x6490
72 #define AVIVO_DC_LUT_30_COLOR 0x6494
73 #define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498
74 #define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c
75 #define AVIVO_DC_LUT_AUTOFILL 0x64a0
77 #define AVIVO_DC_LUTA_CONTROL 0x64c0
[all …]
/linux/arch/sparc/crypto/
H A Ddes_asm.S11 ld [%o0 + 0x00], %f0
12 ld [%o0 + 0x04], %f1
13 DES_KEXPAND(0, 0, 0)
14 DES_KEXPAND(0, 1, 2)
29 std %f0, [%o1 + 0x00]
30 std %f2, [%o1 + 0x08]
31 std %f4, [%o1 + 0x10]
32 std %f6, [%o1 + 0x18]
33 std %f8, [%o1 + 0x20]
34 std %f10, [%o1 + 0x28]
[all …]

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