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/titanic_51/usr/src/uts/sun4u/lw8/sys/
H A Dsgenv_tag.h116 #define SG_SENSOR_PART_SBBC 0x1
119 #define SG_SENSOR_PART_SDC 0x2
122 #define SG_SENSOR_PART_AR 0x3
125 #define SG_SENSOR_PART_CBH 0x4
128 #define SG_SENSOR_PART_DX 0x5
131 #define SG_SENSOR_PART_CHEETAH 0x6
134 #define SG_SENSOR_PART_1_5_VDC 0x7
137 #define SG_SENSOR_PART_3_3_VDC 0x8
140 #define SG_SENSOR_PART_5_VDC 0x9
143 #define SG_SENSOR_PART_12_VDC 0x
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/titanic_51/usr/src/uts/sun4u/serengeti/sys/
H A Dsgfrutypes.h53 #define SG_HPU_TYPE_SYSTEM_CONTROLLER_BOARD (0x101)
59 #define SG_HPU_TYPE_SYSTEM_CONTROLLER_BOARD_F3800 (0x102)
66 #define SG_HPU_TYPE_CPU_BOARD (0x201)
71 #define SG_HPU_TYPE_WIB_BOARD (0x202)
76 #define SG_HPU_TYPE_ZULU_BOARD (0x203)
82 #define SG_HPU_TYPE_REPEATER_BOARD (0x301)
86 #define SG_HPU_TYPE_LOGIC_ANALYZER_BOARD (0x302)
90 #define SG_HPU_TYPE_REPEATER_BOARD_F3800 (0x303)
96 #define SG_HPU_TYPE_FAN_TRAY_F6800_IO (0x401)
101 #define SG_HPU_TYPE_FAN_TRAY_F6800_CPU (0x40
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/titanic_51/usr/src/lib/libm/common/C/
H A Dsin.c59 * |cos(x) - (1+qq1*x^2+qq2*x^4)| <= 2^-55.99 for |x| <= 0.008 (0x3f80624d)
75 #define ONE sc[0]
103 ix = hx & ~0x80000000; in sin()
105 if (ix <= 0x3fc50000) { /* |x| < .1640625 */ in sin()
106 if (ix < 0x3e400000) /* |x| < 2**-27 */ in sin()
107 if ((int)x == 0) in sin()
110 if (ix < 0x3f800000) /* |x| < 2**-8 */ in sin()
119 if (n < 0x402) { /* x < 8 */ in sin()
120 i = (((ix >> 12) & 0xf in sin()
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H A Dcos.c59 * |cos(x) - (1+qq1*x^2+qq2*x^4)| <= 2^-55.99 for |x| <= 0.008 (0x3f80624d)
82 #define ONE sc[0]
117 ix = hx & ~0x80000000; in cos()
119 if (ix <= 0x3fc50000) { /* |x| < 10.5/64 = 0.164062500 */ in cos()
120 if (ix < 0x3e400000) { /* |x| < 2**-27 */ in cos()
121 if ((int)x == 0) in cos()
125 if (ix < 0x3f800000) /* |x| < 0.008 */ in cos()
134 if (n < 0x402) { /* x < 8 */ in cos()
135 i = (((ix >> 12) & 0xf in cos()
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H A Datan.c42 * (1). Purge off Inf and NaN and 0
53 * Note: (i) domain of poly1 is [0, 1/8], (ii) remez relative
63 * its domain is [0, 0.0154]; and its remez absolute
70 * Let j = (ix - 0x3fc00000) >> 16, 0 <= j < 96, where ix is the high
107 #define one g[0]
132 ix = hx & ~0x80000000; in atan()
136 if (j < 0x3fc) { in atan()
137 if (j < 0x3f5) { /* when |x| < 2**(-prec/6-2) */ in atan()
138 if (j < 0x3e in atan()
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H A Dsincos.c36 * 1. Reduce x to x>0 by cos(-x)=cos(x), sin(-x)=-sin(x).
37 * 2. For 0<= x < 8, let i = (64*x chopped)-10. Let d = x - a[i], where
77 * 0 S C S/C
112 * |cos(x) - (1+qq1*x^2+qq2*x^4)| <= 2^-55.99 for |x| <= 0.008 (0x3f80624d)
143 #define ONE sc[0]
188 ix = hx & ~0x80000000; in sincos()
190 if (ix <= 0x3fc50000) { /* |x| < 10.5/64 = 0.164062500 */ in sincos()
191 if (ix < 0x3e400000) { /* |x| < 2**-27 */ in sincos()
192 if ((int)x == 0) in sincos()
197 if (ix < 0x3f80000 in sincos()
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/titanic_51/usr/src/uts/intel/sys/
H A Dmca_amd.h42 #define AMD_MSR_MCG_CAP 0x179
43 #define AMD_MSR_MCG_STATUS 0x17a
44 #define AMD_MSR_MCG_CTL 0x17b
46 #define AMD_MCA_BANK_DC 0 /* Data Cache */
53 #define AMD_MSR_DC_CTL 0x400
54 #define AMD_MSR_DC_MASK 0xc0010044
55 #define AMD_MSR_DC_STATUS 0x401
56 #define AMD_MSR_DC_ADDR 0x402
57 #define AMD_MSR_DC_MISC 0x40
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/titanic_51/usr/src/uts/sun4u/starcat/io/
H A Dfcgp2.c65 #define HIADDR(n) ((uint32_t)(((uint64_t)(n) & 0xFFFFFFFF00000000)>> 32))
66 #define LOADDR(n)((uint32_t)((uint64_t)(n) & 0x00000000FFFFFFFF))
68 #define PCI_4GIG_LIMIT 0xFFFFFFFFUL
202 "Free claim-memory resource 0x%lx size 0x%x\n", in gp2_fc_ops_free_handle()
234 if (fc_ops(ap, rp->next_handle, cp) == 0) { in gp2_fc_ops()
236 if (strcmp(pv->svc_name, name) == 0) in gp2_fc_ops()
238 return (0); in gp2_fc_ops()
242 if (strcmp(pv->svc_name, name) == 0) in gp2_fc_ops()
270 r.regspec_size = len = fc_cell2size(fc_arg(cp, 0)); in gfc_map_in()
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/titanic_51/usr/src/man/man7m/
H A Dkb.7m56 words (\fBunsigned short\fRs). If a table entry is less than 0x100, the entry
173 from 0 to 127. The number is used as an index into the translation table that
175 a value from 0 to 255, the value is treated as an \fBISO\fR 8859/1 character,
187 \fBSHIFTKEYS 0x100 \fR
195 \fB\fBCAPSLOCK 0\fR \fR
278 \fB\fBBUCKYBITS 0x200\fR \fR
287 \fB\fBMETABIT 0\fR \fR
291 bucky bit. It is ORed in as the 0x80 bit; since this bit is a legitimate bit in
292 a character, the only way to distinguish between, for example, 0xA0 as
293 \fBMETA+0x2
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/titanic_51/usr/src/uts/common/sys/
H A Dkbd.h29 #pragma ident "%Z%%M% %I% %E% SMI" /* SunOS4.0 1.18 */
40 #define KB_KLUNK 0x00 /* Micro Switch 103SD32-2 */
41 #define KB_VT100 0x01 /* Keytronics VT100 compatible */
42 #define KB_SUN2 0x02 /* Sun-2 custom keyboard */
43 #define KB_VT220 0x81 /* Emulation VT220 */
44 #define KB_VT220I 0x82 /* International VT220 Emulation */
46 #define NOTPRESENT 0xFF /* Keyboard is not plugged in */
47 #define KBD_CMD_LED1 0x04 /* Turn on LED 1 for Sun-2 */
48 #define KBD_CMD_NOLED1 0x05 /* Turn off LED 1 for Sun-2 */
49 #define KBD_CMD_LED2 0x0
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/titanic_51/usr/src/lib/hbaapi/common/
H A Dhbaapi.h112 #define HBA_HANDLE_INVALID 0
117 #define HBA_STATUS_OK 0
233 #define HBA_PORTSPEED_UNKNOWN 0 /* Unknown - transceiver incable
414 #define HBA_EVENT_PROPRIETARY 0xFFFF
451 #define HBA_BIND_TO_D_ID 0x0001
452 #define HBA_BIND_TO_WWPN 0x0002
453 #define HBA_BIND_TO_WWNN 0x0004
454 #define HBA_BIND_TO_LUID 0x0008
455 #define HBA_BIND_TARGETS 0x0800
460 #define HBA_CAN_BIND_TO_D_ID 0x000
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/titanic_51/usr/src/uts/common/sys/fibre-channel/fca/emlxs/
H A Demlxs_hbaapi.h113 #define HBA_HANDLE_INVALID 0
118 #define HBA_STATUS_OK 0
234 #define HBA_PORTSPEED_UNKNOWN 0 /* Unknown - transceiver incable
415 #define HBA_EVENT_PROPRIETARY 0xFFFF
454 #define HBA_BIND_TO_D_ID 0x0001
455 #define HBA_BIND_TO_WWPN 0x0002
456 #define HBA_BIND_TO_WWNN 0x0004
457 #define HBA_BIND_TO_LUID 0x0008
458 #define HBA_BIND_TARGETS 0x0800
463 #define HBA_CAN_BIND_TO_D_ID 0x000
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/titanic_51/usr/src/boot/sys/x86/include/
H A Dspecialreg.h39 #define CR0_PE 0x00000001 /* Protected mode Enable */
40 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */
41 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
43 #define CR0_PG 0x80000000 /* PaGing enable */
48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
49 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
52 #define CR0_NW 0x20000000 /* Not Write-through */
53 #define CR0_CD 0x4000000
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/titanic_51/usr/src/cmd/ndmpd/ndmp/
H A Dndmp.x73 NDMP_NO_ERR = 0, /* No error */
122 NDMP_CONNECT_OPEN = 0x900,
123 NDMP_CONNECT_CLIENT_AUTH = 0x901,
124 NDMP_CONNECT_CLOSE = 0x902,
125 NDMP_CONNECT_SERVER_AUTH = 0x903,
127 NDMP_CONFIG_GET_HOST_INFO = 0x100,
128 NDMP_CONFIG_GET_BUTYPE_ATTR = 0x101, /* NDMP V2 */
129 NDMP_CONFIG_GET_CONNECTION_TYPE = 0x102,
130 NDMP_CONFIG_GET_AUTH_ATTR = 0x103,
131 NDMP_CONFIG_GET_BUTYPE_INFO = 0x10
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/titanic_51/usr/src/lib/libfru/libfrureg/
H A Dfrudefs.c42 { 0x0, "NO JEDEC CODE FOR THIS VENDOR" },
43 { 0x1, "AMD" },
44 { 0x2, "AMI" },
45 { 0x4, "Fujitsu" },
46 { 0x7, "Hitachi" },
47 { 0x8, "Inmos" },
48 { 0xb, "Intersil" },
49 { 0xd, "Mostek" },
50 { 0xe, "Freescale (formerly Motorola)" },
51 { 0x1
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/titanic_51/usr/src/data/perfmon/WSM-EP-DP/
H A DWestmereEP-DP_core_V2.json3 "EventCode": "0x14",
4 "UMask": "0x1",
8 "Counter": "0,1,2,3",
10 "MSRIndex": "0",
11 "MSRValue": "0",
12 "CounterMask": "0",
13 "Invert": "0",
14 "AnyThread": "0",
15 "EdgeDetect": "0",
16 "PEBS": "0",
2 { global() object
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/titanic_51/usr/src/data/perfmon/NHM-EP/
H A DNehalemEP_core_V2.json3 "EventCode": "0x14",
4 "UMask": "0x1",
8 "Counter": "0,1,2,3",
10 "MSRIndex": "0",
11 "MSRValue": "0",
12 "CounterMask": "0",
13 "Invert": "0",
14 "AnyThread": "0",
15 "EdgeDetect": "0",
16 "PEBS": "0",
2 { global() object
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/titanic_51/usr/src/data/perfmon/NHM-EX/
H A DNehalemEX_core_V2.json3 "EventCode": "0x14",
4 "UMask": "0x1",
8 "Counter": "0,1,2,3",
10 "MSRIndex": "0",
11 "MSRValue": "0",
12 "CounterMask": "0",
13 "Invert": "0",
14 "AnyThread": "0",
15 "EdgeDetect": "0",
16 "PEBS": "0",
2 { global() object
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/titanic_51/usr/src/data/perfmon/WSM-EP-SP/
H A DWestmereEP-SP_core_V2.json3 "EventCode": "0x14",
4 "UMask": "0x1",
8 "Counter": "0,1,2,3",
10 "MSRIndex": "0",
11 "MSRValue": "0",
12 "CounterMask": "0",
13 "Invert": "0",
14 "AnyThread": "0",
15 "EdgeDetect": "0",
16 "PEBS": "0",
2 { global() object
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/titanic_51/usr/src/data/perfmon/WSM-EX/
H A DWestmereEX_core_V2.json3 "EventCode": "0x14",
4 "UMask": "0x1",
8 "Counter": "0,1,2,3",
10 "MSRIndex": "0",
11 "MSRValue": "0",
12 "CounterMask": "0",
13 "Invert": "0",
14 "AnyThread": "0",
15 "EdgeDetect": "0",
16 "PEBS": "0",
2 { global() object
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/titanic_51/usr/src/uts/common/io/fibre-channel/fca/qlc/
H A Dql_api.c195 static int ql_flash_sbus_fpga = 0;
197 uint32_t ql_disable_aif = 0;
198 uint32_t ql_disable_msi = 0;
199 uint32_t ql_disable_msix = 0;
200 uint32_t ql_enable_ets = 0;
229 0x7e, 0x7d, 0x7c, 0x00, 0x7
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