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/illumos-gate/usr/src/lib/libc/sparc/fp/
H A D_Q_stoq.c59 m = ((u.l & 0x7f800000) >> 7) + 0x3f800000; in _Qp_stoq()
60 if (m == 0x3f800000) { in _Qp_stoq()
62 if (u.l & 0x7fffff) { in _Qp_stoq()
64 m = 0x3f810000; in _Qp_stoq()
65 f = u.l & 0x7fffff; in _Qp_stoq()
68 m -= 0x10000; in _Qp_stoq()
69 } while ((f & 0x7f800000) == 0); in _Qp_stoq()
70 u.l = (u.l & 0x80000000) | f; in _Qp_stoq()
72 m = 0; in _Qp_stoq()
74 } else if (m == 0x407f0000) { in _Qp_stoq()
[all …]
/illumos-gate/usr/src/uts/common/sys/
H A Dfile.h83 #define FOPEN 0xffffffff
84 #define FREAD 0x01 /* <sys/aiocb.h> LIO_READ must be identical */
85 #define FWRITE 0x02 /* <sys/aiocb.h> LIO_WRITE must be identical */
86 #define FNDELAY 0x04
87 #define FAPPEND 0x08
88 #define FSYNC 0x10 /* file (data+inode) integrity while writing */
89 #define FREVOKED 0x20 /* Object reuse Revoked file */
90 #define FDSYNC 0x40 /* file data only integrity while writing */
91 #define FNONBLOCK 0x80
93 #define FMASK 0xa0ff /* all flags that can be changed by F_SETFL */
[all …]
H A Dfilep.h54 #define FI_CACHED 0x100000
55 #define FI_PARTIAL_CACHE 0x200000
56 #define FI_NOCACHE 0x400000
58 #define FI_COMPRESSED 0x8 /* File compressed in ramdisk */
H A Dauxv_SPARC.h39 #define AV_SPARC_MUL32 0x0001 /* 32x32-bit smul/umul is efficient */
40 #define AV_SPARC_DIV32 0x0002 /* 32x32-bit sdiv/udiv is efficient */
41 #define AV_SPARC_FSMULD 0x0004 /* fsmuld is efficient */
42 #define AV_SPARC_V8PLUS 0x0008 /* V9 instructions available to 32-bit apps */
43 #define AV_SPARC_POPC 0x0010 /* popc is efficient */
44 #define AV_SPARC_VIS 0x0020 /* VIS instruction set supported */
45 #define AV_SPARC_VIS2 0x0040 /* VIS2 instruction set supported */
46 #define AV_SPARC_ASI_BLK_INIT 0x0080 /* ASI_BLK_INIT_xxx ASI */
47 #define AV_SPARC_FMAF 0x0100 /* Fused Multiply-Add */
49 #define AV_SPARC_VIS3 0x0400 /* VIS3 instruction set extensions */
[all …]
H A Dstmf_defines.h31 #define BIT_0 0x1
32 #define BIT_1 0x2
33 #define BIT_2 0x4
34 #define BIT_3 0x8
35 #define BIT_4 0x10
36 #define BIT_5 0x20
37 #define BIT_6 0x40
38 #define BIT_7 0x80
39 #define BIT_8 0x100
40 #define BIT_9 0x200
[all …]
H A Dauxv_386.h44 #define AV_386_FPU 0x00001 /* x87-style floating point */
45 #define AV_386_TSC 0x00002 /* rdtsc insn */
46 #define AV_386_CX8 0x00004 /* cmpxchg8b insn */
47 #define AV_386_SEP 0x00008 /* sysenter and sysexit */
48 #define AV_386_AMD_SYSC 0x00010 /* AMD's syscall and sysret */
49 #define AV_386_CMOV 0x00020 /* conditional move insns */
50 #define AV_386_MMX 0x00040 /* MMX insns */
51 #define AV_386_AMD_MMX 0x00080 /* AMD's MMX insns */
52 #define AV_386_AMD_3DNow 0x00100 /* AMD's 3Dnow! insns */
53 #define AV_386_AMD_3DNowx 0x00200 /* AMD's 3Dnow! extended insns */
[all …]
/illumos-gate/usr/src/test/bhyve-tests/tests/common/
H A Dpayload_common.h22 #define MEM_LOC_PAGE_TABLE_2M 0x200000
23 #define MEM_LOC_PAGE_TABLE_1G 0x204000
24 #define MEM_LOC_PAGE_TABLE_512G 0x205000
25 #define MEM_LOC_GDT 0x206000
26 #define MEM_LOC_TSS 0x206200
27 #define MEM_LOC_IDT 0x207000
28 #define MEM_LOC_HEAP 0x400000
29 #define MEM_LOC_STACK 0x7fff00
30 #define MEM_LOC_PAYLOAD 0x800000
31 #define MEM_LOC_ROM 0xffff000
[all …]
/illumos-gate/usr/src/uts/common/inet/ipf/
H A Dopts.h21 #define SOLARIS (0)
23 #define OPT_REMOVE 0x000001
24 #define OPT_DEBUG 0x000002
25 #define OPT_AUTHSTATS 0x000004
26 #define OPT_RAW 0x000008
27 #define OPT_LOG 0x000010
28 #define OPT_SHOWLIST 0x000020
29 #define OPT_VERBOSE 0x000040
30 #define OPT_DONOTHING 0x000080
31 #define OPT_HITS 0x000100
[all …]
/illumos-gate/usr/src/uts/i86pc/conf/
H A DMapfile.amd6432 PADDR = 0xC00000;
33 VADDR = 0xC00000;
44 PADDR = 0x400000;
45 VADDR = 0xFFFFFFFFFB800000;
58 PADDR = 0x800000;
59 VADDR = 0xFFFFFFFFFBc00000;
H A DMapfile32 PADDR = 0xC00000;
33 VADDR = 0xC00000;
47 PADDR = 0x400000;
48 VADDR = 0xFE800000;
61 PADDR = 0x800000;
62 VADDR = 0xFEc00000;
/illumos-gate/usr/src/common/mapfiles/common/
H A Dmap.default35 LOAD_SEGMENT text { VADDR = 0x10000 };
38 LOAD_SEGMENT text { VADDR = 0x100000000 };
47 LOAD_SEGMENT text { VADDR = 0x08048000 };
50 LOAD_SEGMENT text { VADDR = 0x400000 };
H A Dmap.below4G39 LOAD_SEGMENT text { VADDR = 0x80000000 };
44 LOAD_SEGMENT text { VADDR = 0x400000 };
H A Dmap.bssalign40 ALIGN = 0x400000;
/illumos-gate/usr/src/uts/common/io/bnx/include/
H A Dbits.h26 #define BIT_NONE 0x00
27 #define BIT_0 0x01
28 #define BIT_1 0x02
29 #define BIT_2 0x04
30 #define BIT_3 0x08
31 #define BIT_4 0x10
32 #define BIT_5 0x20
33 #define BIT_6 0x40
34 #define BIT_7 0x80
35 #define BIT_8 0x0100
[all …]
/illumos-gate/usr/src/uts/common/sys/scsi/adapters/pmcs/
H A Dpmcs_reg.h36 #define PMCS_VENDOR_ID 0x11F8
37 #define PMCS_DEVICE_ID 0x8001
39 #define PMCS_PM8001_REV_A 0
77 #define PMCS_MSGU_IBDB 0x04 /* Inbound Doorbell */
78 #define PMCS_MSGU_IBDB_CLEAR 0x20 /* InBound Doorbell Clear */
79 #define PMCS_MSGU_OBDB 0x3c /* OutBound Doorbell */
80 #define PMCS_MSGU_OBDB_CLEAR 0x40 /* OutBound Doorbell Clear */
81 #define PMCS_MSGU_SCRATCH0 0x44 /* Scratchpad 0 */
82 #define PMCS_MSGU_SCRATCH1 0x48 /* Scratchpad 1 */
83 #define PMCS_MSGU_SCRATCH2 0x4C /* Scratchpad 2 */
[all …]
/illumos-gate/usr/src/cmd/ipf/lib/
H A Dionames.c12 { IPOPT_NOP, 0x000001, 1, "nop" }, /* RFC791 */
13 { IPOPT_RR, 0x000002, 7, "rr" }, /* 1 route */
14 { IPOPT_ZSU, 0x000004, 3, "zsu" }, /* size ?? */
15 { IPOPT_MTUP, 0x000008, 3, "mtup" }, /* RFC1191 */
16 { IPOPT_MTUR, 0x000010, 3, "mtur" }, /* RFC1191 */
17 { IPOPT_ENCODE, 0x000020, 3, "encode" }, /* size ?? */
18 { IPOPT_TS, 0x000040, 8, "ts" }, /* 1 TS */
19 { IPOPT_TR, 0x000080, 3, "tr" }, /* RFC1393 */
20 { IPOPT_SECURITY,0x000100, 11, "sec" }, /* RFC1108 */
21 { IPOPT_SECURITY,0x000100, 11, "sec-class" }, /* RFC1108 */
[all …]
/illumos-gate/usr/src/uts/common/sys/nxge/
H A Dnxge_defs.h37 #define PIO 0x000000
38 #define FZC_PIO 0x080000
39 #define RESERVED_1 0x100000
40 #define FZC_MAC 0x180000
41 #define RESERVED_2 0x200000
42 #define FZC_IPP 0x280000
43 #define FFLP 0x300000
44 #define FZC_FFLP 0x380000
45 #define PIO_VADDR 0x400000
46 #define RESERVED_3 0x480000
[all …]
/illumos-gate/usr/src/uts/common/io/chxge/com/
H A Delmer0.h36 #define A_ELMER0_VERSION 0x100000
37 #define A_ELMER0_PHY_CFG 0x100004
38 #define A_ELMER0_INT_ENABLE 0x100008
39 #define A_ELMER0_INT_CAUSE 0x10000c
40 #define A_ELMER0_GPI_CFG 0x100010
41 #define A_ELMER0_GPI_STAT 0x100014
42 #define A_ELMER0_GPO 0x100018
43 #define A_ELMER0_PORT0_MI1_CFG 0x400000
45 #define S_MI1_MDI_ENABLE 0
58 #define M_MI1_SOF 0x3
[all …]
/illumos-gate/usr/src/uts/common/sys/rsm/
H A Drsm_common.h37 #define RSM_SUCCESS 0
130 #define RSM_DRIVER_PRIVATE_ID_BASE 0
131 #define RSM_DRIVER_PRIVATE_ID_END 0x0FFFFF
133 #define RSM_CLUSTER_TRANSPORT_ID_BASE 0x100000
134 #define RSM_CLUSTER_TRANSPORT_ID_END 0x1FFFFF
135 #define RSM_RSMLIB_ID_BASE 0x200000
136 #define RSM_RSMLIB_ID_END 0x2FFFFF
137 #define RSM_DLPI_ID_BASE 0x300000
138 #define RSM_DLPI_ID_END 0x3FFFFF
139 #define RSM_HPC_ID_BASE 0x400000
[all …]
/illumos-gate/usr/src/uts/sun4u/serengeti/sys/
H A Dsbdp_mem.h66 #define SG_MEM_TIMING1_CTL 0x400000
67 #define SG_MEM_TIMING2_CTL 0x400008
68 #define SG_MEM_TIMING3_CTL 0x400038
69 #define SG_MEM_TIMING4_CTL 0x400040
70 #define SG_MEM_DECODE0_ADR 0x400028
71 #define SG_MEM_DECODE1_ADR 0x400010
72 #define SG_MEM_DECODE2_ADR 0x400018
73 #define SG_MEM_DECODE3_ADR 0x400020
74 #define SG_MEM_CONTROL_ADR 0x400030
75 #define SG_EMU_ACTIVITY_STATUS 0x400050
[all …]
/illumos-gate/usr/src/data/perfmon/GLP/
H A Dgoldmontplus_matrix_v1.01.json5 "MATRIX_VALUE": "0x0001 ",
6 "MATRIX_REGISTER": "0,1",
12 "MATRIX_VALUE": "0x0002 ",
13 "MATRIX_REGISTER": "0,1",
19 "MATRIX_VALUE": "0x0004 ",
20 "MATRIX_REGISTER": "0,1",
26 "MATRIX_VALUE": "0x0008 ",
27 "MATRIX_REGISTER": "0,1",
33 "MATRIX_VALUE": "0x0010 ",
34 "MATRIX_REGISTER": "0,1",
[all …]
/illumos-gate/usr/src/data/perfmon/GLM/
H A Dgoldmont_matrix_v13.json5 "MATRIX_VALUE": "0x0001 ",
6 "MATRIX_REGISTER": "0,1",
12 "MATRIX_VALUE": "0x0002 ",
13 "MATRIX_REGISTER": "0,1",
19 "MATRIX_VALUE": "0x0004 ",
20 "MATRIX_REGISTER": "0,1",
26 "MATRIX_VALUE": "0x0008 ",
27 "MATRIX_REGISTER": "0",
33 "MATRIX_VALUE": "0x0010 ",
34 "MATRIX_REGISTER": "0,1",
[all …]
/illumos-gate/usr/src/uts/common/sys/ib/clients/iser/
H A Diser_resource.h41 #define ISER_MAX_CTRLPDU_LEN 0x4000
42 #define ISER_MAX_TEXTPDU_LEN 0x4000
45 #define ISER_DEFAULT_BUFLEN 0x20000
78 #define ISER_MR_QUANTSIZE 0x400
79 #define ISER_MIN_CHUNKSIZE 0x100000 /* 1MB */
82 #define ISER_BUF_MR_CHUNKSIZE 0x8000000 /* 128MB */
83 #define ISER_BUF_POOL_MAX 0x40000000 /* 1GB */
86 #define ISER_BUF_MR_CHUNKSIZE 0x400000 /* 4MB */
87 #define ISER_BUF_POOL_MAX 0x4000000 /* 64MB */
92 #define ISER_MSG_MR_CHUNKSIZE 0x2000000 /* 32MB */
[all …]
/illumos-gate/usr/src/uts/common/sys/fibre-channel/impl/
H A Dfcph.h41 #define R_CTL_ROUTING 0xF0 /* mask for routing bits */
42 #define R_CTL_INFO 0x0F /* mask for information bits */
44 #define R_CTL_DEVICE_DATA 0x00 /* all I/O related frames */
45 #define R_CTL_EXTENDED_SVC 0x20 /* extended link services (PLOGI) */
46 #define R_CTL_FC4_SVC 0x30 /* FC-4 link services (FCP_LOGI) */
47 #define R_CTL_VIDEO_BUFF 0x40 /* not yet defined */
48 #define R_CTL_BASIC_SVC 0x80 /* basic link services (NOP) */
49 #define R_CTL_LINK_CTL 0xC0 /* ACKs, etc. */
52 #define R_CTL_UNCATEGORIZED 0x00
53 #define R_CTL_SOLICITED_DATA 0x01
[all …]
/illumos-gate/usr/src/man/man1/
H A Dppgsz.191 \fIsize\fR must be a supported page size (see \fBpagesize\fR(1)) or \fB0\fR, in
95 \fIsize\fR defaults to bytes and can be specified in octal (\fB0\fR), decimal,
96 or hexadecimal (\fB0x\fR). The numeric value can be qualified with \fBK\fR,
98 Terabytes, respectively. \fB4194304\fR, \fB0x400000\fR, \fB4096K\fR,
99 \fB0x1000K\fR, and \fB4M\fR are different ways to specify 4 Megabytes.
166 \fB\fB0\fR \fR

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