16f45ec7bSml29623 /* 26f45ec7bSml29623 * CDDL HEADER START 36f45ec7bSml29623 * 46f45ec7bSml29623 * The contents of this file are subject to the terms of the 56f45ec7bSml29623 * Common Development and Distribution License (the "License"). 66f45ec7bSml29623 * You may not use this file except in compliance with the License. 76f45ec7bSml29623 * 86f45ec7bSml29623 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 96f45ec7bSml29623 * or http://www.opensolaris.org/os/licensing. 106f45ec7bSml29623 * See the License for the specific language governing permissions 116f45ec7bSml29623 * and limitations under the License. 126f45ec7bSml29623 * 136f45ec7bSml29623 * When distributing Covered Code, include this CDDL HEADER in each 146f45ec7bSml29623 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 156f45ec7bSml29623 * If applicable, add the following below this CDDL HEADER, with the 166f45ec7bSml29623 * fields enclosed by brackets "[]" replaced with your own identifying 176f45ec7bSml29623 * information: Portions Copyright [yyyy] [name of copyright owner] 186f45ec7bSml29623 * 196f45ec7bSml29623 * CDDL HEADER END 206f45ec7bSml29623 */ 216f45ec7bSml29623 /* 22*4df55fdeSJanie Lu * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 236f45ec7bSml29623 * Use is subject to license terms. 246f45ec7bSml29623 */ 256f45ec7bSml29623 266f45ec7bSml29623 #ifndef _SYS_NXGE_NXGE_DEFS_H 276f45ec7bSml29623 #define _SYS_NXGE_NXGE_DEFS_H 286f45ec7bSml29623 296f45ec7bSml29623 #ifdef __cplusplus 306f45ec7bSml29623 extern "C" { 316f45ec7bSml29623 #endif 326f45ec7bSml29623 336f45ec7bSml29623 /* 346f45ec7bSml29623 * Block Address Assignment (24-bit base address) 356f45ec7bSml29623 * (bits [23:20]: block [19]: set to 1 for FZC ) 366f45ec7bSml29623 */ 376f45ec7bSml29623 #define PIO 0x000000 386f45ec7bSml29623 #define FZC_PIO 0x080000 396f45ec7bSml29623 #define RESERVED_1 0x100000 406f45ec7bSml29623 #define FZC_MAC 0x180000 416f45ec7bSml29623 #define RESERVED_2 0x200000 426f45ec7bSml29623 #define FZC_IPP 0x280000 436f45ec7bSml29623 #define FFLP 0x300000 446f45ec7bSml29623 #define FZC_FFLP 0x380000 456f45ec7bSml29623 #define PIO_VADDR 0x400000 466f45ec7bSml29623 #define RESERVED_3 0x480000 476f45ec7bSml29623 #define ZCP 0x500000 486f45ec7bSml29623 #define FZC_ZCP 0x580000 496f45ec7bSml29623 #define DMC 0x600000 506f45ec7bSml29623 #define FZC_DMC 0x680000 516f45ec7bSml29623 #define TXC 0x700000 526f45ec7bSml29623 #define FZC_TXC 0x780000 536f45ec7bSml29623 #define PIO_LDSV 0x800000 546f45ec7bSml29623 #define RESERVED_4 0x880000 556f45ec7bSml29623 #define PIO_LDGIM 0x900000 566f45ec7bSml29623 #define RESERVED_5 0x980000 576f45ec7bSml29623 #define PIO_IMASK0 0xa00000 586f45ec7bSml29623 #define RESERVED_6 0xa80000 596f45ec7bSml29623 #define PIO_IMASK1 0xb00000 606f45ec7bSml29623 #define RESERVED_7_START 0xb80000 616f45ec7bSml29623 #define RESERVED_7_END 0xc00000 626f45ec7bSml29623 #define FZC_PROM 0xc80000 636f45ec7bSml29623 #define RESERVED_8 0xd00000 646f45ec7bSml29623 #define FZC_PIM 0xd80000 656f45ec7bSml29623 #define RESERVED_9_START 0xe00000 666f45ec7bSml29623 #define RESERVED_9_END 0xf80000 676f45ec7bSml29623 686f45ec7bSml29623 /* PIO (0x000000) */ 696f45ec7bSml29623 706f45ec7bSml29623 716f45ec7bSml29623 /* FZC_PIO (0x080000) */ 726f45ec7bSml29623 #define LDGITMRES (FZC_PIO + 0x00008) /* timer resolution */ 736f45ec7bSml29623 #define SID (FZC_PIO + 0x10200) /* 64 LDG, INT data */ 746f45ec7bSml29623 #define LDG_NUM (FZC_PIO + 0x20000) /* 69 LDs */ 756f45ec7bSml29623 766f45ec7bSml29623 776f45ec7bSml29623 786f45ec7bSml29623 /* FZC_IPP (0x280000) */ 796f45ec7bSml29623 806f45ec7bSml29623 816f45ec7bSml29623 /* FFLP (0x300000), Header Parser */ 826f45ec7bSml29623 836f45ec7bSml29623 /* PIO_VADDR (0x400000), PIO Virtaul DMA Address */ 846f45ec7bSml29623 /* ?? how to access DMA via PIO_VADDR? */ 856f45ec7bSml29623 #define VADDR (PIO_VADDR + 0x00000) /* ?? not for driver */ 866f45ec7bSml29623 876f45ec7bSml29623 886f45ec7bSml29623 /* ZCP (0x500000), Neptune Only */ 896f45ec7bSml29623 906f45ec7bSml29623 916f45ec7bSml29623 /* FZC_ZCP (0x580000), Neptune Only */ 926f45ec7bSml29623 936f45ec7bSml29623 946f45ec7bSml29623 /* DMC (0x600000), register offset (32 DMA channels) */ 956f45ec7bSml29623 966f45ec7bSml29623 /* Transmit Ring Register Offset (32 Channels) */ 976f45ec7bSml29623 #define TX_RNG_CFIG (DMC + 0x40000) 986f45ec7bSml29623 #define TX_RING_HDH (DMC + 0x40008) 996f45ec7bSml29623 #define TX_RING_HDL (DMC + 0x40010) 1006f45ec7bSml29623 #define TX_RING_KICK (DMC + 0x40018) 1016f45ec7bSml29623 /* Transmit Operations (32 Channels) */ 1026f45ec7bSml29623 #define TX_ENT_MSK (DMC + 0x40020) 1036f45ec7bSml29623 #define TX_CS (DMC + 0x40028) 1046f45ec7bSml29623 #define TXDMA_MBH (DMC + 0x40030) 1056f45ec7bSml29623 #define TXDMA_MBL (DMC + 0x40038) 1066f45ec7bSml29623 #define TX_DMA_PRE_ST (DMC + 0x40040) 1076f45ec7bSml29623 #define TX_RNG_ERR_LOGH (DMC + 0x40048) 1086f45ec7bSml29623 #define TX_RNG_ERR_LOGL (DMC + 0x40050) 1096f45ec7bSml29623 #if OLD 1106f45ec7bSml29623 #define SH_TX_RNG_ERR_LOGH (DMC + 0x40058) 1116f45ec7bSml29623 #define SH_TX_RNG_ERR_LOGL (DMC + 0x40060) 1126f45ec7bSml29623 #endif 1136f45ec7bSml29623 1146f45ec7bSml29623 /* FZC_DMC RED Initial Random Value register offset (global) */ 1156f45ec7bSml29623 #define RED_RAN_INIT (FZC_DMC + 0x00068) 1166f45ec7bSml29623 1176f45ec7bSml29623 #define RX_ADDR_MD (FZC_DMC + 0x00070) 1186f45ec7bSml29623 1196f45ec7bSml29623 /* FZC_DMC Ethernet Timeout Countue register offset (global) */ 1206f45ec7bSml29623 #define EING_TIMEOUT (FZC_DMC + 0x00078) 1216f45ec7bSml29623 1226f45ec7bSml29623 /* RDC Table */ 1236f45ec7bSml29623 #define RDC_TBL (FZC_DMC + 0x10000) /* 256 * 8 */ 1246f45ec7bSml29623 1256f45ec7bSml29623 /* FZC_DMC partitioning support register offset (32 channels) */ 1266f45ec7bSml29623 1276f45ec7bSml29623 #define TX_LOG_PAGE_VLD (FZC_DMC + 0x40000) 1286f45ec7bSml29623 #define TX_LOG_MASK1 (FZC_DMC + 0x40008) 1296f45ec7bSml29623 #define TX_LOG_VAL1 (FZC_DMC + 0x40010) 1306f45ec7bSml29623 #define TX_LOG_MASK2 (FZC_DMC + 0x40018) 1316f45ec7bSml29623 #define TX_LOG_VAL2 (FZC_DMC + 0x40020) 1326f45ec7bSml29623 #define TX_LOG_PAGE_RELO1 (FZC_DMC + 0x40028) 1336f45ec7bSml29623 #define TX_LOG_PAGE_RELO2 (FZC_DMC + 0x40030) 1346f45ec7bSml29623 #define TX_LOG_PAGE_HDL (FZC_DMC + 0x40038) 1356f45ec7bSml29623 1366f45ec7bSml29623 #define TX_ADDR_MOD (FZC_DMC + 0x41000) /* only one? */ 1376f45ec7bSml29623 1386f45ec7bSml29623 1396f45ec7bSml29623 /* FZC_DMC RED Parameters register offset (32 channels) */ 1406f45ec7bSml29623 #define RDC_RED_PARA1 (FZC_DMC + 0x30000) 1416f45ec7bSml29623 #define RDC_RED_PARA2 (FZC_DMC + 0x30008) 1426f45ec7bSml29623 /* FZC_DMC RED Discard Cound Register offset (32 channels) */ 1436f45ec7bSml29623 #define RED_DIS_CNT (FZC_DMC + 0x30010) 1446f45ec7bSml29623 1456f45ec7bSml29623 #if OLD /* This has been moved to TXC */ 1466f45ec7bSml29623 /* Transmit Ring Scheduler (per port) */ 1476f45ec7bSml29623 #define TX_DMA_MAP0 (FZC_DMC + 0x50000) 1486f45ec7bSml29623 #define TX_DMA_MAP1 (FZC_DMC + 0x50008) 1496f45ec7bSml29623 #define TX_DMA_MAP2 (FZC_DMC + 0x50010) 1506f45ec7bSml29623 #define TX_DMA_MAP3 (FZC_DMC + 0x50018) 1516f45ec7bSml29623 #endif 1526f45ec7bSml29623 1536f45ec7bSml29623 /* Transmit Ring Scheduler: DRR Weight (32 Channels) */ 1546f45ec7bSml29623 #define DRR_WT (FZC_DMC + 0x51000) 1556f45ec7bSml29623 #if OLD 1566f45ec7bSml29623 #define TXRNG_USE (FZC_DMC + 0x51008) 1576f45ec7bSml29623 #endif 1586f45ec7bSml29623 1596f45ec7bSml29623 /* TXC (0x700000)?? */ 1606f45ec7bSml29623 1616f45ec7bSml29623 1626f45ec7bSml29623 /* FZC_TXC (0x780000)?? */ 1636f45ec7bSml29623 1646f45ec7bSml29623 1656f45ec7bSml29623 /* 1666f45ec7bSml29623 * PIO_LDSV (0x800000) 1676f45ec7bSml29623 * Logical Device State Vector 0, 1, 2. 1686f45ec7bSml29623 * (69 logical devices, 8192 apart, partitioning control) 1696f45ec7bSml29623 */ 1706f45ec7bSml29623 #define LDSV0 (PIO_LDSV + 0x00000) /* RO (64 - 69) */ 1716f45ec7bSml29623 #define LDSV1 (PIO_LDSV + 0x00008) /* RO (32 - 63) */ 1726f45ec7bSml29623 #define LDSV2 (PIO_LDSV + 0x00010) /* RO ( 0 - 31) */ 1736f45ec7bSml29623 1746f45ec7bSml29623 /* 1756f45ec7bSml29623 * PIO_LDGIM (0x900000) 1766f45ec7bSml29623 * Logical Device Group Interrupt Management (64 groups). 1776f45ec7bSml29623 * (count 64, step 8192) 1786f45ec7bSml29623 */ 1796f45ec7bSml29623 #define LDGIMGN (PIO_LDGIMGN + 0x00000) /* RW */ 1806f45ec7bSml29623 1816f45ec7bSml29623 /* 1826f45ec7bSml29623 * PIO_IMASK0 (0xA000000) 1836f45ec7bSml29623 * 1846f45ec7bSml29623 * Logical Device Masks 0, 1. 1856f45ec7bSml29623 * (64 logical devices, 8192 apart, partitioning control) 1866f45ec7bSml29623 */ 1876f45ec7bSml29623 #define LD_IM0 (PIO_IMASK0 + 0x00000) /* RW ( 0 - 63) */ 1886f45ec7bSml29623 1896f45ec7bSml29623 /* 1906f45ec7bSml29623 * PIO_IMASK0 (0xB000000) 1916f45ec7bSml29623 * 1926f45ec7bSml29623 * Logical Device Masks 0, 1. 1936f45ec7bSml29623 * (5 logical devices, 8192 apart, partitioning control) 1946f45ec7bSml29623 */ 1956f45ec7bSml29623 #define LD_IM1 (PIO_IMASK1 + 0x00000) /* RW (64 - 69) */ 1966f45ec7bSml29623 1976f45ec7bSml29623 1986f45ec7bSml29623 /* DMC/TMC CSR size */ 199678453a8Sspeer #define DMA_CSR_SLL 9 /* Used to calculate VR addresses */ 200678453a8Sspeer #define DMA_CSR_SIZE (1 << DMA_CSR_SLL) /* 512 */ 201678453a8Sspeer #define DMA_CSR_MASK 0xff /* Used to calculate VR addresses */ 202678453a8Sspeer /* 203678453a8Sspeer * That is, each DMA CSR set must fit into a 512 byte space. 204678453a8Sspeer * If you subtract DMC (0x60000) from each DMA register definition, 205678453a8Sspeer * what you have left over is currently less than 255 (0xff) 206678453a8Sspeer */ 207678453a8Sspeer #define DMA_CSR_MIN_PAGE_SIZE (2 * DMA_CSR_SIZE) /* 1024 */ 208678453a8Sspeer /* 209678453a8Sspeer * There are 2 subpages per page in a VR. 210678453a8Sspeer */ 211678453a8Sspeer #define VDMA_CSR_SIZE (8 * DMA_CSR_MIN_PAGE_SIZE) /* 0x2000 */ 212678453a8Sspeer /* 213678453a8Sspeer * There are 8 pages in a VR. 214678453a8Sspeer */ 2156f45ec7bSml29623 2166f45ec7bSml29623 /* 2176f45ec7bSml29623 * Define the Default RBR, RCR 2186f45ec7bSml29623 */ 21930ac2e7bSml29623 #define RBR_DEFAULT_MAX_BLKS 8192 /* each entry (16 blockaddr/64B) */ 2206f45ec7bSml29623 #define RBR_NBLK_PER_LINE 16 /* 16 block addresses per 64 B line */ 2216f45ec7bSml29623 #define RBR_DEFAULT_MAX_LEN (RBR_DEFAULT_MAX_BLKS) 2226f45ec7bSml29623 #define RBR_DEFAULT_MIN_LEN 1 22330ac2e7bSml29623 #define RCR_DEFAULT_MAX 8192 2246f45ec7bSml29623 2256f45ec7bSml29623 #define SW_OFFSET_NO_OFFSET 0 2266f45ec7bSml29623 #define SW_OFFSET_64 1 /* 64 bytes */ 2276f45ec7bSml29623 #define SW_OFFSET_128 2 /* 128 bytes */ 228*4df55fdeSJanie Lu /* The following additional offsets are defined for Neptune-L and RF-NIU */ 229*4df55fdeSJanie Lu #define SW_OFFSET_192 3 230*4df55fdeSJanie Lu #define SW_OFFSET_256 4 231*4df55fdeSJanie Lu #define SW_OFFSET_320 5 232*4df55fdeSJanie Lu #define SW_OFFSET_384 6 233*4df55fdeSJanie Lu #define SW_OFFSET_448 7 2346f45ec7bSml29623 23530ac2e7bSml29623 #define TDC_DEFAULT_MAX 8192 2366f45ec7bSml29623 /* 2376f45ec7bSml29623 * RBR block descriptor is 32 bits (bits [43:12] 2386f45ec7bSml29623 */ 2396f45ec7bSml29623 #define RBR_BKADDR_SHIFT 12 2406f45ec7bSml29623 2416f45ec7bSml29623 2426f45ec7bSml29623 #define RCR_DEFAULT_MAX_BLKS 4096 /* each entry (8 blockaddr/64B) */ 2436f45ec7bSml29623 #define RCR_NBLK_PER_LINE 8 /* 8 block addresses per 64 B line */ 2446f45ec7bSml29623 #define RCR_DEFAULT_MAX_LEN (RCR_DEFAULT_MAX_BLKS) 2456f45ec7bSml29623 #define RCR_DEFAULT_MIN_LEN 1 2466f45ec7bSml29623 2476f45ec7bSml29623 /* DMA Channels. */ 2486f45ec7bSml29623 #define NXGE_MAX_DMCS (NXGE_MAX_RDCS + NXGE_MAX_TDCS) 2496f45ec7bSml29623 #define NXGE_MAX_RDCS 16 2506f45ec7bSml29623 #define NXGE_MAX_TDCS 24 2516f45ec7bSml29623 #define NXGE_MAX_TDCS_NIU 16 2526f45ec7bSml29623 /* 2536f45ec7bSml29623 * original mapping from Hypervisor 2546f45ec7bSml29623 */ 2556f45ec7bSml29623 #ifdef ORIGINAL 2566f45ec7bSml29623 #define NXGE_N2_RXDMA_START_LDG 0 2576f45ec7bSml29623 #define NXGE_N2_TXDMA_START_LDG 16 2586f45ec7bSml29623 #define NXGE_N2_MIF_LDG 32 2596f45ec7bSml29623 #define NXGE_N2_MAC_0_LDG 33 2606f45ec7bSml29623 #define NXGE_N2_MAC_1_LDG 34 2616f45ec7bSml29623 #define NXGE_N2_SYS_ERROR_LDG 35 2626f45ec7bSml29623 #endif 2636f45ec7bSml29623 2646f45ec7bSml29623 #define NXGE_N2_RXDMA_START_LDG 19 2656f45ec7bSml29623 #define NXGE_N2_TXDMA_START_LDG 27 2666f45ec7bSml29623 #define NXGE_N2_MIF_LDG 17 2676f45ec7bSml29623 #define NXGE_N2_MAC_0_LDG 16 2686f45ec7bSml29623 #define NXGE_N2_MAC_1_LDG 35 2696f45ec7bSml29623 #define NXGE_N2_SYS_ERROR_LDG 18 2706f45ec7bSml29623 #define NXGE_N2_LDG_GAP 17 2716f45ec7bSml29623 2726f45ec7bSml29623 #define NXGE_MAX_RDC_GRPS 8 2736f45ec7bSml29623 2746f45ec7bSml29623 /* 2756f45ec7bSml29623 * Max. ports per Neptune and NIU 2766f45ec7bSml29623 */ 2776f45ec7bSml29623 #define NXGE_MAX_PORTS 4 2786f45ec7bSml29623 #define NXGE_PORTS_NEPTUNE 4 2796f45ec7bSml29623 #define NXGE_PORTS_NIU 2 2806f45ec7bSml29623 281678453a8Sspeer /* 282678453a8Sspeer * Virtualization Regions. 283678453a8Sspeer */ 284678453a8Sspeer #define NXGE_MAX_VRS 8 285678453a8Sspeer 286da14cebeSEric Cheng /* 287da14cebeSEric Cheng * TDC groups are used exclusively for the purpose of Hybrid I/O 288da14cebeSEric Cheng * TX needs one group for each VR 289da14cebeSEric Cheng */ 290da14cebeSEric Cheng #define NXGE_MAX_TDC_GROUPS (NXGE_MAX_VRS) 291da14cebeSEric Cheng 2926f45ec7bSml29623 /* Max. RDC table groups */ 2936f45ec7bSml29623 #define NXGE_MAX_RDC_GROUPS 8 2946f45ec7bSml29623 #define NXGE_MAX_RDCS 16 2956f45ec7bSml29623 #define NXGE_MAX_DMAS 32 2966f45ec7bSml29623 2976f45ec7bSml29623 #define NXGE_MAX_MACS_XMACS 16 2986f45ec7bSml29623 #define NXGE_MAX_MACS_BMACS 8 2996f45ec7bSml29623 #define NXGE_MAX_MACS (NXGE_MAX_PORTS * NXGE_MAX_MACS_XMACS) 3006f45ec7bSml29623 3016f45ec7bSml29623 #define NXGE_MAX_VLANS 4096 3026f45ec7bSml29623 #define VLAN_ETHERTYPE (0x8100) 3036f45ec7bSml29623 3046f45ec7bSml29623 3056f45ec7bSml29623 /* Scaling factor for RBR (receive block ring) */ 3066f45ec7bSml29623 #define RBR_SCALE_1 0 3076f45ec7bSml29623 #define RBR_SCALE_2 1 3086f45ec7bSml29623 #define RBR_SCALE_3 2 3096f45ec7bSml29623 #define RBR_SCALE_4 3 3106f45ec7bSml29623 #define RBR_SCALE_5 4 3116f45ec7bSml29623 #define RBR_SCALE_6 5 3126f45ec7bSml29623 #define RBR_SCALE_7 6 3136f45ec7bSml29623 #define RBR_SCALE_8 7 3146f45ec7bSml29623 3156f45ec7bSml29623 3166f45ec7bSml29623 #define MAX_PORTS_PER_NXGE 4 3176f45ec7bSml29623 #define MAX_MACS 32 3186f45ec7bSml29623 3196f45ec7bSml29623 #define TX_GATHER_POINTER_SZ 8 3206f45ec7bSml29623 #define TX_GP_PER_BLOCK 8 3216f45ec7bSml29623 #define TX_DEFAULT_MAX_GPS 1024 /* Max. # of gather pointers */ 3226f45ec7bSml29623 #define TX_DEFAULT_JUMBO_MAX_GPS 4096 /* Max. # of gather pointers */ 3236f45ec7bSml29623 #define TX_DEFAULT_MAX_LEN (TX_DEFAULT_MAX_GPS/TX_GP_PER_BLOCK) 3246f45ec7bSml29623 #define TX_DEFAULT_JUMBO_MAX_LEN (TX_DEFAULT_JUMBO_MAX_GPS/TX_GP_PER_BLOCK) 3256f45ec7bSml29623 3266f45ec7bSml29623 #define TX_RING_THRESHOLD (TX_DEFAULT_MAX_GPS/4) 3276f45ec7bSml29623 #define TX_RING_JUMBO_THRESHOLD (TX_DEFAULT_JUMBO_MAX_GPS/4) 3286f45ec7bSml29623 3296f45ec7bSml29623 #define TRANSMIT_HEADER_SIZE 16 /* 16 B frame header */ 3306f45ec7bSml29623 3316f45ec7bSml29623 #define TX_DESC_SAD_SHIFT 0 3326f45ec7bSml29623 #define TX_DESC_SAD_MASK 0x00000FFFFFFFFFFFULL /* start address */ 3336f45ec7bSml29623 #define TX_DESC_TR_LEN_SHIFT 44 3346f45ec7bSml29623 #define TX_DESC_TR_LEN_MASK 0x00FFF00000000000ULL /* Transfer Length */ 3356f45ec7bSml29623 #define TX_DESC_NUM_PTR_SHIFT 58 3366f45ec7bSml29623 #define TX_DESC_NUM_PTR_MASK 0x2C00000000000000ULL /* gather pointers */ 3376f45ec7bSml29623 #define TX_DESC_MASK_SHIFT 62 3386f45ec7bSml29623 #define TX_DESC_MASK_MASK 0x4000000000000000ULL /* Mark bit */ 3396f45ec7bSml29623 #define TX_DESC_SOP_SHIF 63 3406f45ec7bSml29623 #define TX_DESC_NUM_MASK 0x8000000000000000ULL /* Start of packet */ 3416f45ec7bSml29623 3426f45ec7bSml29623 #define TCAM_FLOW_KEY_MAX_CLASS 12 3436f45ec7bSml29623 #define TCAM_L3_MAX_USER_CLASS 4 344*4df55fdeSJanie Lu #define TCAM_MAX_ENTRY 256 3456f45ec7bSml29623 #define TCAM_NIU_TCAM_MAX_ENTRY 128 3466f45ec7bSml29623 #define TCAM_NXGE_TCAM_MAX_ENTRY 256 347*4df55fdeSJanie Lu #define NXGE_L2_PROG_CLS 2 348*4df55fdeSJanie Lu #define NXGE_L3_PROG_CLS 4 3496f45ec7bSml29623 3506f45ec7bSml29623 3516f45ec7bSml29623 3526f45ec7bSml29623 /* TCAM entry formats */ 3536f45ec7bSml29623 #define TCAM_IPV4_5TUPLE_FORMAT 0x00 3546f45ec7bSml29623 #define TCAM_IPV6_5TUPLE_FORMAT 0x01 3556f45ec7bSml29623 #define TCAM_ETHERTYPE_FORMAT 0x02 3566f45ec7bSml29623 3576f45ec7bSml29623 3586f45ec7bSml29623 /* TCAM */ 3596f45ec7bSml29623 #define TCAM_SELECT_IPV6 0x01 3606f45ec7bSml29623 #define TCAM_LOOKUP 0x04 3616f45ec7bSml29623 #define TCAM_DISCARD 0x08 3626f45ec7bSml29623 3636f45ec7bSml29623 /* FLOW Key */ 3646f45ec7bSml29623 #define FLOW_L4_1_34_BYTES 0x10 3656f45ec7bSml29623 #define FLOW_L4_1_78_BYTES 0x11 3666f45ec7bSml29623 #define FLOW_L4_0_12_BYTES (0x10 << 2) 3676f45ec7bSml29623 #define FLOW_L4_0_56_BYTES (0x11 << 2) 3686f45ec7bSml29623 #define FLOW_PROTO_NEXT 0x10 3696f45ec7bSml29623 #define FLOW_IPDA 0x20 3706f45ec7bSml29623 #define FLOW_IPSA 0x40 3716f45ec7bSml29623 #define FLOW_VLAN 0x80 3726f45ec7bSml29623 #define FLOW_L2DA 0x100 3736f45ec7bSml29623 #define FLOW_PORT 0x200 3746f45ec7bSml29623 3756f45ec7bSml29623 /* TCAM */ 3766f45ec7bSml29623 #define MAX_EFRAME 11 3776f45ec7bSml29623 3786f45ec7bSml29623 #define TCAM_USE_L2RDC_FLOW_LOOKUP 0x00 3796f45ec7bSml29623 #define TCAM_USE_OFFSET_DONE 0x01 3806f45ec7bSml29623 #define TCAM_OVERRIDE_L2_FLOW_LOOKUP 0x02 3816f45ec7bSml29623 #define TCAM_OVERRIDE_L2_USE_OFFSET 0x03 3826f45ec7bSml29623 3836f45ec7bSml29623 /* 3846f45ec7bSml29623 * FCRAM (Hashing): 3856f45ec7bSml29623 * 1. IPv4 exact match 3866f45ec7bSml29623 * 2. IPv6 exact match 3876f45ec7bSml29623 * 3. IPv4 Optimistic match 3886f45ec7bSml29623 * 4. IPv6 Optimistic match 3896f45ec7bSml29623 * 3906f45ec7bSml29623 */ 3916f45ec7bSml29623 #define FCRAM_IPV4_EXT_MATCH 0x00 3926f45ec7bSml29623 #define FCRAM_IPV6_EXT_MATCH 0x01 3936f45ec7bSml29623 #define FCRAM_IPV4_OPTI_MATCH 0x02 3946f45ec7bSml29623 #define FCRAM_IPV6_OPTI_MATCH 0x03 3956f45ec7bSml29623 3966f45ec7bSml29623 3976f45ec7bSml29623 #define NXGE_HASH_MAX_ENTRY 256 3986f45ec7bSml29623 3996f45ec7bSml29623 4006f45ec7bSml29623 #define MAC_ADDR_LENGTH 6 4016f45ec7bSml29623 4026f45ec7bSml29623 /* convert values */ 4036f45ec7bSml29623 #define NXGE_BASE(x, y) (((y) << (x ## _SHIFT)) & (x ## _MASK)) 4046f45ec7bSml29623 #define NXGE_VAL(x, y) (((y) & (x ## _MASK)) >> (x ## _SHIFT)) 4056f45ec7bSml29623 4066f45ec7bSml29623 /* 4076f45ec7bSml29623 * Locate the DMA channel start offset (PIO_VADDR) 4086f45ec7bSml29623 * (DMA virtual address space of the PIO block) 4096f45ec7bSml29623 */ 4106f45ec7bSml29623 #define TDMC_PIOVADDR_OFFSET(channel) (2 * DMA_CSR_SIZE * channel) 4116f45ec7bSml29623 #define RDMC_PIOVADDR_OFFSET(channel) (TDMC_OFFSET(channel) + DMA_CSR_SIZE) 4126f45ec7bSml29623 4136f45ec7bSml29623 /* 4146f45ec7bSml29623 * PIO access using the DMC block directly (DMC) 4156f45ec7bSml29623 */ 4166f45ec7bSml29623 #define DMC_OFFSET(channel) (DMA_CSR_SIZE * channel) 4176f45ec7bSml29623 #define TDMC_OFFSET(channel) (TX_RNG_CFIG + DMA_CSR_SIZE * channel) 4186f45ec7bSml29623 4196f45ec7bSml29623 /* 4206f45ec7bSml29623 * Number of logical pages. 4216f45ec7bSml29623 */ 4226f45ec7bSml29623 #define NXGE_MAX_LOGICAL_PAGES 2 4236f45ec7bSml29623 4246f45ec7bSml29623 #ifdef SOLARIS 4256f45ec7bSml29623 #ifndef i386 4266f45ec7bSml29623 #define _BIT_FIELDS_BIG_ENDIAN _BIT_FIELDS_HTOL 4276f45ec7bSml29623 #else 4286f45ec7bSml29623 #define _BIT_FIELDS_LITTLE_ENDIAN _BIT_FIELDS_LTOH 4296f45ec7bSml29623 #endif 4306f45ec7bSml29623 #else 4316f45ec7bSml29623 #define _BIT_FIELDS_LITTLE_ENDIAN _LITTLE_ENDIAN_BITFIELD 4326f45ec7bSml29623 #endif 4336f45ec7bSml29623 4346f45ec7bSml29623 #define MAX_PIO_RETRIES 32 4356f45ec7bSml29623 4366f45ec7bSml29623 #define IS_PORT_NUM_VALID(portn)\ 4376f45ec7bSml29623 (portn < 4) 4386f45ec7bSml29623 4396f45ec7bSml29623 /* 4406f45ec7bSml29623 * The following macros expect unsigned input values. 4416f45ec7bSml29623 */ 4426f45ec7bSml29623 #define TXDMA_CHANNEL_VALID(cn) (cn < NXGE_MAX_TDCS) 4436f45ec7bSml29623 #define TXDMA_PAGE_VALID(pn) (pn < NXGE_MAX_LOGICAL_PAGES) 4446f45ec7bSml29623 #define TXDMA_FUNC_VALID(fn) (fn < MAX_PORTS_PER_NXGE) 4456f45ec7bSml29623 #define FUNC_VALID(n) (n < MAX_PORTS_PER_NXGE) 4466f45ec7bSml29623 4476f45ec7bSml29623 /* 4486f45ec7bSml29623 * DMA channel binding definitions. 4496f45ec7bSml29623 */ 4506f45ec7bSml29623 #define VIR_PAGE_INDEX_MAX 8 4516f45ec7bSml29623 #define VIR_SUB_REGIONS 2 4526f45ec7bSml29623 #define VIR_DMA_BIND 1 4536f45ec7bSml29623 4546f45ec7bSml29623 #define SUBREGION_VALID(n) (n < VIR_SUB_REGIONS) 4556f45ec7bSml29623 #define VIR_PAGE_INDEX_VALID(n) (n < VIR_PAGE_INDEX_MAX) 4566f45ec7bSml29623 #define VRXDMA_CHANNEL_VALID(n) (n < NXGE_MAX_RDCS) 4576f45ec7bSml29623 4586f45ec7bSml29623 /* 4596f45ec7bSml29623 * Logical device definitions. 4606f45ec7bSml29623 */ 4616f45ec7bSml29623 #define NXGE_INT_MAX_LD 69 4626f45ec7bSml29623 #define NXGE_INT_MAX_LDG 64 4636f45ec7bSml29623 4646f45ec7bSml29623 #define NXGE_RDMA_LD_START 0 4656f45ec7bSml29623 #define NXGE_TDMA_LD_START 32 4666f45ec7bSml29623 #define NXGE_MIF_LD 63 4676f45ec7bSml29623 #define NXGE_MAC_LD_PORT0 64 4686f45ec7bSml29623 #define NXGE_MAC_LD_PORT1 65 4696f45ec7bSml29623 #define NXGE_MAC_LD_PORT2 66 4706f45ec7bSml29623 #define NXGE_MAC_LD_PORT3 67 4716f45ec7bSml29623 #define NXGE_SYS_ERROR_LD 68 4726f45ec7bSml29623 4736f45ec7bSml29623 #define LDG_VALID(n) (n < NXGE_INT_MAX_LDG) 4746f45ec7bSml29623 #define LD_VALID(n) (n < NXGE_INT_MAX_LD) 4756f45ec7bSml29623 #define LD_RXDMA_LD_VALID(n) (n < NXGE_MAX_RDCS) 4766f45ec7bSml29623 #define LD_TXDMA_LD_VALID(n) (n >= NXGE_MAX_RDCS && \ 4776f45ec7bSml29623 ((n - NXGE_MAX_RDCS) < NXGE_MAX_TDCS))) 4786f45ec7bSml29623 #define LD_MAC_VALID(n) (IS_PORT_NUM_VALID(n)) 4796f45ec7bSml29623 4806f45ec7bSml29623 #define LD_TIMER_MAX 0x3f 4816f45ec7bSml29623 #define LD_INTTIMER_VALID(n) (n <= LD_TIMER_MAX) 4826f45ec7bSml29623 4836f45ec7bSml29623 /* System Interrupt Data */ 4846f45ec7bSml29623 #define SID_VECTOR_MAX 0x1f 4856f45ec7bSml29623 #define SID_VECTOR_VALID(n) (n <= SID_VECTOR_MAX) 4866f45ec7bSml29623 4876f45ec7bSml29623 #define NXGE_COMPILE_32 4886f45ec7bSml29623 4896f45ec7bSml29623 #ifdef __cplusplus 4906f45ec7bSml29623 } 4916f45ec7bSml29623 #endif 4926f45ec7bSml29623 4936f45ec7bSml29623 #endif /* _SYS_NXGE_NXGE_DEFS_H */ 494