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/linux/drivers/gpu/drm/meson/
H A Dmeson_registers.h18 #define VPP2_DUMMY_DATA 0x1900
19 #define VPP2_LINE_IN_LENGTH 0x1901
20 #define VPP2_PIC_IN_HEIGHT 0x1902
21 #define VPP2_SCALE_COEF_IDX 0x1903
22 #define VPP2_SCALE_COEF 0x1904
23 #define VPP2_VSC_REGION12_STARTP 0x1905
24 #define VPP2_VSC_REGION34_STARTP 0x1906
25 #define VPP2_VSC_REGION4_ENDP 0x1907
26 #define VPP2_VSC_START_PHASE_STEP 0x1908
27 #define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h26 #define ixATTR00 0x0000
27 #define ixATTR01 0x0001
28 #define ixATTR02 0x0002
29 #define ixATTR03 0x0003
30 #define ixATTR04 0x0004
31 #define ixATTR05 0x0005
32 #define ixATTR06 0x0006
33 #define ixATTR07 0x0007
34 #define ixATTR08 0x0008
35 #define ixATTR09 0x0009
[all …]
H A Ddce_8_0_d.h27 #define mmPIPE0_PG_CONFIG 0x1760
28 #define mmPIPE0_PG_ENABLE 0x1761
29 #define mmPIPE0_PG_STATUS 0x1762
30 #define mmPIPE1_PG_CONFIG 0x1764
31 #define mmPIPE1_PG_ENABLE 0x1765
32 #define mmPIPE1_PG_STATUS 0x1766
33 #define mmPIPE2_PG_CONFIG 0x1768
34 #define mmPIPE2_PG_ENABLE 0x1769
35 #define mmPIPE2_PG_STATUS 0x176a
36 #define mmPIPE3_PG_CONFIG 0x176c
[all …]
/linux/sound/hda/codecs/
H A Dsigmatel.c220 #define AC_VERB_IDT_SET_POWER_MAP 0x7ec
221 #define AC_VERB_IDT_GET_POWER_MAP 0xfec
224 0x0a, 0x0b, 0x0c, 0xd, 0x0e,
225 0x0f, 0x10, 0x1
[all...]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm8650.dtsi42 #clock-cells = <0>;
47 #clock-cells = <0>;
52 #clock-cells = <0>;
61 #clock-cells = <0>;
71 #size-cells = <0>;
73 cpu0: cpu@0 {
76 reg = <0 0>;
83 clocks = <&cpufreq_hw 0>;
93 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0 0x100>;
[all …]
H A Dglymur.dtsi41 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0x0 0x0>;
49 power-domains = <&cpu_pd0>, <&scmi_perf 0>;
64 reg = <0x0 0x100>;
67 power-domains = <&cpu_pd1>, <&scmi_perf 0>;
76 reg = <0x0 0x200>;
79 power-domains = <&cpu_pd2>, <&scmi_perf 0>;
88 reg = <0x0 0x300>;
91 power-domains = <&cpu_pd3>, <&scmi_perf 0>;
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_1_0_offset.h27 // base address: 0x48
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
35 // base address: 0x3b4
36 …CRTC8_IDX 0x002d
38 …CRTC8_DATA 0x002d
40 …GENFC_WT 0x002e
42 …GENS1 0x002e
[all …]
H A Ddcn_3_0_1_offset.h27 // base address: 0x48
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
35 // base address: 0x3b4
36 …CRTC8_IDX 0x002d
38 …CRTC8_DATA 0x002d
40 …GENFC_WT 0x002e
42 …GENS1 0x002e
[all …]
H A Ddcn_4_1_0_offset.h11 // base address: 0x0
12 …DENTIST_DISPCLK_CNTL 0x0064
17 // base address: 0x0
18 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
20 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
22 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
24 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
26 …DP_DTO_DBUF_EN 0x0044
28 …DSCCLK3_DTO_PARAM 0x0045
30 …DSCCLK4_DTO_PARAM 0x0046
[all …]
H A Ddcn_3_5_1_offset.h7 // base address: 0x1300000
8 …OBAL_CAPABILITIES 0x4b7000
10 …NOR_VERSION 0x4b7000
12 …JOR_VERSION 0x4b7000
14 …TPUT_PAYLOAD_CAPABILITY 0x4b7001
16 …PUT_PAYLOAD_CAPABILITY 0x4b7001
18 …OBAL_CONTROL 0x4b7002
20 …KE_ENABLE 0x4b7003
22 …ATE_CHANGE_STATUS 0x4b7003
24 …OBAL_STATUS 0x4b7004
[all …]
H A Ddcn_3_5_0_offset.h28 // base address: 0x1300000
29 …OBAL_CAPABILITIES 0x4b7000
31 …NOR_VERSION 0x4b7000
33 …JOR_VERSION 0x4b7000
35 …TPUT_PAYLOAD_CAPABILITY 0x4b7001
37 …PUT_PAYLOAD_CAPABILITY 0x4b7001
39 …OBAL_CONTROL 0x4b7002
41 …KE_ENABLE 0x4b7003
43 …ATE_CHANGE_STATUS 0x4b7003
45 …OBAL_STATUS 0x4b7004
[all …]
H A Ddcn_2_0_0_offset.h27 // base address: 0x0
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
32 …VGA_RENDER_CONTROL 0x0000
34 …VGA_SEQUENCER_RESET_CONTROL 0x0001
36 …VGA_MODE_CONTROL 0x0002
38 …VGA_SURFACE_PITCH_SELECT 0x0003
40 …VGA_MEMORY_BASE_ADDRESS 0x0004
[all …]