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/freebsd/sys/contrib/device-tree/Bindings/arm/tegra/
H A Dnvidia,tegra20-ahb.txt9 Tegra20, Tegra30, and Tegra114 chips, the value must be <0x6000c004
10 0x10c>. For Tegra124, Tegra132 and Tegra210 chips, the value should
11 be be <0x6000c000 0x150>.
16 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
/freebsd/contrib/file/magic/Magdir/
H A Dunknown6 # 0x107 is 0407, 0x108 is 0410, and 0x109 is 0411; those are all PDP-11
11 # 0x10B is 0413; that's VAX demand-paged, but this is a short, not a
14 # binaries, so the first 16 bits of the file would contain 0x10B.
18 # 0x10C is 0414 and 0x10E is 0416; those *are* unknown.
20 #0 short 0x107 unknown machine executable
21 #>8 short >0 not stripped
22 #>15 byte >0 - version %ld
23 #0 short 0x108 unknown pure executable
24 #>8 short >0 not stripped
25 #>15 byte >0 - version %ld
[all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/ampere/emag/
H A Dpipeline.json4 "EventCode": "0x108",
10 "EventCode": "0x109",
16 "EventCode": "0x10a",
22 "EventCode": "0x10b",
28 "EventCode": "0x10c",
34 "EventCode": "0x10d",
40 "EventCode": "0x10e",
46 "EventCode": "0x10f",
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dzte,tdm.txt23 reg = <0x01487000 0x1000>;
28 pinctrl-0 = <&tdm_global_pin>;
29 zte,tdm-dma-sysctrl = <&sysctrl 0x10c 4>;
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap4-mcpdm.dtsi12 /* 0x4a100106 abe_pdm_ul_data.abe_pdm_ul_data ag25 */
13 OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0)
15 /* 0x4a100108 abe_pdm_dl_data.abe_pdm_dl_data af25 */
16 OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0)
18 /* 0x4a10010a abe_pdm_frame.abe_pdm_frame ae25 */
19 OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0)
21 /* 0x4a10010c abe_pdm_lb_clk.abe_pdm_lb_clk af26 */
22 OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0)
24 /* 0x4a10010e abe_clks.abe_clks ah26 */
25 OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0)
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/vf/
H A Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/freebsd/sys/arm/ti/omap4/
H A Domap4_smc.h33 #define L2CACHE_WRITE_DEBUG_REG 0x100
34 #define L2CACHE_CLEAN_INV_RANG 0x101
35 #define L2CACHE_WRITE_CTRL_REG 0x102
36 #define READ_AUX_CORE_REGS 0x103
37 #define MODIFY_AUX_CORE_0 0x104
38 #define WRITE_AUX_CORE_1 0x105
39 #define READ_WKG_CTRL_REG 0x106
40 #define CLEAR_WKG_CTRL_REG 0x107
41 #define SET_POWER_STATUS_REG 0x108
42 #define WRITE_AUXCTRL_REG 0x109
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/freebsd/sys/arm/ti/
H A Dti_mbox.h32 #define TI_MBOX_REVISION 0x00
33 #define TI_MBOX_SYSCONFIG 0x10
34 #define TI_MBOX_SYSCONFIG_SOFTRST 0x01
35 #define TI_MBOX_SYSCONFIG_SMARTIDLE (0x02 << 2)
36 #define TI_MBOX_MESSAGE(n) (0x40 + (n) * 0x4)
37 #define TI_MBOX_FIFOSTATUS(n) (0x80 + (n) * 0x4)
38 #define TI_MBOX_MSGSTATUS(n) (0xc0 + (n) * 0x4)
39 #define TI_MBOX_IRQSTATUS_RAW(n) (0x100 + (n) * 0x10)
40 #define TI_MBOX_IRQSTATUS_CLR(n) (0x104 + (n) * 0x10)
41 #define TI_MBOX_IRQENABLE_SET(n) (0x108 + (n) * 0x10)
[all …]
/freebsd/sys/contrib/dev/iwlwifi/
H A Diwl-scd.h33 iwl_set_bits_prph(trans, SCD_AGGR_SEL, 0); in iwl_scd_disable_agg()
38 iwl_write_prph(trans, SCD_TXFACT, IWL_MASK(0, 7)); in iwl_scd_activate_fifos()
43 iwl_write_prph(trans, SCD_TXFACT, 0); in iwl_scd_deactivate_fifos()
55 return SCD_BASE + 0x18 + chnl * 4; in SCD_QUEUE_WRPTR()
57 return SCD_BASE + 0x284 + (chnl - 20) * 4; in SCD_QUEUE_WRPTR()
63 return SCD_BASE + 0x68 + chnl * 4; in SCD_QUEUE_RDPTR()
65 return SCD_BASE + 0x2B4 + chnl * 4; in SCD_QUEUE_RDPTR()
71 return SCD_BASE + 0x10c + chnl * 4; in SCD_QUEUE_STATUS_BITS()
73 return SCD_BASE + 0x334 + chnl * 4; in SCD_QUEUE_STATUS_BITS()
80 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| in iwl_scd_txq_set_inactive()
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dscorpion_reg_map.h77 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
78 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
79 volatile char pad__1[0x8]; /* 0xc - 0x14 */
80 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
81 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
82 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
83 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
84 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
85 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
86 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
[all …]
/freebsd/contrib/netbsd-tests/lib/libcurses/tests/
H A Dstd_defines8 assign TRUE 0x01
9 assign FALSE 0x00
13 assign COLOR_BLACK 0x00
14 assign COLOR_RED 0x01
15 assign COLOR_GREEN 0x02
16 assign COLOR_YELLOW 0x03
17 assign COLOR_BLUE 0x04
18 assign COLOR_MAGENTA 0x05
19 assign COLOR_CYAN 0x06
20 assign COLOR_WHITE 0x07
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dam3.h8 #define AM3_CLKCTRL_OFFSET 0x0
12 #define AM3_L4LS_CLKCTRL_OFFSET 0x38
14 #define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38)
15 #define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c)
16 #define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40)
17 #define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44)
18 #define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48)
19 #define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c)
20 #define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50)
21 #define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60)
[all …]
/freebsd/tools/test/stress2/misc/
H A Dsyzkaller63.sh5 # fault virtual address = 0x20
7 # instruction pointer = 0x20:0xfa1a2c
8 # stack pointer = 0x28:0x27a41a80
9 # frame pointer = 0x28:0x27a41a98
10 # code segment = base 0x0, limit 0xfffff, type 0x1b
11 # = DPL 0, pres 1, def32 1, gran 1
12 # processor eflags = interrupt enabled, resume, IOPL = 0
19 # db_trace_self_wrapper(d,2048e3a0,27a41a40,20,c,...) at db_trace_self_wrapper+0x28/frame 0x27a418d0
20 # vpanic(146c355,27a4190c,27a4190c,27a41938,141f1d6,...) at vpanic+0xf4/frame 0x27a418ec
21 # panic(146c355,15010e8,0,fffff,1dfc39b,...) at panic+0x14/frame 0x27a41900
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dqoriq-mpic4.3.dtsi2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
37 #address-cells = <0>;
39 reg = <0x40000 0x40000>;
42 clock-frequency = <0x0>;
47 reg = <0x41100 0x100 0x41300 4>;
48 interrupts = <0 0 3 0
49 1 0 3 0
50 2 0 3 0
51 3 0 3 0>;
56 reg = <0x41600 0x200 0x44148 4>;
[all …]
/freebsd/sys/powerpc/mpc85xx/
H A Dlbc.h36 #define LBC85XX_BR(n) (0x0 + (8 * n)) /* Base register 0-7 */
37 #define LBC85XX_OR(n) (0x4 + (8 * n)) /* Options register 0-7 */
38 #define LBC85XX_MAR 0x068 /* UPM address register */
39 #define LBC85XX_MAMR 0x070 /* UPMA mode register */
40 #define LBC85XX_MBMR 0x074 /* UPMB mode register */
41 #define LBC85XX_MCMR 0x078 /* UPMC mode register */
42 #define LBC85XX_MRTPR 0x084 /* Memory refresh timer prescaler */
43 #define LBC85XX_MDR 0x088 /* UPM data register */
44 #define LBC85XX_LSOR 0x090 /* Special operation initiation */
45 #define LBC85XX_LURT 0x0a0 /* UPM refresh timer */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/hisilicon/
H A Dhi3620-hi4511.dts22 reg = <0x40000000 0x20000000>;
32 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
39 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
46 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
53 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
60 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
67 pinctrl-0 = <&board_pmx_pins>;
71 0x008 0x0 /* GPIO -- eFUSE_DOUT */
72 0x100 0x0 /* USIM_CLK & USIM_DATA (IOMG63) */
77 0x0f0 0x0
[all …]
/freebsd/sys/arm/freescale/imx/
H A Dimx6_anatopreg.h32 #define IMX6_ANALOG_CCM_PLL_ARM 0x000
33 #define IMX6_ANALOG_CCM_PLL_ARM_SET 0x004
34 #define IMX6_ANALOG_CCM_PLL_ARM_CLR 0x008
35 #define IMX6_ANALOG_CCM_PLL_ARM_TOG 0x00C
36 #define IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK 0x7F
39 #define IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK (0x03 << 16)
40 #define IMX6_ANALOG_CCM_PLL_USB1 0x010
41 #define IMX6_ANALOG_CCM_PLL_USB1_SET 0x014
42 #define IMX6_ANALOG_CCM_PLL_USB1_CLR 0x018
43 #define IMX6_ANALOG_CCM_PLL_USB1_TOG 0x01C
[all …]
/freebsd/sys/arm/include/
H A Dpl310.h37 #define PL310_CACHE_ID 0x000
38 #define CACHE_ID_RELEASE_SHIFT 0
39 #define CACHE_ID_RELEASE_MASK 0x3f
40 #define CACHE_ID_RELEASE_r0p0 0x00
41 #define CACHE_ID_RELEASE_r1p0 0x02
42 #define CACHE_ID_RELEASE_r2p0 0x04
43 #define CACHE_ID_RELEASE_r3p0 0x05
44 #define CACHE_ID_RELEASE_r3p1 0x06
45 #define CACHE_ID_RELEASE_r3p2 0x08
46 #define CACHE_ID_RELEASE_r3p3 0x09
[all …]
/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dst,stm32-rproc.yaml168 reg = <0x10000000 0x40000>,
169 <0x30000000 0x40000>,
170 <0x38000000 0x10000>;
174 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
175 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
176 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
182 reg = <0x10000000 0x40000>,
183 <0x30000000 0x40000>,
184 <0x38000000 0x10000>;
188 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
[all …]

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