Lines Matching +full:0 +full:x10c

37 #define PL310_CACHE_ID			0x000
38 #define CACHE_ID_RELEASE_SHIFT 0
39 #define CACHE_ID_RELEASE_MASK 0x3f
40 #define CACHE_ID_RELEASE_r0p0 0x00
41 #define CACHE_ID_RELEASE_r1p0 0x02
42 #define CACHE_ID_RELEASE_r2p0 0x04
43 #define CACHE_ID_RELEASE_r3p0 0x05
44 #define CACHE_ID_RELEASE_r3p1 0x06
45 #define CACHE_ID_RELEASE_r3p2 0x08
46 #define CACHE_ID_RELEASE_r3p3 0x09
48 #define CACHE_ID_PARTNUM_MASK 0xf
49 #define CACHE_ID_PARTNUM_VALUE 0x3
50 #define PL310_CACHE_TYPE 0x004
51 #define PL310_CTRL 0x100
52 #define CTRL_ENABLED 0x01
53 #define CTRL_DISABLED 0x00
54 #define PL310_AUX_CTRL 0x104
55 #define AUX_CTRL_MASK 0xc0000fff
58 #define AUX_CTRL_WAY_SIZE_MASK (0x7 << 17)
65 #define PL310_TAG_RAM_CTRL 0x108
66 #define PL310_DATA_RAM_CTRL 0x10C
68 #define RAM_CTRL_WRITE_MASK (0x7 << 8)
70 #define RAM_CTRL_READ_MASK (0x7 << 4)
71 #define RAM_CTRL_SETUP_SHIFT 0
72 #define RAM_CTRL_SETUP_MASK (0x7 << 0)
73 #define PL310_EVENT_COUNTER_CTRL 0x200
74 #define EVENT_COUNTER_CTRL_ENABLED (1 << 0)
77 #define PL310_EVENT_COUNTER1_CONF 0x204
78 #define PL310_EVENT_COUNTER0_CONF 0x208
79 #define EVENT_COUNTER_CONF_NOINTR 0
82 #define EVENT_COUNTER_CONF_NOEV (0 << 2)
92 #define PL310_EVENT_COUNTER1_VAL 0x20C
93 #define PL310_EVENT_COUNTER0_VAL 0x210
94 #define PL310_INTR_MASK 0x214
95 #define PL310_MASKED_INTR_STAT 0x218
96 #define PL310_RAW_INTR_STAT 0x21C
97 #define PL310_INTR_CLEAR 0x220
99 #define INTR_MASK_ECNTR (1 << 0)
108 #define PL310_CACHE_SYNC 0x730
109 #define PL310_INV_LINE_PA 0x770
110 #define PL310_INV_WAY 0x77C
111 #define PL310_CLEAN_LINE_PA 0x7B0
112 #define PL310_CLEAN_LINE_IDX 0x7B8
113 #define PL310_CLEAN_WAY 0x7BC
114 #define PL310_CLEAN_INV_LINE_PA 0x7F0
115 #define PL310_CLEAN_INV_LINE_IDX 0x7F8
116 #define PL310_CLEAN_INV_WAY 0x7FC
117 #define PL310_LOCKDOWN_D_WAY(x) (0x900 + ((x) * 8))
118 #define PL310_LOCKDOWN_I_WAY(x) (0x904 + ((x) * 8))
119 #define PL310_LOCKDOWN_LINE_ENABLE 0x950
120 #define PL310_UNLOCK_ALL_LINES_WAY 0x954
121 #define PL310_ADDR_FILTER_STAR 0xC00
122 #define PL310_ADDR_FILTER_END 0xC04
123 #define PL310_DEBUG_CTRL 0xF40
124 #define DEBUG_CTRL_DISABLE_LINEFILL (1 << 0)
127 #define PL310_PREFETCH_CTRL 0xF60
128 #define PREFETCH_CTRL_OFFSET_MASK (0x1f)
136 #define PL310_POWER_CTRL 0xF80
138 #define POWER_CTRL_ENABLE_STANDBY (1 << 0)