Searched +full:0 +full:x100008 (Results 1 – 7 of 7) sorted by relevance
69 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;72 dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,73 <&mdma1 22 0x10 0x100008 0x0 0x0>;79 #size-cells = <0>;81 flash@0 {83 reg = <0>;
24 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */25 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */27 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */28 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */29 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */30 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */31 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */32 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */33 #define MCFINTC_IRLR 0x18 /* */34 #define MCFINTC_IACKL 0x19 /* */[all …]
24 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */25 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */27 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */28 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */29 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */30 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */31 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */32 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */33 #define MCFINTC_IRLR 0x18 /* */34 #define MCFINTC_IACKL 0x19 /* */[all …]
39 #define A_ELMER0_VERSION 0x10000040 #define A_ELMER0_PHY_CFG 0x10000441 #define A_ELMER0_INT_ENABLE 0x10000842 #define A_ELMER0_INT_CAUSE 0x10000c43 #define A_ELMER0_GPI_CFG 0x10001044 #define A_ELMER0_GPI_STAT 0x10001445 #define A_ELMER0_GPO 0x10001846 #define A_ELMER0_PORT0_MI1_CFG 0x40000048 #define S_MI1_MDI_ENABLE 061 #define M_MI1_SOF 0x3[all …]
123 int err, offset = 0x20; in platinumfb_set_par()125 if((err = platinum_var_to_par(&info->var, pinfo, 0))) { in platinumfb_set_par()136 offset = 0x10; in platinumfb_set_par()147 return 0; in platinumfb_set_par()153 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL in platinumfb_blank()155 * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due in platinumfb_blank()167 ctrl = le32_to_cpup(&info->platinum_regs->ctrl.r) | 0x33; in platinumfb_blank()173 ctrl &= ~0x30; in platinumfb_blank()177 return 0; in platinumfb_blank()216 return 0; in platinumfb_setcolreg()[all …]
29 // base address: 0x50f0030 …MCA_UMC_UMC0_MCUMC_STATUST0 0x03c231 …e regMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX 032 …MCA_UMC_UMC0_MCUMC_ADDRT0 0x03c433 …e regMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX 034 …MCA_UMC_UMC0_MCUMC_MISC0T0 0x03c635 …e regMCA_UMC_UMC0_MCUMC_MISC0T0_BASE_IDX 036 …MCA_UMC_UMC0_MCUMC_IPIDT0 0x03ca37 …e regMCA_UMC_UMC0_MCUMC_IPIDT0_BASE_IDX 038 …MCA_UMC_UMC0_MCUMC_SYNDT0 0x03cc[all …]
13 #define RISC_CNT_INC 0x0001000014 #define RISC_CNT_RESET 0x0003000015 #define RISC_IRQ1 0x0100000016 #define RISC_IRQ2 0x0200000017 #define RISC_EOL 0x0400000018 #define RISC_SOL 0x0800000019 #define RISC_WRITE 0x1000000020 #define RISC_SKIP 0x2000000021 #define RISC_JUMP 0x7000000022 #define RISC_SYNC 0x80000000[all …]