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/linux/drivers/net/can/softing/
H A Dsofting_cs.c30 .manf = 0x0168, .prod = 0x001,
34 .dpram_size = 0x0800,
35 .boot = {0x0000, 0x000000, fw_dir "bcard.bin",},
36 .load = {0x0120, 0x00f600, fw_dir "ldcard.bin",},
37 .app = {0x0010, 0x0d0000, fw_dir "cancard.bin",},
42 .manf = 0x0168, .prod = 0x002,
46 .dpram_size = 0x0800,
47 .boot = {0x0000, 0x000000, fw_dir "bcard.bin",},
48 .load = {0x0120, 0x00f600, fw_dir "ldcard.bin",},
49 .app = {0x0010, 0x0d0000, fw_dir "cancard.bin",},
[all …]
/linux/drivers/dma/dw-edma/
H A Ddw-edma-v0-regs.h15 #define EDMA_V0_VIEWPORT_MASK GENMASK(2, 0)
16 #define EDMA_V0_DONE_INT_MASK GENMASK(7, 0)
18 #define EDMA_V0_WRITE_CH_COUNT_MASK GENMASK(3, 0)
21 #define EDMA_V0_DOORBELL_CH_MASK GENMASK(2, 0)
22 #define EDMA_V0_LINKED_LIST_ERR_MASK GENMASK(7, 0)
25 #define EDMA_V0_CH_EVEN_MSI_DATA_MASK GENMASK(15, 0)
28 u32 ch_control1; /* 0x0000 */
29 u32 ch_control2; /* 0x0004 */
30 u32 transfer_size; /* 0x0008 */
32 u64 reg; /* 0x000c..0x0010 */
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
H A Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
H A Dimx6sll-pinfunc.h15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
H A Dimx95-pinfunc.h13 #define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0204 0x0610 0x00 0x00
14 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0204 0x0000 0x01 0x00
15 #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0204 0x0000 0x02 0x00
16 #define IMX95_PAD_DAP_TDI__CAN2_TX 0x0000 0x0204 0x0000 0x03 0x00
17 #define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x0000 0x0204 0x0000 0x04 0x00
18 #define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x0000 0x0204 0x0000 0x05 0x00
19 #define IMX95_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0204 0x0570 0x06 0x00
21 #define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0208 0x0614 0x00 0x00
22 #define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x0004 0x0208 0x0000 0x02 0x00
23 #define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x0004 0x0208 0x0000 0x04 0x00
[all …]
/linux/drivers/gpu/drm/ast/
H A Dast_dram_tables.h12 { 0x0108, 0x00000000 },
13 { 0x0120, 0x00004a21 },
14 { 0xFF00, 0x00000043 },
15 { 0x0000, 0xFFFFFFFF },
16 { 0x0004, 0x00000089 },
17 { 0x0008, 0x22331353 },
18 { 0x000C, 0x0d07000b },
19 { 0x0010, 0x11113333 },
20 { 0x0020, 0x00110350 },
21 { 0x0028, 0x1e0828f0 },
[all …]
/linux/drivers/media/i2c/
H A Dsony-btf-mpx.c21 MODULE_PARM_DESC(debug, "debug level 0=off(default) 1=on");
29 * IF/MPX address: 0x42/0x40 0x43/0x44
52 buffer[0] = dev; in mpx_write()
54 buffer[2] = addr & 0xff; in mpx_write()
56 buffer[4] = val & 0xff; in mpx_write()
58 msg.flags = 0; in mpx_write()
62 return 0; in mpx_write()
97 * For Asia, replace the 0x26XX in FM_PRESCALE with 0x14XX.
102 * 0x01 MAIN SUB
103 * 0x03 MAIN MAIN
[all …]
/linux/include/linux/mfd/
H A Dlochnagar2_regs.h15 #define LOCHNAGAR2_CDC_AIF1_CTRL 0x000D
16 #define LOCHNAGAR2_CDC_AIF2_CTRL 0x000E
17 #define LOCHNAGAR2_CDC_AIF3_CTRL 0x000F
18 #define LOCHNAGAR2_DSP_AIF1_CTRL 0x0010
19 #define LOCHNAGAR2_DSP_AIF2_CTRL 0x0011
20 #define LOCHNAGAR2_PSIA1_CTRL 0x0012
21 #define LOCHNAGAR2_PSIA2_CTRL 0x0013
22 #define LOCHNAGAR2_GF_AIF3_CTRL 0x0014
23 #define LOCHNAGAR2_GF_AIF4_CTRL 0x0015
24 #define LOCHNAGAR2_GF_AIF1_CTRL 0x0016
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt8186-topckgen.c22 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2, 0),
23 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2, 0),
24 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4, 0),
25 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16, 0),
26 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
27 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2, 0),
28 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4, 0),
29 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
30 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
31 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
[all …]
/linux/drivers/media/platform/chips-media/wave5/
H A Dwave5-regdefine.h12 W5_INIT_VPU = 0x0001,
13 W5_WAKEUP_VPU = 0x0002,
14 W5_SLEEP_VPU = 0x0004,
15 W5_CREATE_INSTANCE = 0x0008, /* queuing command */
16 W5_FLUSH_INSTANCE = 0x0010,
17 W5_DESTROY_INSTANCE = 0x0020, /* queuing command */
18 W5_INIT_SEQ = 0x0040, /* queuing command */
19 W5_SET_FB = 0x0080,
20 W5_DEC_ENC_PIC = 0x0100, /* queuing command */
21 W5_ENC_SET_PARAM = 0x0200, /* queuing command */
[all …]
/linux/drivers/s390/char/
H A Dsclp_ap.c15 #define SCLP_CMDW_CONFIGURE_AP 0x001f0001
16 #define SCLP_CMDW_DECONFIGURE_AP 0x001e0001
35 cmd |= (apid & 0xFF) << 8; in do_ap_configure()
40 case 0x0020: case 0x0120: case 0x0440: case 0x0450: in do_ap_configure()
43 pr_warn("configure AP adapter %u failed: cmd=0x%08x response=0x%04x\n", in do_ap_configure()
H A Dsclp_cmd.c34 #define SCLP_CMDW_ASSIGN_STORAGE 0x000d0001
35 #define SCLP_CMDW_UNASSIGN_STORAGE 0x000c0001
46 return sclp_sync_request_timeout(cmd, sccb, 0); in sclp_sync_request()
75 pr_warn("sync request failed (cmd=0x%08x, status=0x%02x)\n", in sclp_sync_request_timeout()
88 #define SCLP_CMDW_CONFIGURE_CPU 0x00110001
89 #define SCLP_CMDW_DECONFIGURE_CPU 0x00100001
104 sccb->header.control_mask[2] = 0x80; in _sclp_get_core_info()
109 if (sccb->header.response_code != 0x0010) { in _sclp_get_core_info()
110 pr_warn("readcpuinfo failed (response=0x%04x)\n", in _sclp_get_core_info()
144 case 0x0020: in do_core_configure()
[all …]
/linux/arch/s390/include/asm/
H A Dlowcore.h22 #define LOWCORE_ALT_ADDRESS _AC(0x70000, UL)
31 __u8 pad_0x0000[0x0014-0x0000]; /* 0x0000 */
32 __u32 ipl_parmblock_ptr; /* 0x0014 */
33 __u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */
34 __u32 ext_params; /* 0x0080 */
37 __u16 ext_cpu_addr; /* 0x0084 */
38 __u16 ext_int_code; /* 0x0086 */
42 __u32 svc_int_code; /* 0x0088 */
45 __u16 pgm_ilc; /* 0x008c */
46 __u16 pgm_code; /* 0x008e */
[all …]
/linux/sound/soc/codecs/
H A Dmax98373-sdw.h10 #define MAX98373_R0040_SCP_INIT_STAT_1 0x0040
11 #define MAX98373_R0041_SCP_INIT_MASK_1 0x0041
12 #define MAX98373_R0042_SCP_INIT_STAT_2 0x0042
13 #define MAX98373_R0044_SCP_CTRL 0x0044
14 #define MAX98373_R0045_SCP_SYSTEM_CTRL 0x0045
15 #define MAX98373_R0046_SCP_DEV_NUMBER 0x0046
16 #define MAX98373_R0050_SCP_DEV_ID_0 0x0050
17 #define MAX98373_R0051_SCP_DEV_ID_1 0x0051
18 #define MAX98373_R0052_SCP_DEV_ID_2 0x0052
19 #define MAX98373_R0053_SCP_DEV_ID_3 0x0053
[all …]
/linux/include/linux/
H A Di8042.h13 #define I8042_CMD_CTL_RCTR 0x0120
14 #define I8042_CMD_CTL_WCTR 0x1060
15 #define I8042_CMD_CTL_TEST 0x01aa
17 #define I8042_CMD_KBD_DISABLE 0x00ad
18 #define I8042_CMD_KBD_ENABLE 0x00ae
19 #define I8042_CMD_KBD_TEST 0x01ab
20 #define I8042_CMD_KBD_LOOP 0x11d2
22 #define I8042_CMD_AUX_DISABLE 0x00a7
23 #define I8042_CMD_AUX_ENABLE 0x00a8
24 #define I8042_CMD_AUX_TEST 0x01a9
[all …]
/linux/arch/arm/mach-rockchip/
H A Dpm.h28 #define RK3288_PMU_WAKEUP_CFG0 0x00
29 #define RK3288_PMU_WAKEUP_CFG1 0x04
30 #define RK3288_PMU_PWRMODE_CON 0x18
31 #define RK3288_PMU_OSC_CNT 0x20
32 #define RK3288_PMU_PLL_CNT 0x24
33 #define RK3288_PMU_STABL_CNT 0x28
34 #define RK3288_PMU_DDR0IO_PWRON_CNT 0x2c
35 #define RK3288_PMU_DDR1IO_PWRON_CNT 0x30
36 #define RK3288_PMU_CORE_PWRDWN_CNT 0x34
37 #define RK3288_PMU_CORE_PWRUP_CNT 0x38
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7925/
H A Dregs.h9 #define MT_MDP_BASE 0x820cc800
12 #define MT_MDP_DCR0 MT_MDP(0x000)
16 #define MT_MDP_DCR1 MT_MDP(0x004)
19 #define MT_MDP_BNRCFR0(_band) MT_MDP(0x090 + ((_band) << 8))
24 #define MT_MDP_BNRCFR1(_band) MT_MDP(0x094 + ((_band) << 8))
28 #define MT_MDP_TO_HIF 0
31 #define MT_WFDMA0_HOST_INT_ENA MT_WFDMA0(0x228)
32 #define MT_WFDMA0_HOST_INT_DIS MT_WFDMA0(0x22c)
65 #define MT_RX_DATA_RING_BASE MT_WFDMA0(0x500)
67 #define MT_INFRA_CFG_BASE 0xd1000
[all …]
/linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop_reg.h11 #define RK3288_REG_CFG_DONE 0x0000
12 #define RK3288_VERSION_INFO 0x0004
13 #define RK3288_SYS_CTRL 0x0008
14 #define RK3288_SYS_CTRL1 0x000c
15 #define RK3288_DSP_CTRL0 0x0010
16 #define RK3288_DSP_CTRL1 0x0014
17 #define RK3288_DSP_BG 0x0018
18 #define RK3288_MCU_CTRL 0x001c
19 #define RK3288_INTR_CTRL0 0x0020
20 #define RK3288_INTR_CTRL1 0x0024
[all …]
/linux/drivers/clk/samsung/
H A Dclk-exynos7885.c27 /* Register Offset definitions for CMU_TOP (0x12060000) */
28 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
29 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
30 #define PLL_CON0_PLL_SHARED0 0x0100
31 #define PLL_CON0_PLL_SHARED1 0x0120
32 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
33 #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
34 #define CLK_CON_MUX_MUX_CLKCMU_CORE_G3D 0x101c
35 #define CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS 0x1028
36 #define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD 0x102c
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dusb-drd.yaml19 0x0200 or above.
21 enum: [0x0100, 0x0120, 0x0130, 0x0200]
71 reg = <0x4a030000 0xcfff>;
72 interrupts = <0 92 4>;
77 otg-rev = <0x0200>;
/linux/drivers/media/cec/platform/s5p/
H A Dregs-cec.h16 #define S5P_CEC_STATUS_0 (0x0000)
17 #define S5P_CEC_STATUS_1 (0x0004)
18 #define S5P_CEC_STATUS_2 (0x0008)
19 #define S5P_CEC_STATUS_3 (0x000C)
20 #define S5P_CEC_IRQ_MASK (0x0010)
21 #define S5P_CEC_IRQ_CLEAR (0x0014)
22 #define S5P_CEC_LOGIC_ADDR (0x0020)
23 #define S5P_CEC_DIVISOR_0 (0x0030)
24 #define S5P_CEC_DIVISOR_1 (0x0034)
25 #define S5P_CEC_DIVISOR_2 (0x0038)
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am642-evm-icssg1-dualemac.dtso24 #size-cells = <0>;
26 mdio@0 {
27 reg = <0x0>;
29 #size-cells = <0>;
43 AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
44 AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
45 AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
46 AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
47 AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
48 AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
[all …]
/linux/drivers/net/dsa/microchip/
H A Dksz_ptp_reg.h9 #define REG_SW_GLOBAL_LED_OVR__4 0x0120
11 #define LED_OVR_1 BIT(0)
13 #define REG_SW_GLOBAL_LED_SRC__4 0x0128
18 #define REG_PTP_CLK_CTRL 0x0500
26 #define PTP_CLK_RESET BIT(0)
28 #define REG_PTP_RTC_SUB_NANOSEC__2 0x0502
30 #define PTP_RTC_SUB_NANOSEC_M 0x0007
31 #define PTP_RTC_0NS 0x00
33 #define REG_PTP_RTC_NANOSEC 0x0504
35 #define REG_PTP_RTC_SEC 0x0508
[all …]

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