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/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-npcm730-gsj-gpio.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 gpio0pp_pins: gpio0pp-pins {
7 pins = "GPIO0/IOX1DI";
8 bias-disable;
9 drive-push-pull;
11 gpio1pp_pins: gpio1pp-pins {
12 pins = "GPIO1/IOX1LD";
13 bias-disable;
14 drive-push-pull;
16 gpio2pp_pins: gpio2pp-pins {
[all …]
H A Dnuvoton-npcm750-runbmc-olympus-pincfg.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 gpio0ol_pins: gpio0ol-pins {
7 pins = "GPIO0/IOX1DI";
8 bias-disable;
9 output-low;
11 gpio1ol_pins: gpio1ol-pins {
12 pins = "GPIO1/IOX1LD";
13 bias-disable;
14 output-low;
16 gpio2ol_pins: gpio2ol-pins {
[all …]
H A Dnuvoton-npcm730-kudo.dts1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
5 #include "nuvoton-npcm730.dtsi"
7 #include <dt-bindings/gpio/gpio.h>
41 stdout-path = &serial3;
48 iio-hwmon {
49 compatible = "iio-hwmon";
50 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
55 compatible = "nuvoton,npcm750-jtag-master";
56 #address-cells = <1>;
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dbrcm,bcm6368-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/brcm,bcm6368-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
14 Bindings for Broadcom's BCM6368 memory-mapped pin controller.
18 const: brcm,bcm6368-pinctrl
24 '-pins$':
26 $ref: pinmux-node.yaml#
[all …]
H A Dbrcm,bcm6362-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/brcm,bcm6362-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
14 Bindings for Broadcom's BCM6362 memory-mapped pin controller.
18 const: brcm,bcm6362-pinctrl
24 '-pins$':
26 $ref: pinmux-node.yaml#
[all …]
H A Dbrcm,bcm63268-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/brcm,bcm63268-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
14 Bindings for Broadcom's BCM63268 memory-mapped pin controller.
18 const: brcm,bcm63268-pinctrl
24 '-pins$':
26 $ref: pinmux-node.yaml#
[all …]
H A Dbrcm,bcm6318-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/brcm,bcm6318-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
14 Bindings for Broadcom's BCM6318 memory-mapped pin controller.
18 const: brcm,bcm6318-pinctrl
24 '-pins$':
26 $ref: pinmux-node.yaml#
[all …]
H A Dbrcm,bcm6328-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/brcm,bcm6328-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
14 Bindings for Broadcom's BCM6328 memory-mapped pin controller.
18 const: brcm,bcm6328-pinctrl
24 '-pins$':
26 $ref: pinmux-node.yaml#
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dbrcm,bcm6368-gpio-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/brcm,bcm6368-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
15 for controlling the GPIO and pins of the SoC.
18 "#address-cells": true
20 "#size-cells": true
24 - const: brcm,bcm6368-gpio-sysctl
[all …]
H A Dbrcm,bcm6362-gpio-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/brcm,bcm6362-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
15 for controlling the GPIO and pins of the SoC.
18 "#address-cells": true
20 "#size-cells": true
24 - const: brcm,bcm6362-gpio-sysctl
[all …]
H A Dbrcm,bcm63268-gpio-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/brcm,bcm63268-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
15 for controlling the GPIO and pins of the SoC.
18 "#address-cells": true
20 "#size-cells": true
24 - const: brcm,bcm63268-gpio-sysctl
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynosautov920-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's ExynosAutov920 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov920 SoC pin-mux and pin-config options are listed as
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "exynos-pinctrl.h"
16 gpa0: gpa0-gpio-bank {
17 gpio-controller;
18 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
[all …]
H A Dexynosautov9-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's ExynosAutov9 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov9 SoC pin-mux and pin-config options are listed as
11 #include "exynos-pinctrl.h"
14 gpa0: gpa0-gpio-bank {
15 gpio-controller;
16 #gpio-cells = <2>;
17 interrupt-controller;
18 #interrupt-cells = <2>;
19 interrupt-parent = <&gic>;
[all …]
H A Dexynos7885-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos7885 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "exynos-pinctrl.h"
16 etc0: etc0-gpio-bank {
17 gpio-controller;
18 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
[all …]
/linux/arch/mips/boot/dts/mobileye/
H A Deyeq5-pins.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
9 timer0_pins: timer0-pins {
11 pins = "PA0", "PA1";
13 timer1_pins: timer1-pins {
15 pins = "PA2", "PA3";
17 timer2_pins: timer2-pins {
19 pins = "PA4", "PA5";
21 pps0_pins: pps0-pin {
23 pins = "PA4";
25 pps1_pins: pps1-pin {
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Ds3c64xx-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 * - pin control-related definitions
8 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
12 #include "s3c64xx-pinctrl.h"
19 gpa: gpa-gpio-bank {
20 gpio-controller;
21 #gpio-cells = <2>;
22 interrupt-controller;
23 #interrupt-cells = <2>;
26 gpb: gpb-gpio-bank {
[all …]
H A Ds5pv210-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's S5PV210 SoC device tree source - pin control-related
6 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
11 * Samsung's S5PV210 SoC pin banks, pin-mux and pin-config options are
15 #include "s5pv210-pinctrl.h"
18 pin- ## _pin { \
19 samsung,pins = #_pin; \
20 samsung,pin-con-pdn = <S5PV210_PIN_PDN_ ##_mode>; \
21 samsung,pin-pud-pdn = <S5PV210_PIN_PULL_ ##_pull>; \
25 gpa0: gpa0-gpio-bank {
[all …]
H A Dexynos4x12-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
16 samsung,pins = #_pin; \
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
22 gpa0: gpa0-gpio-bank {
23 gpio-controller;
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-base-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 /omit-if-no-ref/
16 auddsm_pins: auddsm-pins {
17 rockchip,pins =
30 /omit-if-no-ref/
31 bt1120_pins: bt1120-pins {
32 rockchip,pins =
71 /omit-if-no-ref/
[all …]
H A Drk3568-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 /omit-if-no-ref/
16 acodec_pins: acodec-pins {
17 rockchip,pins =
36 /omit-if-no-ref/
37 audiopwm_lout: audiopwm-lout {
38 rockchip,pins =
43 /omit-if-no-ref/
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-iot2050-arduino-connector.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) Siemens AG, 2018-2023
13 pinctrl-names =
15 "d0-uart0-rxd", "d0-gpio", "d0-gpio-pullup", "d0-gpio-pulldown",
16 "d1-uart0-txd", "d1-gpio", "d1-gpio-pullup", "d1-gpio-pulldown",
17 "d2-uart0-ctsn", "d2-gpio", "d2-gpio-pullup", "d2-gpio-pulldown",
18 "d3-uart0-rtsn", "d3-gpio", "d3-gpio-pullup", "d3-gpio-pulldown",
19 "d10-spi0-cs0", "d10-gpio", "d10-gpio-pullup", "d10-gpio-pulldown",
20 "d11-spi0-d0", "d11-gpio", "d11-gpio-pullup", "d11-gpio-pulldown",
21 "d12-spi0-d1", "d12-gpio", "d12-gpio-pullup", "d12-gpio-pulldown",
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8064-pins.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 sdcc1_default_state: sdcc1-default-state {
5 clk-pins {
6 pins = "sdc1_clk";
7 drive-strength = <16>;
8 bias-disable;
11 cmd-pins {
12 pins = "sdc1_cmd";
13 drive-strength = <10>;
14 bias-pull-up;
[all …]
/linux/arch/arm64/boot/dts/exynos/google/
H A Dgs101-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * GS101 SoC pin-mux and pin-config device tree source
5 * Copyright 2019-2023 Google LLC
6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
9 #include "gs101-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
15 interrupt-controller;
16 #interrupt-cells = <2>;
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drv1126-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <arm64/rockchip/rockchip-pinconf.dtsi>
15 /omit-if-no-ref/
16 clk_out_ethernetm1_pins: clk-out-ethernetm1-pins {
17 rockchip,pins =
23 /omit-if-no-ref/
24 emmc_rstnout: emmc-rstnout {
25 rockchip,pins =
29 /omit-if-no-ref/
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhikey970-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/pinctrl/hisi.h>
10 range: gpio-range {
11 #pinctrl-single,gpio-range-cells = <3>;
15 compatible = "pinctrl-single";
17 #pinctrl-cells = <1>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
21 /* pin base, nr pins & gpio function */
[all …]

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